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| Ordering number : *EN5572 CMOS LSI LC897194 CD-ROM Decoder with Built-In ATAPI (IDE) and DVD ECC Interfaces Preliminary Overview The LC897194 provides CD-ROM functionality and includes built-in DVD ECC and ATAPI (IDE) interfaces. Package Dimensions unit: mm 3214-SQFP144 [LC897194] Function * CD-ROM ECC functionality, an ATAPI (IDE) interface (the register and other blocks), and a DVD ECC interface Features * ATAPI (IDE) interface * DVD ECC interface * Supports up to 12x-speed playback (when using 70-ns 16-bit data path DRAM) * Transfer rate: 16.6 MB/s (when using 60-ns 16-bit data path DRAM) * Transfer rate: 8.33 MB/s (when using 70-ns 8-bit data path DRAM) * Between 1 and 32 Mbits of DRAM can be used as buffer RAM. * The user can freely set up the CD main channel and the C2 flags in buffer RAM. * Built-in batch transfer function (function for transferring the CD main channel and the C2 flags in one operation) * Built-in multiple transfer function (function for automatically transferring multiple blocks in a single operation) SANYO: SQFP144 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistance (pins only) Maximum I/O power Note: Per basic I/O cell. II, IO max Symbol VDD max VI, VO Pd max Topr Tstg 10 seconds Ta = 25C Ta 70C Conditions Ta = 25C Ratings -0.3 to +7.0 -0.3 to VDD +0.3 550 -30 to +70 -55 to +125 235 20* Unit V V mW C C C mA SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT) No. 5572-1/11 LC897194 Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Input leakage current Output leakage current Pull-up resistance Pull-down resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 VIH5 VIL5 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL5 IIL IOZ RUP RDN Applicable pins (see below) TTL compatible: (1) TTL compatible: (1) TTL compatible, with pull-up resistor: (12) TTL compatible, with pull-up resistor: (12) TTL compatible, with pull-down resistor: (2) TTL compatible, with pull-down resistor: (2) TTL compatible, Schmitt characteristics: (3), (5), (13), (14) TTL compatible, Schmitt characteristics: (3), (5), (13), (14) CMOS compatible, Schmitt characteristics: (4) CMOS compatible, Schmitt characteristics: (4) IOH = -2 mA : (7), (10), (12) IOL = 2 mA : (7), (10), (12) IOH = -8 mA : (6) IOL = 8 mA : (6) IOH = -4 mA : (8), (13) IOL = 24 mA : (8), (13) IOL = 24 mA : (9), (14) IOL = 2 mA : (11) VI = VSS, VDD : (1), (2), (3), (4), (5), (12), (13), (14) When the output is high impedance: (9), (11), (13), (14) (12) (2) -10 -10 40 40 80 80 VDD - 2.1 0.4 0.4 0.4 +10 +10 160 160 VDD - 2.1 0.4 VDD - 2.1 0.4 0.8 VDD 0.2 VDD 2.5 0.6 2.2 0.8 2.2 0.8 Ratings min 2.2 0.8 typ max Unit V V V V V V V V V V V V V V V V V V A A k k Note: The applicable pins are as follows: INPUT (1) CSCTRL, RSSEL, HDB0 to 7, SUA0 to 6 (2) TEST0 to 4 (3) ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA, DA0 to 2, ZCS1FX, ZCS3FX (4) ZCS, ZRD, ZWR (5) ZDIOR, ZDIOW, DRESP, WFCK, SCOR OUTPUT (6) MCK, MCK2 (7) ZINT0, ZINT1 (8) DMARQ, HINTRQ (9) IORDY, ZIOCS16 (10) RA0 to 9, ZCAS0 to 1, ZRAS0 to 1, ZLWE, ZUWE, ZOE, DREQ (11) ZRSTCPU, ZRSTIC, ZSWAIT INOUT (12) D0 to 7, IO0 to 15 (13) DD0 to 15 (14) ZDASP, ZPDIAG *: The DC characteristics do not apply to the XTAL and XTALCK pins. No. 5572-2/11 LC897194 Recommended Oscillator Circuit Example R1 = 120 k R2 = 47 C1 = 30 pF With a crystal with a resonant frequency of 16.9344 MHz, or: R1 = 3.3 k R2 = None C1 = 5 pF With a crystal with a resonant frequency of 33.8688 MHz. If third harmonics are a problem in the 33.8688-MHz recommended circuit, consult with the manufacturer of the crystal for exact component values, since those values will be influenced by the printed circuit board used. No. 5572-3/11 LC897194 Block Diagram *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 **1 BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE DREQ HDB0 to HDB7, DRESP WFCK, SCOR HISIDE (WD25C32) is made by WESTERN DIGITAL. No. 5572-4/11 LC897194 Pin Functions typ I O Input Output B P Bidirection Power NC Not connected Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol VSS0 ZRAS0 ZRAS1 VSS0 ZCAS0 ZCAS1 VSS0 ZOE ZUWE ZLWE RA0 RA1 RA2 RA3 RA4 RA5 RA6 VDD VSS0 RA7 RA8 RA9 TEST0 TEST1 TEST2 TEST3 TEST4 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 VSS0 VDD Type P O O P O O P O O O O O O O O O O P P O O O NC NC NC NC NC B B B B B B B B P P Data I/O to/from data buffer DRAM Pull-up resistors are built in. RA0 to RA9 are used for the data buffer DRAM address. Buffer RAM output enable Buffer RAM upper write enable Buffer RAM lower write enable RA0 to RA9 are used for the data buffer DRAM address. Function RAS signal output 0 to the buffer DRAM (Output 0 is normally used.) RAS signal output 1 to the buffer DRAM CAS signal output 0 to the buffer DRAM (Output 0 is normally used.) CAS signal output 1 to the buffer DRAM Used for testing. There should be no connections to these pins. These pins must be left open. Continued on next page. No. 5572-5/11 LC897194 Continued from preceding page. Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Symbol IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 VSS0 WFCK SCOR VSS0 DREQ DRESP HDB7 HDB6 VDD VSS0 HDB5 HDB4 HDB3 HDB2 HDB1 HDB0 SDATA BCK LRCK C2PO MCK2 CSCTRL RSSEL VSS0 XTALCK XTAL VSS0 VDD MCK VSS0 ZRSTIC ZRESET ZRD ZWR ZCS ZINT1 ZINT0 Type B B B B B B B B P I I P O I I I P P I I I I I I I I I I O I I P I O P P O P O I I I I O O Reset output to the driver reset IC LSI reset input Microcontroller data read signal input Microcontroller data write signal input Register chip select signal input from the microcontroller ATAPI block interrupt output (selected by a register) Interrupt request signal output to the microcontroller Outputs the XTALCK signal times 1/1 or 1/2, or stopped. Crystal oscillator circuit input Crystal oscillator circuit output Outputs the XTALCK signal times 1/1, 1/2, or 1/512, or stopped. Microcontroller chip select signal active high or low selection Direct or indirect addressing selection Interface with the CD digital signal processor DVD ECC data input DVD ECC data request output DVD ECC data latch signal input DVD ECC data input Subcode input Subcode input Data I/O to/from data buffer DRAM Pull-up resistors are built in. Function Continued on next page. No. 5572-6/11 LC897194 Continued from preceding page. Pin No. 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Symbol SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD VSS0 D0 D1 D2 D3 D4 D5 D6 D7 VSS0 ZRSTCPU ZSWAIT ZHRST ZDASP ZCS3FX ZCS1FX DA2 VSS0 VDD DA0 ZPDIAG DA1 ZIOCS16 HINTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ DD15 VSS1 DD0 DD14 DD1 Type I I I I I I I P P B B B B B B B B P O O I B I I I P P I B I O O I P O I I O B P B B B ATAPI data bus ATAPI data bus ATAPI control signals ATAPI control signals Reset signal output to the CPU WAIT signal output to the microcontroller ATAPI control signals Microcontroller data signals Pull-up resistors are built in. Microcontroller register selection signals The SUA0 pin functions as RS in indirect address mode. Function Continued on next page. No. 5572-7/11 LC897194 Continued from preceding page. Pin No. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Symbol VDD VSS1 DD13 DD2 DD12 DD3 VSS1 DD11 DD4 DD10 VSS1 VDD DD5 DD9 DD6 VSS1 DD8 DD7 VDD Type P P B B B B P B B B P P B B B P B B P ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus Function NC pins must be left open. Make no connections to these pins. Pin symbols that start with the letter Z are negative logic signals. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. No. 5572-8/11 LC897194 Pin Descriptions 1. ATAPI Pins ZCS1FX (input) Chip select signal used to select the command block register. ZCS3FX (input) Chip select signal used to select the control block register. DA0 to DA2 (input) Address used to access the ATAPI registers. ZDASP(input/output) Drive 1 is output, drive 0 is input. Signal used to indicate to drive 0 that drive 1 exists. An external pull-up resistor must be provided. DD0 to DD15 (input/output) Data bus with a width of 16 bits. Data can be transferred in 8-bit and 16-bit units. ZDIOR (input) Read strobe signal from the host. ZDIOW (input) Write strobe signal from the host. ZDMACK (input) Acknowledge signal from the host in response to a drive DMARQ request signal during DMA transfers. There is no internal pull-up resistor in the pin circuit. DMARQ (output) Drive request signal during DMA transfers. HINTRQ (output) Drive interrupt signal sent to the host. ZIOCS16 (output) This signal is asserted by the drive when the drive can support 16-bit transfers. This signal is not asserted during DMA transfers. IORDY (output) Signal that indicates that the drive has completed response preparation during data transfers. This signal will be low when preparation has not completed. ZPDIAG (input/output) Signal asserted by drive 1 to inform drive 0 that the diagnostics have completed. An external pull-up resistor must be provided. ZHRST (input) Reset signal from the host. There is no internal pull-up resistor in the pin circuit. 2. Microcontroller Interface Pins ZCS (input) Chip select signal from the microcontroller. CSCTRL (input) Signal that selects the logic of the chip select from the microcontroller. High - The ZCS signal functions as an active-low signal. Low - The ZCS signal functions as an active-high signal. ZRD, ZWR, SUA0 to SUA6 (input) Microcontroller interface control pins. The SUA0 to SUA6 pins are used for addressing. SUA0 functions as RS (the register select pin) in indirect addressing. When SUA0 is low, and address read or write operation is performed, and when high, a data read or write operation is performed. RSSEL (input) Signal that selects direct or indirect addressing. High - Indirect addressing selected. Low - Direct addressing selected. ZSWAIT (output) When the microcontroller is accessing RAM, the sub-CPU must wait when this pin is low. D7 to D0 (input/output) Microcontroller data bus. Pull-up resistors are built in. ZINT0 (output) Interrupt request signal to the microcontroller. The active level (high or low) can be changed by setting a register. The default setting is active low. ZINT1 (output) Interrupt request signal from the IDE block to the microcontroller. No. 5572-9/11 LC897194 3. Buffer RAM Pins IO0 to IO15 (input/output) Data bus for the buffer DRAM. Pull-up resistors are built in. RA0 to RA9 (output) Buffer RAM address pins. ZRAS0, ZRAS1 (ZCS0, ZCS1) (output) Buffer DRAM RAS output pins. Although ZRAS0 is used normally, in applications that use two 1M (64K x 16 bits) DRAMs, the ZRAS0 and ZRAS1 signals can be connected to each of DRAM RAS pins. ZCAS0, ZCAS1 (output) Buffer DRAM CAS output pins. Although ZCAS0 is used normally, in applications that use two-CAS DRAMs, the ZCAS0 can be connected to the DRAM UCAS pin, and ZCAS1 to the DRAM LCAS pin. ZOE (output) The buffer DRAM read output pin. ZUWE, ZLWE (output) Buffer DRAM write output signals. Connect these pins to the corresponding pins on the DRAMs. When two-CAS DRAMs are used, connect ZLWE to the write enable signal. 4. Subcode Interface Pins WFCK, SCOR (input) Subcode interface pins. By connecting these pins to the CD DSP, the subcode sync can be detected and the CD main channel buffering can be started according to that sync. Subcode data buffering and ECC are not performed. 5. CD DSP Data Pins BCK, SDATA, LRCK, C2PO (input) Connect these pins to the CD DSP to acquire the CD-ROM data. C2PO is the C2 flag pin. 6. DVD ECC interface pins DRESP (input) DVD ECC data is latched on the falling edge of this signal. HDB0 to HDB7 (input) DVD ECC data input pins. DREQ (output) DVD ECC data request output. 7. Other Pins ZRESET (input) The LC897194 reset pin. The LSI is reset when a low level is applied. Applications must hold this pin low for at least 1 s when power is first applied. XTALCK, XTAL These pins drive an external crystal at either 16.9344 MHz or 33.8688 MHz. An external clock frequency can also be input to the XTALCK pin. MCK (output) Outputs either the XTALCK frequency or that frequency divided by 2. This output can be stopped. MCK2 (output) Outputs either the XTALCK frequency or that frequency divided by 2 (with the opposite phase of the MCK pin) or the XTALCK frequency divided by 512. This output can be stopped. ZRSTIC (output) This pin can be set to output a low level by either setting bit 7 in the microcontroller register R46 (ZSYSRES) low (0), or setting the ZHRST pin (pin 103) low. This pin output is in the high-impedance state when both ZSYSRES and ZHRST are high. Since this pin has an open-drain circuit, an external pull-up resistor must be provided. ZRSTCPU (output) A low-going pulse of about 1 ms (when XTALCK = 34 MHz, or about 2 ms when XTALCK = 16 MHz) is generated on this pin when an ATAPI soft reset command (08H) is received. An interrupt is issued to the microcontroller at this time. If the ZRESET pin (pin 77) is functioning with activelow logic, the ZRESET signal is output without change to ZRSTCPU. Since this pin has an open-drain circuit, an external pull-up resistor must be provided. No. 5572-10/11 LC897194 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5572-11/11 |
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