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| CXA2571N RF Matrix Amplifier Description The CXA2571N is an IC developed for the RF signal processing of compact disc players. Features * Wide band RF signal processing * RF system VCA circuit * RF system equalizer (supports CAV mode) * Supports pickups with built-in RF summing amplifier * Low power consumption mode (EQ Pass mode) * RW/ROM switching mode * Center error amplifier * Output DC level shift circuit Functions * RFAC summing amplifier, equalizer, VCA * RFDC summing amplifier * Focus error amplifier * Tracking error amplifier * Automatic power control * VC buffer amplifier (analog system, digital system) Applications CD-ROM/RW compatible systems Structure Bipolar silicon monolithic IC 30 pin SSOP (Plastic) Absolute Maximum ratings * Supply voltage Vcc * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD 7 V -20 to +75 C -65 to +150 C 620 mW Operating Conditions * Supply voltage Vcc - GND 3.0 to 5.5 V * Operating temperature Topr -20 to +75 C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98260A98-PS CXA2571N Connected Circuit Diagram 0.1 VCC A VC B VC A B C D 10k DVC AVC RW/ROM A D VC AVC VOFST DVC Bottom Hold RW/ROM DVCC CEP CE CE B C VC SW PD LD VCC VC GND VCC VCC GND APC Bottom Hold APC-OFF (Hi-Z) RW/ROM (H/L) VCC AVC r_adj CEM CET DVCC DVC VCC AVC DVC VC -2- CXA2571N Pin Description Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol LD PD EQ_IN AC_SUM GND A B C D E F SW CET CEP DVCC RFAC DVC FE FEI TE CE CEM VCC RFG BST VFC RFC VC RFDCO RFDCI I/O Out In In Out In In In In In In In In In -- In Out Out Out -- Out Out -- In In In In In Out Out -- APC amplifier output. APC amplifier input. RFAC system VCA block and EQ block input. RFAC system RF SUM output. Ground. A signal input. B signal input. C signal input. D signal input. E signal input. F signal input. Mode switching signal input. CE system hold time constant adjustment. CE amplifier non-inverted input. DVCC. RFAC signal output. DVC output. Focus error signal output. FE amplifier virtual ground. Tracking error signal output. Center error signal output. CE amplifier virtual ground. VCC. RFAC system VCA block low-frequency gain adjustment. EQ boost amount adjustment range. EQ cut-off frequency adjustment. EQ cut-off frequency adjustment. VC voltage output. RFDC signal output. RFDC amplifier virtual ground. Description -3- CXA2571N Pin Description and Equivalent Circuit Pin No. Symbol I/O Equivalent circuit Description 10k 1 LD O 1 1k APC amplifier output. 2 PD I 55k 20k 2 20k APC amplifier input. 1.1k 1.1k 3 EQ_IN I 3 5k VC 1.2k Equalizer circuit input. 5k VC 1.6k 1.6k 4 AC_SUM O 4 RFAC summing amplifier output. 5 GND -- -- Ground. -4- CXA2571N Pin No. Symbol I/O Equivalent circuit Description 6 A I 15k 6 7 B I 7 100A 100A 30k RF summing amplifier and focus error amplifier input. 8 C I 8 100A 9 100A 47k VC 47k 9 D I 10 E I 27k 10 27k Tracking error amplifier input. 124 20 11 F I 11 20 TE O 200k 200k Tracking error amplifier output. 12 SW I 12 200k CD-ROM/RW switching input. RW when connected to VCC, ROM when connected to GND. Power supply. 15 VCC -- -- 100 16 RFAC O 2mA 16 RFAC amplifier output. 17 DVC O 150k 25 17 150k (DVCC + GND)/2 voltage output. -5- CXA2571N Pin No. 18 Symbol I/O Equivalent circuit Description FE O 50k VC 124 18 124 19 Focus error amplifier output. Focus error amplifier gain adjustment. The gain is adjusted by the external resistance value connected between this pin and Pin 18. 19 FEI I 13 CET I 76k 4k 124 13 Center error amplifier time constant adjustment. 14 CEP I 22 124 40k 124 21 40k 14 Center error amplifier noninverted input. 21 CE O Center error amplifier input. 22 23 CEM VCC I -- 124 Center error amplifier inverted input. -- VCC. (AVCC) 20k 24 RFG I 24 VC 100A Sets the RFAC low-frequency gain. 50A 25 BST I 20k 25 VC Input for adjusting the equalizer circuit boost amount. 20k 26 VFC I 26 VC 100A Input for adjusting the equalizer circuit boost frequency with the control voltage. -6- CXA2571N Pin No. Symbol I/O Equivalent circuit Description 1.0V 124 27 RFC I 27 Input for adjusting the equalizer circuit boost frequency with external resistance. 28 VC O 150k 25 28 150k (VCC + GND)/2 voltage output. 29 RFDC O 1.5k VC 1mA 29 124 RFDC amplifier output. This pin serves as the eye pattern check point. RFDC amplifier gain adjustment. The gain is adjusted by the external resistance value connected between this pin and Pin 29. 30 RFDCI I 124 30 -7- Electrical Characteristics Switch conditions S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1 E2 0V 0V Pin current Pin current Pin current Pin current Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) - Gsum Pin voltage Pin voltage Pin voltage 16 1.6Vp-p 100kHz 0.8Vp-p 100kHz 0.3Vp-p 100kHz O 0.4Vp-p 100kHz 0.2Vp-p 100kHz 75mVp-p 100kHz 0.8Vp-p 100kHz 0.2Vp-p 10MHz 0.2Vp-p 30MHz 0.8Vp-p 30MHz O O 2V -2V 0V O O O O O O O O O O 0.1Vp-p 100kHz 25mVp-p 100kHz 1.9V 0V O O 1.0V -1.0V 0V 1.0V 0V -1.9V 1.9V 0V 0V -1.0V 16 16 16 16 16 16 16 16 16 16 16 16 29 29 29 29 Pin voltage 0.2 3.5 15 30 1.9V 23 15 23 4 O O O O O O O 0V O O O O O O O O O O O O O 16 -0.3V 4 0.3V 4 0.1Vp-p 30MHz 4 O O O O O O O O O 0.1Vp-p 100kHz 4 0V Hi-Z 0V 23 0V 50 30 0.6 5 -1.2 -0.6 E3 E4 0V E5 Measurement pin Measurement conditions 70 45 1.0 7.5 0 Bias conditions Min. Typ. Max. Unit mA mA mA mA V 14.0 16.0 18.0 dB -3.0 -1.5 -0.5 dB 0.9 - -0.3 -0.3 1.25 - -0.5 -0.3 0 0 0.3 0.3 V V V V 20 log (Vout/Vin) - Gac_ROM2 -11.0 -8.0 -5.0 dB 20 log (Vout/Vin) 20 log (Vout/Vin) - Gac_ROM2 20 log (Vout/Vin) - Gac_RW2 20 log (Vout/Vin) - Gac_ROM2 20 log (Vout/Vin) - Gac_RW2 20 log (Vout/Vin) 20 log (Vout/Vin) - Gac_ROM2 20 log (Vout/Vin) - Gac_ROM2 20 log (Vout/Vin) - Gac_EQoff Pin voltage - AC_OfstROM Pin voltage - AC_OfstROM Pin voltage Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) -1.0 5.0 2.0 5.0 dB 8.0 11.0 dB -11.0 -8.0 -5.0 dB 9.0 5.0 -1.0 3.5 3.5 12.0 15.0 dB 8.0 11.0 dB 2.0 6.0 6.0 5.0 8.5 8.5 dB dB dB -2.0 -1.0 -0.5 dB 0.6 0.8 1.0 -1.0 -0.8 -0.6 -150 -150 0 0 V V 150 mV 150 mV 16.5 19.5 22.5 dB 29.0 32.0 33.0 dB (AVCC = 1.9V, AVEE = -1.9V, DVCC = 1.9V, DVEE = -1.9V) Measurement No. 1 Function Measurement item Symbol Current consumption (Active, EQ On) Icc_Aeqon 2 Current consumption (Active, EQ Off) Icc_Aeqoff 3 Current consumption (DVcc) Icc_DVcc 4 Current consumption (Sleep) Icc_Slp 5 SUM offset voltage ACSUM_Ofst 6 SUM frequency gain Gsum 8 RFAC SUM 7 SUM frequency response Fsum SUM maximum output voltage H Vsum_H 9 SUM maximum output voltage L Vsum_L 10 Offset voltage ROM AC_OfstROM 11 Offset voltage RW AC_OfstRW 12 Low-frequency gain ROM_min Gac_ROM1 13 Low-frequency gain ROM_cnt Gac_ROM2 RFAC EQ RFDC -8- 14 Low-frequency gain ROM_max Gac_ROM3 15 Low-frequency gain RW_min Gac_RW1 16 Low-frequency gain RW_cnt Gac_RW2 17 Low-frequency gain RW_max Gac_RW3 18 Low-frequency gain EQ_off Gac_EQoff 19 Frequency response Min_L Fac_MinL 20 Frequency response Min_H Fac_MinH 21 Frequency response EQ_OFF Fac_ECoff 22 Maximum output voltage H Vac_H 23 Maximum output voltage L Vac_L 24 Offset voltage ROM DC_OfstROM 25 Offset voltage RW DC_OfstRW 26 Low-frequency gain ROM Gdc_ROM 27 Low-frequency gain RW Gdc_RW CXA2571N Switch conditions Bias conditions E2 0V 29 0.25V 1.3 - -150 -150 -0.25V 0V O O O O O O O O O O O O O O O O 0V O O O O O O O O O O O O O O O 0.1Vp-p 10kHz 0.1Vp-p 10kHz 25mVp-p 10kHz 25mVp-p 10kHz 0.1Vp-p 200kHz 0.1Vp-p 200kHz 25mVp-p 200kHz 25mVp-p 200kHz 0.3V -0.3V -0.3V 0.3V O O O 25mVp-p 50kHz O 25mVp-p 50kHz O 0.1Vp-p 100kHz 0.1Vp-p 100kHz 18 18 18 18 18 18 20 20 20 20 20 20 20 20 20 20 20 20 O O 25mVp-p 10kHz 18 O 25mVp-p 10kHz 18 O 0.1Vp-p 10kHz 18 0.1Vp-p 10kHz 18 20 log (Vout/Vin) 20 log (Vout/Vin) 20 log (Vout/Vin) 20 log (Vout/Vin) 18 Pin voltage 18 Pin voltage 29 Pin voltage 29 Pin voltage 20 log (Vout/Vin) - Gdc_RW 0V 0V 0V 29 E3 E4 E5 Measurement pin Min. Typ. Max. Unit 20 log (Vout/Vin) - Gdc_ROM -3.0 -1.5 -0.5 dB -9.0 -7.0 -3.0 dB 1.6 - -1.0 -0.6 0 0 V V 150 mV 150 mV 13.5 16.5 19.5 dB 13.5 16.5 19.5 dB 25.0 28.0 31.0 dB 25.0 28.0 31.0 dB 20 log (Vout/Vin) - Gfe_ROM1 -3.0 -2.0 20 log (Vout/Vin) - Gfe_ROM2 -3.0 -2.0 20 log (Vout/Vin) - Gfe_RW1 20 log (Vout/Vin) - Gfe_RW2 Pin voltage Pin voltage Pin voltage Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) 20 log (Vout/Vin) 20 log (Vout/Vin) 0 0 dB dB -4.0 -2.0 -0.5 dB -4.0 -2.0 -0.5 dB 1.2 - -150 -150 1.7 1.8 -1.5 -1.1 0 0 V V 150 mV 150 mV 17.0 20.0 23.0 dB 17.0 20.0 23.0 dB 29.0 32.0 35.0 dB 29.0 32.0 35.0 dB 20 log (Vout/Vin) - Gte_ROM1 -1.5 20 log (Vout/Vin) - Gte_ROM2 -1.5 20 log (Vout/Vin) - Gte_RW1 20 log (Vout/Vin) - Gte_RW2 Pin voltage Pin voltage 0 0 1.5 1.5 dB dB -4.5 -2.0 -0.5 dB -4.5 -2.0 -0.5 dB 1.2 - 1.7 - -1.5 -1.1 V V Measurement conditions S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1 O O O O O O O O 25mVp-p 10MHz O O O O O O O O O 0.1Vp-p 10MHz 0V Measurement No. 28 Function Measurement item Symbol Frequency response ROM Fdc_ROM 30 RFDC 29 Frequency response RW Fdc_RW Maximum output voltage H Vdc_H 31 Maximum output voltage L Vdc_L 32 Offset voltage ROM FE_OfstROM 33 Offset voltage RW FE_OfstRW 34 Low-frequency gain ROM1 Gfe_ROM1 35 Low-frequency gain ROM2 Gfe_ROM2 36 Low-frequency gain RW1 Gfe_RW1 FE 37 Low-frequency gain RW2 Gfe_RW2 38 Frequency response ROM1 Ffe_ROM1 39 Frequency response ROM2 Ffe_ROM2 40 Frequency response RW1 Ffe_RW1 41 Frequency response RW2 Ffe_RW2 TE -9- 42 Maximum output voltage H Vfe_H 43 Maximum output voltage L Vfe_L 44 Offset voltage ROM TE_OfstROM 45 Offset voltage RW TE_OfstRW 46 Low-frequency gain ROM1 Gte_ROM1 47 Low-frequency gain ROM2 Gte_ROM2 48 Low-frequency gain RW1 Gte_RW1 49 Low-frequency gain RW2 Gte_RW2 50 Frequency response ROM1 Fte_ROM1 51 Frequency response ROM2 Fte_ROM2 52 Frequency response RW1 Fte_RW1 53 Frequency response RW2 Fte_RW2 54 Maximum output voltage H Vte_H 55 Maximum output voltage L Vte_L CXA2571N Switch conditions S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 V1 amplitude V1 frequency E1 E2 0V Pin voltage Pin voltage Pin voltage - CE_OfstROM Pin voltage - CE_OfstROM Pin voltage - CE_OfstROM 0.3 -0.1 -200 0 21 21 21 21 21 21 21 21 21 1 -30mV 30mV Hi-Z 0V 1 1 1 1 O 28 17 0V 0V 0 0V 21 -200 E3 E4 E5 0V O O O O O O O O O O O O 0.5V O 0V 0.5V O O 50mVp-p 1MHz 25mV O O O O O O O O O O O 50mVp-p 1MHz 25mV O 50mVp-p 1MHz 25mV O O 0.2Vp-p 1MHz 0.1V O 0.2Vp-p 1MHz 0.1V 0.2Vp-p 1MHz 0.1V 0V Measurement pin Min. Typ. Max. Unit 200 mV 200 mV V 0.65 1.0 0 0.1 V V V 0.3 0.65 1.0 0 1.1 - Pin voltage Input where output voltage = 0V Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage 110 0.7 1.7 0.1 - -1.7 -1.1 V V V V 160 210 mV 1.0 1.4 -1.4 -1.0 -0.7 1.4 -0.2 -100 -100 1.6 0 0 0 - 0.6 V V V V 100 mV 100 mV Measurement conditions Bias conditions Measurement No. Function Measurement item Symbol 56 Offset voltage ROM CE_OfstROM 57 Offset voltage RW CE_OfstRW 58 I/O characteristics ROM1 Vce_ROM1 -1.0 -0.65 -0.3 59 I/O characteristics ROM2 Vce_ROM2 CE 60 I/O characteristics ROM3 Vce_ROM3 61 I/O characteristics RW1 Vce_RW1 Pin voltage - CE_OfstRW -1.0 -0.65 -0.3 Pin voltage - CE_OfstRW 62 I/O characteristics RW2 Vce_RW2 63 I/O characteristics RW3 Vce_RW3 Pin voltage - CE_OfstRW -0.1 Pin voltage 64 Maximum output voltage H Vce_H 65 Maximum output voltage L Vce_L 66 Output voltage 1 Vapc1 67 Output voltage 2 Vapc2 APC 68 Output voltage 3 Vapc3 69 APC OFF voltage Vapc_off DVC AVC - 10 - 70 Maximum output current Iapc_max 71 Output voltage Vavc 72 Output voltage VdVC CXA2571N CXA2571N Electrical Characteristics Measurement Circuit VCC 5.1k 30 RFDCI 29 RFDCO 10k 28 VC S12 27 RFC 5.1k 26 VFC E5 25 BST E4 24 RFG E3 VCC 1.9V 200k 23 VCC 22 CEM 21 CE 10k 10k 20 TE 19 FEI 100k 18 FE 10k 17 DVC 16 RFAC 15 200k DVCC VEE VCC DVCC 10k AC_SUM EQ_ IN GND 1 S1 S2 2 S3 3 4 10k 5 6 7 8 9 10k 10 10k S10 11 S11 12 13 20k 14 E2 0.8mA VCC VEE S4 VEE S5 -1.9V S6 S7 S8 S9 V1 E1 - 11 - CEP CET SW PD LD C D A B E F CXA2571N Application Circuits RFDC OUT 5.1k 30 RFDCI 29 RFDCO VC VCC 0.1 20k 5.1k VCC 20k 20k CE OUT 200k TE OUT FE OUT 100k DVC RFAC OUT 28 VC 27 RFC 26 VFC 25 BST 24 RFG 23 VCC 22 CEM 21 CE 20 TE 19 FEI 18 FE 17 DVC 16 RFAC 15 20k DVCC RFAC OUT 16 RFAC 15 20k DVCC DVCC DVCC AC_SUM EQ_ IN GND 1 2 3 0.1 4 5 6 A 7 B 8 C 9 D 10k 10 10k E 11 12 MODE Control 13 20k 14 LD PD IN Drive RF SUM F RFDC OUT 5.1k 30 RFDCI 29 RFDCO VC VCC 0.1 20k 5.1k VCC 20k 20k CE OUT 200k TE OUT FE OUT 100k DVC 28 VC 27 RFC 26 VFC 25 BST 24 RFG 23 VCC 22 CEM 21 CE 20 TE 19 FEI 18 FE 17 DVC 14 20k CEP AC_SUM EQ_ IN GND 1 2 3 4 5 6 A 7 B 8 C 9 D 10k 10 10k E 11 12 MODE Control 13 LD PD IN Drive 0.1 F Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 12 - CET SW PD LD C D A B E F CEP CET SW PD LD C D A B E F CXA2571N Description of Functions * RFAC The RF signal input by connecting capacitance to the EQ_IN pin is equalized, arithmetically amplified and then output from the RFAC pin. A6 B7 C8 D9 AC_SUM 4 AC SUM BST VFC 25 26 27 RFC VCC 5.1k 0.1 RF EQ_IN 3 RFG 24 RW/ROM Low-frequency gain AC_SUM: 16dB (both ROM/RW) VCA to RFAC ROM: 2dB RW: 14dB EQ Amp 16 RFAC When BST = VCC The EQ can be bypassed by connecting the BST control pin (Pin 25) to VCC. In this case only the EQ block enters sleep mode and the low power consumption mode (slim mode) is activated. The low-frequency gain is the same value as for EQ ON mode. The RF_SUM input dynamic range is VC 300mV (typ.). If RF (summing signal) is present at the pickup output pin, input the addition output signal to the EQ_IN pin (Pin 3) coupled by capacitance. When using a pickup without a summing output function, perform addition with the AC SUM block and then input the signal to the EQ_IN pin coupled by capacitance. RW/ROM switching is done by the VCA block, so either input method can be used without problem. The RW gain is 12dB higher than the ROM gain. The VCA low-frequency gain can be adjusted by the RFG pin (Pin 24) voltage. The control voltage vs. low-frequency gain characteristics are shown in the graph to the right. Gain [dB] VCA variable range 8 0 -8 Vcut [V] VC - 1 VC VC + 1 The RFAC pin (Pin 16) is an NPN transistor emitter follower output. The maximum drive current is approximately 2mA. If the load capacitance distorts the output waveform, increase the drive current. Connect resistance between Pin 16 and GND. - 13 - CXA2571N * EQ The diagram to the left shows the EQ internal block diagram. The EQ consists of a combination of HPF and LPF. The HPF and LPF transmittance is the Bessel function. The boost gain can be adjusted by adjusting the HPF gain. The boost frequency is adjusted by the RFC external resistance value and the VFC control voltage value. RFC resistance value: The cut-off frequency fo of each filter is adjusted by the Pin 27 external resistance value. The VFC voltage can be varied using this fo as the reference. VFC voltage: fo can be changed by the voltage applied to Pin 26. In HPF Amp LPF fc Boost LPF Out EQ CNT RFC 27 VFC 26 BST 25 VCC VC VC The boost gain can be adjusted by the BST pin control voltage. The control characteristics are shown in the graph below. Boost Gain [dB] 8dB The cut-off frequency control characteristics are shown in the graph below. fc [Hz] 1.5fo fo 0dB Vcut [V] VC - 1.0 VC Pin 25 voltage VC + 1.0 0.5fo Vcut [V] VC - 1.0 VC Pin 26 voltage VC + 1.0 * APC (Automatic Power Control) When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. Therefore, the current must be controlled to maintain the monitor photodiode output at a constant level. This control is performed by the APC function. VCC 56k PD 2 10k 10k 55k 10k 56k 1.25V 1 LD 1k - 14 - CXA2571N * Focus Error The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus error signal is output. This circuit has RW/ROM switching, low-frequency gain adjustment and offset addition functions. VC 100k ROM 50k 30k A6 C8 B7 D9 ROM VOFST RW 200k FE = Gain { (B + D) - (A + C) } Low-frequency gain ROM: 16dB RW: 28dB Cut-off frequency fc (typ.) ROM: 400kHz RW: 300kHz 50k 50k 200k RW ROM DVC 50k RW 200k FEI 19 18 FE * Tracking Error The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output. This circuit has RW/ROM switching and offset addition functions. 10k E 10 RW 387k RW 27k 373k VC ROM ROM 20 TE TE = Gain (F - E) Low-frequency gain ROM: 20dB RW: 32dB fc (typ.) ROM: 1MHz RW: 250kHz 27k 373k 10k F 11 * VC Buffer This outputs the VC ((1/2) VCC) voltage. The maximum output current is approximately 3mA. Use this voltage as the analog system VC voltage. * DVC Buffer This outputs the 1/2 DVCC voltage. The maximum output current is approximately 3mA. Use this voltage as the digital system DC voltage. The output DC voltage of each system is level shifted using the DVC voltage as the reference. DVCC VCC 25k 28 40k 17 40k 25k 40k 40k - 15 - CXA2571N * RFDC The signals input via the A, B, C and D pins are added, amplified and the RFDC signal is output. RW/ROM switching and low-frequency gain adjustment are possible. R (OFST) A6 B7 C8 D9 VC 15k 10k ROM RW 1.5k RFDCI 30 5.1k 29 RFDCO 40k VC RFDC = Gain (A + B + C + D) Low-frequency gain ROM: 20dB (17MHz) RW: 32dB (5.5MHz) fc (Typ.) ROM: 12MHz RW: 5MHz The gain can be adjusted by the external resistance connected between Pins 29 and 30. The output voltage offset can be adjusted by the R (OFST) resistance. * Center Error The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error signal is output. RW/ROM switching, low-frequency gain adjustment and offset adjustment are possible. The bottom hold time constant can be adjusted by the CET (Pin 13) external resistance value. 8k 16k A6 16k D9 VC 32k ROM RW VCC CEP 200k 14 40p VC 40p 40k CE 21 40k CEM 22 200k DVC 16k VC B7 16k C8 32k RW ROM VCC CET 20k 13 8k The (B + C) - (A + D) signal is arithmetically amplified. Low-frequency gain ROM: 14dB RW: 26dB - 16 - CXA2571N * Output Offset Shift The RFDC, FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC). The reference voltage of this IC is the VC voltage, and only the output reference voltage changes. The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in order to protect the DSP_IC. 40k 40k DVC AVC 40k 40k AVC VOFST The AVC and DVC voltages are arithmetically amplified and output as the VOFST voltage. The VOFST voltage serves as the level shift reference voltage, and is distributed to each system. * SW This controls the laser (APC) on/off, active/sleep mode, and RW/ROM mode switching. Switching is controlled by the voltage applied to the SW pin (Pin 12). Active/Sleep 12 R (ofst) SW RW/ROM APC_ON/OFF The VC buffer is kept active even in sleep mode. In the function block, BGR and MODE_SW are always set to active mode. Item Control voltage VCC VC or Hi-Z GND APC ON OFF ON Active/Sleep Active Sleep Active RW/ROM RW -- ROM - 17 - CXA2571N Notes on Operation [RFAC signal] Stabilizing the RFAC signal The RFAC system (RFSUM + EQ) is comprised entirely of non-inverted function blocks. This is in order to support pickups with built-in RFSUM. Therefore, if the voltage gain of each block is increased, a feedback loop is formed over the entire RFAC system causing the RFAC signal to become unstable (oscillate). In these cases, it is recommended to lower the EQ frequency response and the boost gain. This has a large effect on the board (power supply, I/O signal cross talk, etc.) loop. The RFAC signal easily becomes unstable if the VCA gain is increased, the EQ boost frequency is set to a high frequency, the EQ boost amount is increased, etc. The VCA gain is low in ROM mode, so the RFAC signal is stable. The area where the RFAC signal becomes unstable is thought to vary for each set, as this is greatly affected by the board loop as noted above. Proposed stabilization measures The board and other loop characteristics can be changed by adding external capacitance as noted below. This has a particularly large effect on the stabilization when using RFSUM. RF SUM 0.1 VCA ACSUM EQI EQ AMP Add capacitance of 10pF to 20pF [Limiter circuit] This IC has a limiter circuit to protect the input range of the rear-end IC (DSP) during excessive voltage output for each signal (RFDC, FE, TE, CE). When the limiter circuit operates, the maximum output voltage is limited to the DVCC voltage or less. However, when limiting the excessive voltage output, the ON/OFF operation of the limiter circuit causes the maximum output side (clipped portion of the output waveform) to oscillate slightly. Example) AVcc = 5V, DVcc = 3V 3.0V 0V - 18 - CXA2571N Example of Representative Characteristics EQ Rfc resistance value - Frequency response 10 Vbst = VC, Vfc = VC 9 Rfc = 20k 8 7 6 Rfc = 100k Rfc = 5.1k 10 8 6 12 14 EQ boost voltage - Frequency response Rfc = 100k Vboost = 1.0V Rfc = 100k Vboost = 0V Rfc = 5.1k Vboost = 1.0V Rfc = 5.1k Vboost = 0V Vfc = VC [dB] 5 4 3 2 1 0 0.1 1 [MHz] 10 100 [dB] 4 2 0 -2 -4 0.1 1 [MHz] 10 100 Rfc = 100k Vboost = 1.0V Rfc = 5.1k Vboost = 1.0V EQ Vfc frequency response 10 9 8 7 6 Rfc = 20k Vfc = -1V Rfc = 20k Vfc = 0V Vbst = VC Rfc = 20k Vfc = 1V 17 14 11 8 20 RF AC frequency response AC SUM EQ_Pass RW mode [dB] 5 4 3 2 1 0 0.1 1 [MHz] 10 100 [dB] 5 2 -1 -4 -7 0.1 1 [MHz] 10 100 EQ_Pass ROM mode RF DC frequency response 38 35 32 29 26 RW 34 31 28 25 22 FE frequenxy response RW [dB] 23 20 17 14 11 8 0.1 [dB] ROM 19 16 13 10 7 ROM 1 [MHz] 10 100 4 0.01 0.1 [MHz] 1 10 - 19 - CXA2571N TE frequency response 35 32 29 26 23 RW 5.5 5.0 4.5 APC I/O characteristics VLD - Output voltage [V] 4.0 VCC = 5.5V 3.5 3.0 2.5 2.0 VCC = 3.0V 1.5 1.0 [dB] 20 17 16 13 10 0.01 0.1 [MHz] 1 10 ROM 0.5 0.05 0.1 0.15 0.2 VPD - Input voltage [V] 0.25 CE I/O characteristics (DC voltage input) 3.0 BC input, RW mode 2.5 CE frequency response 2.5 2.0 1.5 AVCC = 5V, DVCC = 3V AD input, ROM mode AD input, RW mode 0 0.1 0.2 Input voltage [V] 0.3 0.4 Output voltage [dB] Output voltage [V] BC input, ROM mode 2.0 BC input 1.5 1.0 1.0 AD input AVCC = 5V, DVCC = 3V Input signal amplitude = 100mVp-p 0.5 0 0.5 0.1 1 10 Input frequency [MHz] 100 - 20 - CXA2571N Package Outline Unit: mm 30PIN SSOP (PLASTIC) + 0.2 1.25 - 0.1 9.7 0.1 0.10 30 16 5.6 0.1 A 1 + 0.1 0.22 - 0.05 0.13 M 15 0.65 + 0.05 0.15 - 0.02 0.1 0.1 0 to 10 NOTE: Dimension "" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-30P-L01 SSOP030-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). - 21 - 0.5 0.2 7.6 0.2 |
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