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INTEGRATED CIRCUITS
DATA SHEET
TDA8706A 6-bit analog-to-digital converter with multiplexer and clamp
Product specification File under Integrated Circuits, IC02 1996 Jul 30
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
FEATURES * 6-bit resolution * Binary 3-state CMOS outputs * CMOS compatible digital inputs * 3 multiplexed video inputs * R, G and B clamps on code 0 * Single 6-bit ADC operation allowed up to 40 MSPS * External control of clamping level * Internal reference voltage (external reference allowed) * Power dissipation only 36 mW (typical) * Operating temperature of -40 to +85 C * Operating between 2.7 and 5.5 V. QUICK REFERENCE DATA SYMBOL VDDA VDDD VDDO IDDA IDDD IDDO INL DNL fclk(max) Ptot PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stages supply current integral non-linearity differential non-linearity maximum clock frequency total power dissipation fclk = 40 MHz; ramp input 3 V supplies 5.5 V supplies ORDERING INFORMATION TYPE NUMBER TDA8706AM PACKAGE NAME SSOP24 DESCRIPTION plastic shrink small outline package; 24 leads; body width 5.3 mm - - 36 - fclk = 40 MHz; ramp input fclk = 40 MHz; ramp input; Tamb = 25 C fclk = 40 MHz; ramp input; Tamb = 25 C CONDITIONS MIN. 2.7 2.7 2.7 - - - - - 40 TYP. 3.0 3.0 3.0 7 4 1 0.25 0.20 - GENERAL DESCRIPTION APPLICATIONS * General purpose video applications * R, G and B signals * Automotive (car navigation) * LCD systems * Frame grabber.
TDA8706A
The TDA8706A is a 6-bit analog-to-digital converter (ADC) with 3 analog multiplexed inputs. Each input has an analog clamp on code 0 for RGB video processing. Clamping level can also be adjusted externally up to code 20. It can also be used as a single 6-bit ADC.
MAX. 5.5 5.5 5.5 10 6 1.5 0.6 0.5 - - 96
UNIT V V V mA mA mA LSB LSB MHz mW mW
VERSION SOT340-1
1996 Jul 30
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Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
BLOCK DIAGRAM
TDA8706A
VCLPR
handbook, full pagewidth 11
VCLPB 12
VCLPG 13
CLK 24
CLP
4
CLAMP
20
D5
19
D4
RED
8 MULTIPLEXER 6-BIT ADC CMOS OUTPUTS
18
D3
17
D2
digital voltage outputs
GREEN
9 16 D1
BLUE
10 15 D0
TDA8706A
VSSD 22 VDDA 21 VDDO 5 VDDA 23 VDDD 1 SR 2 SG select inputs 3 SB REGULATOR 6 VRB 7 VSSA 14 VSSO
MGD133
Fig.1 Block diagram.
1996 Jul 30
3
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
PINNING SYMBOL SR SG SB CLP VDDA VRB VSSA RED GREEN BLUE VCLPR VCLPB VCLPG VSSO D0 D1 D2 D3 D4 D5 VDDO VSSD VDDD CLK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION select input RED select input GREEN select input BLUE clamping pulse input (positive pulse) analog supply voltage reference voltage BOTTOM input analog ground RED input GREEN input BLUE input RED clamping voltage level input BLUE clamping voltage level input GREEN clamping voltage level input digital output ground digital voltage output; bit 0 (LSB) digital voltage output; bit 1 digital voltage output; bit 2 digital voltage output; bit 3 digital voltage output; bit 4 digital voltage output; bit 5 supply voltage for output stage digital ground digital supply voltage clock input
handbook, halfpage
TDA8706A
SR SG SB CLP VDDA VRB VSSA RED GREEN
1 2 3 4 5 6
24 CLK 23 VDDD 22 VSSD 21 VDDO 20 D5 19 D4
TDA8706A
7 8 9 18 D3 17 D2 16 D1 15 D0 14 VSSO 13 VCLPG
MGD132
BLUE 10 VCLPR 11 VCLPB 12
Fig.2 Pin configuration.
1996 Jul 30
4
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD VDD analog supply voltage digital supply voltage supply voltage difference VDDA - VDDD VDDA - VDDO VDDD - VDDO VI IO Tstg Tamb Tj HANDLING input voltage output current storage temperature operating ambient temperature junction temperature -1.0 -1.0 -1.0 -0.3 - -55 -40 - PARAMETER MIN. -0.3 -0.3
TDA8706A
MAX. +7.0 +7.0 +1.0 +1.0 +1.0 +7.0 10 +150 +85 +150 V V V V V V
UNIT
mA C C C
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 119 UNIT K/W
1996 Jul 30
5
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
TDA8706A
CHARACTERISTICS VDDA = V5 to V7 = 2.7 to 5.5 V; VDDD = V23 to V22 = 2.7 to 5.5 V; VDDO = V21 to V14 = 2.7 to 5.5 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = -40 to +85 C; typical values measured at VDDA = VDDD = VDDO = 3 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDDA VDDD VDDO VDD analog supply voltage digital supply voltage output stages supply voltage supply voltage difference VDDA - VDDD VDDA - VDDO VDDD - VDDO IDDA IDDD IDDO Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 VIL VIH IIL IIH Zi CI VIL VIH IIL IIH VCLP ICLP LOW level input voltage VDDD < 3.3 V HIGH level input voltage VDDD < 3.3 V LOW level input current HIGH level input current input impedance input capacitance Vclk = VDDD x 0.2 Vclk = VDDD x 0.8 fclk = 40 MHz fclk = 40 MHz 0 0 - - VDDD x 0.3 V VDDD x 0.2 V VDDD VDDD +1 10 - - V V A A k pF analog supply current digital supply current output stages supply current fclk = 40 MHz; ramp input -0.3 -0.3 -0.3 - - - - - - 7 4 1 +0.3 +0.3 +0.3 10 6 1.5 V V V mA mA mA 2.7 2.7 2.7 3.0 3.0 3.0 5.5 5.5 5.5 V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDDD x 0.7 - VDDD x 0.8 - -1 - - - 0 VDDD < 3.3 V 0 0 2 4 3 - -
INPUTS SR, SG, SB, CLP (REFERENCED TO VSSD) LOW level input voltage HIGH level input voltage VDDD < 3.3 V LOW level input current HIGH level input current VIL = VDDD x 0.2 VIH = VDDD x 0.8 VDDD x 0.3 V VDDD x 0.2 V VDDD VDDD - +1 V V A A V A
VDDD x 0.7 - VDDD x 0.8 - -1 - Vcode -9 - - - - -
INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2 input voltage for clamping input current Vcode 20 30
1996 Jul 30
6
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8706A
MAX.
UNIT
ANALOG INPUTS RED, GREEN AND BLUE; see Table 1 Vi(p-p) input voltage amplitude (peak-to-peak value) VDDA = VDDD = 3 V; Tamb = 25 C VDDA = VDDD = 5 V; Tamb = 25 C Ii Cclamp VRB TVRB Outputs DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD) VOL VOH LOW level output voltage HIGH level output voltage IO = 1 mA IO = -1 mA 0 - 0.5 VDDO V V VDDO - 0.5 - input current clamp coupling capacitance 0.665 0.625 - 1 - - - 0.70 0.66 - 10 0.735 0.695 10 100 V V A nF
Reference voltages for the resistor ladder; see Table 1 reference voltage BOTTOM VDDA = 3 V VDDA = 5 V temperature variation on VRB Tamb = 0 to 50 C VDDA - 1.19 - VDDA - 1.13 - 0.7 - V V mV/C
Switching characteristics CLOCK INPUT CLK; see Fig.3; note 1 fclk(max) fmux(max) tCPH tCPL tr tf maximum clock frequency maximum multiplexer frequency clock pulse width HIGH clock pulse width LOW clock rise time clock fall time 40 20 8 8 10% to 90%; fclk 25 MHz; - LOW = VSSD, HIGH = VDDD 90% to 10%; fclk 25 MHz; - LOW = VSSD, HIGH = VDDD - - - - - - - - - - 10 10 MHz MHz ns ns ns ns
Analog signal processing LINEARITY INL DNL integral non-linearity differential non-linearity fclk = 40 MHz; ramp input; Tamb = 25 C fclk = 40 MHz; ramp input; Tamb = 25 C - - 0.25 0.20 0.6 0.5 LSB LSB
EFFECTIVE BITS; note 2 EB effective bits fclk = 40 MHz; fi = 4.43 MHz - 5.8 - bits
1996 Jul 30
7
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8706A
MAX.
UNIT
Timing (fclk = 40 MHz; CL = 20 pF); Tamb = 25 C; see Fig.3 OUTPUT DATA; note 3 tds th td sampling delay time output hold time output delay time VDDO = 4.75 V VDDO = 3.15 V VDDO = 2.70 V SELECT INPUT SIGNALS SR, SG, SB AND CLP tsu tr tf tover set-up time SR, SG and SB rise time SR, SG and SB fall time SR, SG and SB R, G and B (active) overlap time with respect to select signals SR, SG and SB clamp pulse time multiplexer hold time SR, SG and SB with no overlap; see Fig.3 with overlap 10% to 90% 90% to 10% see Fig.4 4 4 0 6 6 - 10 - see Fig.4 - - - - ns ns ns ns ns - 5 - - - - - 12 17 18 7 - 15 20 21 ns ns ns ns ns
tCLPP tMH Notes
CCLP = 10 nF
- 9
3 -
- -
s ns
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 3. Output data acquisition: the output data is available after the maximum delay time of td.
1996 Jul 30
8
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
Table 1 Output coding and input voltage (typical values) Vi(p-p) (V) VDDA = VDDD = 3 V VDDA = VDDD = 5 V Underflow 0 1 . . 62 63 Overflow Table 2 VDDA - 0.4 VDDA - 0.4 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1
TDA8706A
BINARY OUTPUT BITS D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1
STEP
Clamping input level (VCLPR, VCLPG and VCLPB) VCLPR, VCLPG AND VCLPB CLAMPING LEVEL code 0 code -9 to code 20
Open-circuit(1) Vcode -9 to Vcode 20 Note 1. Use capacitor 10 pF to VSSA. Table 3
Clamp and inputs RED, GREEN and BLUE; VDDA = VDDD = VDDO = 3 V CLAMP VCLPR, VCLPG or VCLPB open 1 1 VCLP open VCLP Vi RED or GREEN or BLUE VDDA - 1.1 V VCLP VDDA - 1.1 V VCLP DIGITAL OUTPUTS X(1) 0 code (VCLP)
SR or SG or SB 0
Note 1. Where X = don't care. Table 4 Clamping characteristic related to TV signals PARAMETER Clamping time per line (signal active) Input signals clamped to correct level 2.2 - MIN. 3.0 3 TYP. - 10 MAX. s lines UNIT
1996 Jul 30
9
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
TDA8706A
handbook, full pagewidth
tCPH
tCPL
CLK tSU tMH SR
SG
SB
CLAMP tCLPP OUTPUT DATA
GREEN
BLUE
RED
GREEN
MBE859
td
th
Fig.3 AC characteristics select signals, clamp and output data.
1996 Jul 30
10
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
TDA8706A
handbook, full pagewidth
CLK
SR
SG
SB tover
RED ACTIVE tover
GREEN ACTIVE tsu tover
BLUE ACTIVE
MBE860
Fig.4 Anti-overlap system for analog multiplexer.
handbook, full pagewidth
RED, GREEN, BLUE (SR, SG, SB inputs) digital outputs = 000000
CLAMP input
1 0
MBE861
Fig.5 AC characteristics select signals; clamp and data.
1996 Jul 30
11
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
INTERNAL PIN CONFIGURATIONS
TDA8706A
handbook, halfpage
handbook, halfpage
VDDA
VDDO
RLAD REGULATOR
D5 to D0
VRB
VSSO
MGD134
VSSA
MBE967
Fig.6 CMOS data outputs.
Fig.7 VRB.
DDD handbook, halfpage
V
CLK
1/2V
DDD
VSSD
MLC860
Fig.8 CLK input.
1996 Jul 30
12
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
APPLICATION INFORMATION
TDA8706A
handbook, full pagewidth
SR SG SB CLP VDDA VRB(1) 100 nF VSSA VSSA RED GREEN BLUE VCLPR 100 nF VSSA 100 nF VSSA VCLPB
(2)
1 2 3 4 5 6
24 23 22 21 20 19
CLK VDDD VSSD VDDO D5 D4 D3 D2 D1 D0 VSSO VCLPG(2) 100 nF VSSA
TDA8706A
7 8 9 10 11 12 18 17 16 15 14 13
MBE969
(2)
The analog and digital supplies should be separated and decoupled. VRB must not be connected to VCLPR, VCLPB or VCLPG pins. For applications where the black level is clamped to code 0, VCLPR, VCLPB and VCLPG must be left open-circuit with their respective decoupling capacitors. In that event, they may also be connected together in order to use only one single decoupling capacitor. (1) VRB is decoupled to VSSA. Eventually an external regulator can be connected to VRB. (2) VCLPR, VCLPB and VCLPG are decoupled to VSSA. Eventually external voltages can be forced on VCLPR, VCLPB and VCLPG.
Fig.9 Application diagram.
1996 Jul 30
13
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
PACKAGE OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
TDA8706A
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150AG EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-09-08 95-02-04
1996 Jul 30
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Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering SO Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. SSOP
TDA8706A
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 30
15
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8706A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jul 30
16
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
NOTES
TDA8706A
1996 Jul 30
17
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
NOTES
TDA8706A
1996 Jul 30
18
Philips Semiconductors
Product specification
6-bit analog-to-digital converter with multiplexer and clamp
NOTES
TDA8706A
1996 Jul 30
19
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com (1) TDA8706A_1 July 18, 1996 12:44 pm SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
537021/30/01/pp20 Date of release: 1996 Jul 30 Document order number: 9397 750 00991

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