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INTEGRATED CIRCUITS
DATA SHEET
TDA8043 Satellite Demodulator and Decoder (SDD)
Product specification Supersedes data of 1997 Nov 07 File under Integrated Circuits, IC02 1998 Feb 13
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
FEATURES * One-chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer * 3.3 V supply voltage (up to 5 V allowed) * Internal clock divider * On-chip crystal oscillator * QPSK/BPSK demodulator: - Interpolator to handle variable symbol rates without an external anti-aliasing filter - On-chip Automatic Gain Control (AGC) of the analog input I and Q baseband signals or tuner AGC control - Two on-chip matched Analog-to-Digital Converters (ADCs; 7 bits) - Square-Root Raised-Cosine Nyquist filter with programmable roll-off factor - High maximum symbol frequency: 32 Msymbols/s - Can be used at low channel Es/No (Symbol energy-to-noise ratio) - Internal carrier recovery, clock recovery and AGC loops with programmable loop filters - Two carrier recovery loops enabling phase tracking of the incoming symbols - Different modulation schemes: Quadrature Phase Shift Keying (QPSK) and Binary-Phase Shift Keying (BPSK) - Signal-to-noise ratio (S/N) estimation - External indication of demodulator lock. * Viterbi decoder: - Rate 12 convolutional code based - Constraint length K = 7 with G1 = 171oct and G2 = 133oct - Supported puncturing code rates: 12, 23, 34, 45, 56, 6 , 7 and 8 7 8 9 - 4 bits `soft decision' inputs for both I and Q - Truncation length: 144 - Automatic synchronization to correct puncturing rate and spectral inversion - Channel Bit Error Rate (BER) estimation from 10-2 to 10-8 - External indication of Viterbi synchronization lock - Differential decoding supported. * Reed-Solomon (RS) decoder:
TDA8043
- (204, 188 and T = 8) Reed Solomon code - Automatic (I2C-bus configurable) synchronization of bytes, transport packets and frames - Internal convolutional de-interleaving (I = 12; using internal memory) - De-randomizer based on Pseudo Random Binary Sequence (PRBS) - External indication of RS decoder sync lock - External indication of uncorrectable errors (transport error indicator is set) - Indication of the number of lost blocks - Indication of the number of corrected blocks/bytes. * I2C-bus interface: - I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder with standby mode; when no I2C-bus is used, default mode is defined - 4-bit I/O expander for flexible access to and from the I2C-bus - I2C-bus configurable interrupt pin - Standby mode for reduced power consumption. * Package: QFP100 * Boundary scan test. APPLICATIONS * Demodulation and FEC for digital satellite TV.
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
GENERAL DESCRIPTION This document specifies a DVB compliant demodulator and forward error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. The TDA8043 can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are: * Single Carrier Per Channel (SCPC): two or more QPSK or BPSK modulated signals in a single satellite channel (transponder) * Multi-Carrier Per Channel (MCPC): one QPSK or BPSK modulated signal in a single satellite channel (transponder) * Simul-cast: QPSK or BPSK modulated signal together with a Frequency Modulated (FM) signal in a single satellite channel. The SDD requires the analog in-phase (I) and quadrature (Q) components as an input and provides 8-bit wide MPEG2 transport packet data at the output. The outputs of the SDD can be directly connected to a descrambler (SAA7206) or a demultiplexer (SAA7205).
TDA8043
For evaluation purposes, the output can also be used to monitor internal data, for example I/Q after demodulation. The SDD requires a single clock frequency which is independent of the received symbol rate, providing the clock frequency is slightly higher than twice the highest symbol frequency. All loops to recover the data from the received symbols are internal. No external loop components are required. Loop parameters for the clock, carrier recovery and AGC can be controlled via the I2C-bus. The Forward Error Correction (FEC) unit has a built-in state machine to achieve lock without knowing the system parameters (depuncturing rate, spectral inversion, etc.). Once lock is achieved, all necessary parameters can be read via the I2C-bus. By programming these parameters in advance lock can be achieved more quickly. The SDD can be controlled and monitored via the I2C-bus. An I2C-bus default mode is specified which makes it possible to use the device by software control. A 4-bit bidirectional I/O expander and an interrupt line are available. By sending an interrupt signal, the SDD can inform the microcontroller of its internal status (lock).
ORDERING INFORMATION TYPE NUMBER TDA8043H PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT317-2
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
QUICK REFERENCE DATA SYMBOL VDDA VDDD IDD(tot) fclk rs IL S/N Ptot Tstg Tamb Tj Notes PARAMETER analog supply voltage digital supply voltage total supply current clock frequency symbol rate nyquist roll-off (selectable) implementation loss signal-to-noise ratio for locking the SDD total power dissipation IC storage temperature operating ambient temperature operating junction temperature Tamb = 70 C note 3 QPSK mode; note 1 Tamb = 70C; note 1 note 2 CONDITIONS MIN. 3.0 3.0 VDDD = 3.3 V; note 1 - - 0.5 - - 2 - -55 0 - TYP. 3.3 3.3 390 - - 35 or 50 0.3 - 1285 - - -
TDA8043
MAX. 3.6 3.6 - 65 32 - - - 1650 +150 70 125 V V mA
UNIT
MHz Msymbols/s % dB dB mW C C C
1. These values are specified for a symbol rate of 27.5 Msymbols/s, a puncturing rate of 34 and a clock frequency of 65 MHz. 2. A range from 3 to 32 Msymbols/s can be achieved with one SAW filter. By using an internal clock divider and reducing the external SAW filter bandwidth, symbol rates down to 0.5 Msymbols/s can be achieved by using a 65 MHz crystal clock. 3. This data was measured in a laboratory environment at a symbol rate of 27.5 Msymbols/s, a clock frequency of 65 MHz, a signal-to-noise ratio of 4.5 dB and including a tuner. PINNING SYMBOL I2 I3 VSSD1 n.c. n.c. I4 I5 I6 Q0 VDDD1 Q1 Q2 Q3 Q4 VSSD2 Q5 Q6 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 I/O I I - - - I I I I - I I I I - I I DESCRIPTION digital I-input bit 2 (ADC bypass); note 1 digital I-input bit 3 (ADC bypass); note 1 digital ground 1 not connected not connected digital I-input bit 4 (ADC bypass); note 1 digital I-input bit 5 (ADC bypass); note 1 digital I-input bit 6 (ADC bypass: MSB); note 1 digital Q-input bit 0 (ADC bypass: LSB); note 1 digital supply voltage 1 digital Q-input bit 1 (ADC bypass); note 1 digital Q-input bit 2 (ADC bypass); note 1 digital Q-input bit 3 (ADC bypass); note 1 digital Q-input bit 4 (ADC bypass); note 1 digital ground 2 digital Q-input bit 5 (ADC bypass); note 1 digital Q-input bit 6 (ADC bypass: MSB); note 1
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
SYMBOL VSSD3 VDDD2 PRESET P3 P2 P1 P0 VDDD3 n.c. n.c. PDOCLK PDO0 PDO1 PDO2 VSSD4 PDO3 PDO4 PDO5 n.c. n.c. PDO6 n.c. VDDD4 VDDD5 VSSD5 VDDD6 VDDD7 PDO7 n.c. n.c. PDOERR PDOVAL PDOSYNC VSSD6 SCL SDA INT A0 RSLOCK VLOCK DLOCK VDDD8 VDDD9 TEST PIN 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 I/O - - I I/O I/O I/O I/O - - - O O O O - O O O - - O - - - - - - O - - O O O - I I/O O I O O O - - I DESCRIPTION digital ground 3 digital supply voltage 2 set device into default mode quasi-bidirectional I/O port (bit 3) quasi-bidirectional I/O port (bit 2) quasi-bidirectional I/O port (bit 1) quasi-bidirectional I/O port (bit 0) digital supply voltage 3 not connected not connected output clock for transport stream bytes parallel data output (bit 0) parallel data output (bit 1) parallel data output (bit 2) digital ground 4 parallel data output (bit 3) parallel data output (bit 4) parallel data output (bit 5) not connected not connected parallel data output (bit 6) not connected digital supply voltage 4 digital supply voltage 5 digital ground 5 digital supply voltage 6 digital supply voltage 7 parallel data output (bit 7) not connected not connected transport error indicator data valid indicator transport packet synchronization signal digital ground 6 serial clock of I2C-bus; note 1 serial data of I2C-bus; note 1 interrupt output (active LOW); note 1 I2C hardware address; note 1 Reed-Solomon lock indicator Viterbi lock indicator demodulator lock indicator digital supply voltage 8 digital supply voltage 9 test pin (normally connected to ground); note 1
TDA8043
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
SYMBOL TRST TCK n.c. n.c. VDDD10 VSSD7 VSSD8 TMS TDO TDI VDDD11 VSSD9 VSSD(AD) VDDD(AD) Vref(B) VSSA1 QA Vref(Q) IA VSSA2 Vref(I) VDDA VDDXTAL XTALI XTALO VSSXTAL VDDD12 VDDD13 VSSD10 n.c. n.c. n.c. VAGC n.c. VDDD14 VDDD15 OUTSD I0 I1 Note 1. This pin is 5 V tolerant. PIN 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I I - - - - - I O I - - - - O - I O I - O - - I O - - - - - - - O - - - O I I DESCRIPTION
TDA8043
BST optional asynchronous reset (normally connected to ground); note 1 BST dedicated test clock (normally connected to ground); note 1 not connected not connected digital supply voltage 10 digital ground 7 digital ground 8 BST input control signal (normally connected to ground); note 1 BST serial test data out BST serial test data in (normally connected to ground); note 1 digital supply voltage 11 digital ground 9 digital ground for ADC digital supply for ADC bottom reference voltage for ADC analog ground 1 analog input Q AGC decoupling for Q path analog input I analog ground 2 AGC decoupling for I path analog supply voltage supply voltage for crystal oscillator crystal oscillator input crystal oscillator output ground for crystal oscillator digital supply voltage 12 digital supply voltage 13 digital ground 10 not connected not connected not connected AGC output voltage; note 1 not connected digital supply voltage 14 digital supply voltage 15 general purpose sigma-delta output digital I-input bit 0 (ADC bypass: LSB); note 1 digital I-input bit 1 (ADC bypass); note 1
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
TDA8043
97 VDDD15 96 VDDD14
90 VSSD10 89 VDDD13
handbook, full pagewidth
84 VDDXTAL 83 VDDA
88 VDDD12 87 VSSXTAL
98 OUTSD
86 XTALO
100 I1
I2 I3 VSSD1 n.c. n.c. I4 I5 I6 Q0
1 2 3 4 5 6 7 8 9
82 Vref(I) 81 VSSA2 80 IA 79 Vref(Q) 78 QA 77 VSSA1 76 Vref(B) 75 VDDD(AD) 74 VSSD(AD) 73 VSSD9 72 VDDD11 71 TDI 70 TDO 69 TMS 68 VSSD8 67 VSSD7 66 VDDD10 65 n.c. 64 n.c. 63 TCK 62 TRST 61 TEST 60 VDDD9 59 VDDD8 58 DLOCK 57 VLOCK 56 RSLOCK 55 A0 54 INT 53 SDA 52 SCL 51 VSSD6 PDOVAL 49 PDOSYNC 50
94 VAGC 93 n.c.
VDDD1 10 Q1 11 Q2 12 Q3 13 Q4 14 VSSD2 15 Q5 16 Q6 17 VSSD3 18 VDDD2 19 PRESET 20 P3 21 P2 22 P1 23 P0 24 VDDD3 25 n.c. 26 n.c. 27 PDOCLK 28 PDO0 29 PDO1 30 PDO2 31 VSSD4 32 PDO3 33 PDO4 34 PDO5 35 n.c. 36 n.c. 37 PDO6 38 n.c. 39 VDDD4 40 VDDD5 41 VSSD5 42 VDDD6 43 VDDD7 44 PDO7 45 n.c. 46 n.c. 47 PDOERR 48
TDA8043H
85 XTALI
95 n.c.
92 n.c.
91 n.c.
99 I0
MGM102
Fig.1 Pin configuration.
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
APPLICATION INFORMATION
TDA8043
handbook, full pagewidth
MICROCONTROLLER
4-Mbit EPROM
4-Mbit DRAM
16-Mbit SDRAM
data address
16
16
8+3
I TUNER Q TDA8043 (SDD) 8 Ctrl SAA7205 AND SAA7206
8
I2S-bus SAA7201 H, V valid YUV
Ctrl
AUDIO DAC
L R
27 MHz CVBS I2C-bus high speed data H, V TTX/TTXRQ
CVBS SAA7183
MGM104
Y/C RGB
Fig.2 Satellite set-top box concept.
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
TDA8043
handbook, full pagewidth
TSA5522
x
TDA8010
Vtune SYNTHESIZER switch output
ADC
SAW
x
TDA8042
x
AGC DETECTOR
AGC control
TUNER
SWITCH XTAL OSCILLATOR ADC ADC I2C-bus
AGC
QPSK/BPSK DEMODULATOR
FORWARD ERROR CORRECTION
TDA8043 (SDD)
MGM105
data
control
Note: Control for external AGC is also available using the internal AGC sigma-delta converter (indicated with the dashed line).
Fig.3 Application of satellite demodulator and decoder including tuner.
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
TDA8043
handbook, full pagewidth +3.3 V
L(1)
VDDD1 15 F
tuner AGC (optional) 10 k 470
10 15 pF 10 nF L 4.7 pF XTAL(2) VDDA 390 k(5) 100 nF 10 nF
+3.3 V
L(1)
VDDD2 15 F 330 nF VDDD2
+5V
(4)
VDDD2 C(3) n.c. n.c. n.c. n.c.
C(3)
C(3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 n.c. n.c. 4 5 6 7 8 9 VDDD C(3) VDDD1 100 nF 10 11 12 13 14 15 470 k 16 17 18 VDDD1 C(3) P3 P2 P1 P0 VDDD1 C(3) n.c. n.c. packet data and control outputs 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n.c. n.c. C(3) C(3) n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67
100 nF I 100 nF Q 100 nF
390 k(5) 100 nF
VDDD2 C(3)
VDDD2 TDI TDO TMS C(3)
TDA8043H
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2.2 k 2.2 k C(3) n.c. n.c. TCK TRST C(3)
VDDD2
VDDD1
+5 V 1.6 k interrupt I2C-bus
n.c.
+3.3 V
L(1)
VDDA 15 F
VDDD1
VDDD1
MGM103
packet data and control outputs
(1) (2) (3) (4)
B = SMD bead type CBD8.9/3/3 Grade 4S2. XTAL = 65 MHz, 3rd overtone. C = 6.8 nF, SMD. L = 560 nH, Taiyo Yuden LAL02.
(5) Value specified for a 65 MHz clock. For other clock frequencies, refer to "Application note AN96108".
If possible, connect `n.c.' pins to ground to ease power dissipation. TRST, TCK, TMS, and TDI pins can be connected to ground if they are not used.
Fig.4 Application diagram.
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA8043
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vMA 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
TDA8043
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8043
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 13
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Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
NOTES
TDA8043
1998 Feb 13
14
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
NOTES
TDA8043
1998 Feb 13
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/1200/03/pp16
Date of release: 1998 Feb 13
Document order number:
9397 750 03267

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