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INTEGRATED CIRCUITS
DATA SHEET
SAA7182; SAA7183 Digital Video Encoder (EURO-DENC)
Preliminary specification Supersedes data of 1995 Sep 19 File under Integrated Circuits, IC22 1996 Jul 08
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
FEATURES * CMOS 5 V device * Digital PAL/NTSC/SECAM encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. or Y and Cb, Cr on 16 lines ("CCIR 656") * Three DACs for CVBS, Y and C operating at 27 MHz with 10-bit resolution * Three DACs for RGB operating at 27 MHz with 9-bit resolution, RGB sync on CVBS and Y * CVBS, Y, C and RGB output simultaneously * Closed captioning and teletext encoding including sequencer and filter * On-chip YUV to RGB matrix * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * Overlay with Look-Up Tables (LUTs) 8 x 3 bytes * Macrovision Pay-per-View protection system as option, also used for RGB output This applies to SAA7183 only. The device is protected by USA patent numbers 461603, 4577216 and 4819098 and other intellectual property rights. QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILE DLE Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C, CVBS and RGB without load (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature - 80 - - 0 PARAMETER
SAA7182; SAA7183
Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information * Controlled rise/fall times of output syncs and blanking * Down-mode of DACs * PLCC84 package. GENERAL DESCRIPTION The SAA7182; SAA7183 encodes digital YUV video data to an NTSC, PAL, SECAM CVBS or S-Video signal and also RGB. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). The circuit is compatible to the DIG-TV2 chip family.
MIN. 4.75 4.75 - -
TYP. 5.0 5.0 90 220 2 - - - -
MAX. 5.25 5.25 110 250 - - 2 1 +70 V V
UNIT
mA mA V LSB LSB C
TTL compatible
1996 Jul 08
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7182WP SAA7183WP BLOCK DIAGRAM PLCC84 PLCC84 DESCRIPTION plastic leaded chip carrier; 84 leads plastic leaded chip carrier; 84 leads
SAA7182; SAA7183
VERSION SOT189-2 SOT189-2
handbook, full pagewidth
RTCI RESET SDA SCL SA
RCV1
TTXRQ XTALO CREF
LLC
RCV2 CDIR
XTALI
Y/C/CVBS VDDA4 to VrefH2 VDDA7 75 68 64, 70, 72, 74
1
84
83
4 I2C-bus control 8
37
50 35 36 20 47 45 44 48
I2C-BUS INTERFACE 8 I2C-bus control
SECAM PROCESSOR
SYNC CLOCK I2C-bus control 73 OUTPUT INTERFACE D A 71 69 CHROMA 67 76 52 8 I2C-bus control 61 Y CbCr RGB PROCESSOR D A 58 55 CVBS Y
DP0 to DP7 MP7 to MP0 OVL2 to OVL0 KEY
10 to 13 16 to 19 8 25 to 28 31 to 34 8 6 to 8 3 9
DbDr Y Y ENCODER CbCr C
clock and timing
8
DATA MANAGER
8 I2C-bus control
I2C-bus control
internal control bus
8
I2C-bus control
VSSA VrefL2 VrefL1
TTX
21 3
SAA7182 SAA7183
RED GREEN BLUE
3, 15, 24, 30, 39, 42, 51, 79, 81 VSSD1 to VSSD9
5, 14, 22, 29, 38, 41, 49, 80, 82 VDDD1 to VDDD9
2, 23, 40, 43, 46, 56, 59, 62, 65, 66 n.c.
78 SP
77 AP
53 VrefH1
63
54, 57, 60 VDDA1 to VDDA3
MGB696
IRGB
Fig.1 Block diagram.
1996 Jul 08
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
PINNING SYMBOL RESET n.c. VSSD1 SA VDDD1 OVL2 OVL1 OVL0 KEY DP0 DP1 DP2 DP3 VDDD2 VSSD2 DP4 DP5 DP6 DP7 TTXRQ TTX VDDD3 n.c. VSSD3 MP7 MP6 MP5 MP4 VDDD4 VSSD4 MP3 MP2 MP1 MP0 RCV1 RCV2 RTCI PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 digital supply voltage 4 digital ground 4 digital supply voltage 2 digital ground 2 Key input for OVL. When HIGH it selects OVL input. DESCRIPTION
SAA7182; SAA7183
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. not connected digital ground 1 The I2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH. digital supply voltage 1 3-bit overlay data input. This is the index for the internal look-up table.
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.
Teletext request output, indicating when the bitstream is valid. Teletext bitstream input. digital supply voltage 3 not connected digital ground 3 Upper 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data, or input for Y data only, if 16 line input mode is used.
Lower 4 bits of MPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data, or input for Y data only, if 16 line input mode is used.
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal. Raster Control 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse. Real Time Control Input. If the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality.
1996 Jul 08
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
SYMBOL VDDD5 VSSD5 n.c. VDDD6 VSSD6 n.c. XTALI XTALO n.c. CREF LLC VDDD7 CDIR
PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 digital supply voltage 5 digital ground 5 not connected digital supply voltage 6 digital ground 6 not connected
DESCRIPTION
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. Crystal oscillator output (to crystal). not connected Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals. Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set by the CDIR pin. digital supply voltage 7 Clock direction. If the CDIR input is HIGH, the circuit receives a clock and optional CREF signal, otherwise if CDIR is LOW CREF and LLC are generated by the internal crystal oscillator. digital ground 7 Lower reference voltage 1 input for the RGB DACs, connect to VSSA. Upper reference voltage 1 input for the RGB DACs, connect via 100 nF capacitor to VSSA. Analog supply voltage 1 for the RGB DACs. Analog output of the BLUE component. not connected Analog supply voltage 2 for the RGB DACs. Analog output of the GREEN component. not connected Analog supply voltage 3 for the RGB DACs. Analog output of the RED component. not connected Current input for RGB amplifiers, connected via 15 k resistor to VDDA. Analog supply voltage 4 for the Y/C/CVBS DACs. not connected not connected Analog ground for the DACs. Current input for the Y/C/CVBS amplifiers, connected via 15 k resistor to VDDA. Analog output of the chrominance signal. Analog supply voltage 5 for the Y/C/CVBS DACs. Analog output of the luminance signal. Analog supply voltage 6 for the Y/C/CVBS DACs. Analog output of the CVBS signal.
VSSD7 VrefL1 VrefH1 VDDA1 BLUE n.c. VDDA2 GREEN n.c. VDDA3 RED n.c. IRGB VDDA4 n.c. n.c. VSSA IY/C/CVBS CHROMA VDDA5 Y VDDA6 CVBS
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
1996 Jul 08
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
SYMBOL VDDA7 VrefH2 VrefL2 AP SP VSSD8 VDDD8 VSSD9 VDDD9 SCL SDA
PIN 74 75 76 77 78 79 80 81 82 83 84
DESCRIPTION Analog supply voltage 6 for the Y/C/CVBS DACs. Upper reference voltage 2 input for the Y/C/CVBS DACs, connected via 100 nF capacitor to VSSA. Lower reference voltage 2 input for the Y/C/CVBS DACs, connect to VSSA. Test pin. Connected to digital ground for normal operation. Test pin. Connected to digital ground for normal operation. digital ground 8 digital supply voltage 8 digital ground 9 digital supply voltage 9 I2C-bus serial clock input. I2C-bus serial data input/output.
1996 Jul 08
6
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
5 VDDD1
82 VDDD9
80 VDDD8
1 RESET
3 VSSD1
81 VSSD9
79 VSSD8
DP2 12 DP3 13 VDDD2 14 VSSD2 15 DP4 16 DP5 17 DP6 18 DP7 19 TTXRQ 20 TTX 21 VDDD3 22 n.c. 23 VSSD3 24 MP7 25 MP6 26 MP5 27 MP4 28 VDDD4 29 VSSD4 30 MP3 31 MP2 32 MP1 33 MP0 34 RCV1 35 RCV2 36 RTCI 37 VDDD5 38 VSSD5 39 n.c. 40 VDDD6 41 VSSD6 42 n.c. 43 XTALI 44 XTALO 45 n.c. 46 CREF 47 LLC 48 VDDD7 49 CDIR 50 VSSD7 51 VrefL1 52 VrefH1 53
76 VrefL2
8 OVL0
7 OVL1
6 OVL2
handbook, full pagewidth
75 VrefH2 74 VDDA7 73 CVBS 72 VDDA6 71 Y 70 VDDA5 69 CHROMA 68 IY/C/CVBS 67 VSSA 66 n.c. 65 n.c. 64 VDDA4 63 IRGB 62 n.c. 61 RED 60 VDDA3 59 n.c. 58 GREEN 57 VDDA2 56 n.c. 55 BLUE 54 VDDA1
84 SDA
11 DP1
10 DP0
9 KEY
83 SCL
2 n.c.
4 SA
78 SP
SAA7182 SAA7183
77 AP
MGB697
Fig.2 Pin configuration.
1996 Jul 08
7
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
FUNCTIONAL DESCRIPTION The digital video encoder (EURO-DENC) encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-Video signals. NTSC-M, PAL B/G and SECAM standards and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. In addition to RED, GREEN and BLUE converted components, the dematrixed YUV input is available on three separate analog outputs. The basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of RS-170-A and "CCIR 624". For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. For total filter transfer characteristics see Figs 3, 4, 5, 6, 7 and 8. The DACs for Y, C and CVBS are realized with full 10-bit resolution, DACs for RGB are with 9-bit resolution. The MPEG port (MP) accept 8 lines multiplexed Cb-Y-Cr data. The 8-bit multiplexed Cb-Y-Cr formats are "CCIR 656" (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb, Cr on DP port can be chosen as input. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to EURO-DENC. Via RTCI pin connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID (see "data sheet SAA7111" ) definite subcarrier phase can be inserted. The EURO-DENC synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. The encoder is always timing master for the MPEG port (MP), but it can additionally be configured as slave with respect to the RCV trigger inputs.
SAA7182; SAA7183
European teletext encoding is supported if an appropriate teletext bitstream is applied to the TTX pin. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision; it also supports overlay via KEY and three control bits by a 24 x 8 LUT. A number of possibilities are provided for setting of different video parameters such as: Black and blanking level control Colour subcarrier frequency Variable burst amplitude etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. Depending on the polarity of pin KEY, the MP input (or MP/DP input) or OVL input are selected to be encoded to CVBS and Y/C signals, and output as RGB. KEY controls OVL entries of a programmable LUT for encoded signals and for RGB output. The common KEY switching signal can be disabled by software for the signals to be encoded (Y, C and CVBS), such that OVL will appear on RGB outputs, but not on Y, C and CVBS. OVL input under control of KEY can be also used to insert decoded teletext information or other on-screen data. Optionally, the OVL colour LUTs located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving, for example, a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control.
1996 Jul 08
8
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with Macrovision anti-taping, additional insertion of AGC super-white pulses, programmable in height, is supported. In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 5 and 6. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. TELETEXT INSERTION AND ENCODING Pin TTX receives a teletext bitstream sampled at the LLC clock, each teletext bit is carried by four or three LLC samples. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 teletext bits including clock run-in bits. For protocol and timing see Fig.17. 1996 Jul 08 9
SAA7182; SAA7183
CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. ANTI-TAPING (SAA7183 ONLY) For more information contact your nearest Philips Semiconductors sales office. RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, Cb, Cr signals are dematrixed, 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. For transfer curves of luminance and colour difference components of RGB see Figs 7 and 8. SECAM processor SECAM specific pre-processing is achieved in this block by a pre-emphasis of colour difference signals (for gain and phase see Figs 9 and 10. A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to DC carries out SECAM modulation in accordance with appropriate standard or optionally wide clipping limits. After the HF pre-emphasis, also applied on a DC reference carrier (anti-Cloche filter; see Figs 11 and 12), line-by-line sequential carriers with black reference of 4.25 MHz (Db) and 4.40625 MHz (Dr) are generated using specified values for FSC programming bytes. Alternating phase reset in accordance with SECAM standard is carried out automatically. During vertical blanking the so-called bottle pulses are not provided.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Output interface/DACs In the output interface encoded both Y and C signals are converted from digital-to-analog in 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 9-bit resolution. Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose. Synchronization Synchronization of the EURO-DENC is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of EURO-DENC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output: * A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or * An ODD/EVEN signal which is LOW in odd fields, or * A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 respectively 12 fields.
SAA7182; SAA7183
On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. Field length is in accordance with 50 Hz or 60 Hz standards, including non-interlaced options; start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line, if the standard blanking option SBLBN is not set. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses are selected: 88H: LOW at pin 4 8CH: HIGH at pin 4. Input levels and formats EURO-DENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with "CCIR 601". For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. For RGB outputs fixed amplification in accordance with "CCIR 601" is provided. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
1996 Jul 08
10
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 1
SAA7182; SAA7183
"CCIR 601" signal component levels
SIGNALS(1)
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Notes 1. Transformation: a) R = Y + 1.3707 x (Cr - 128) b) G = Y - 0.3365 x (Cb - 128) - 0.6982 x (Cb - 128) c) B = Y + 1.7324 x (Cb - 128). 2. Representation of R, G and B at the output is 9 bits at 27 MHz. Table 2 8-bit multiplexed format (similar to "CCIR 601") TIME Sample Luminance pixel number Colour pixel number Table 3 16-bit multiplexed format (DTV2 format) TIME Sample Y line Sample UV line Luminance pixel number Colour pixel number 0 Y0 Cb0 0 0 1 2 Y1 Cr0 1 0 Cb0 0 0 1 Y0 2 Cr0 1 235 210 170 145 106 81 41 16 Cb 128 16 166 54 202 90 240 128 Cr 128 146 16 34 222 240 110 128
R(2) 235 235 16 16 235 235 16 16
G(2) 235 235 235 235 16 16 16 16
B(2) 235 16 235 16 235 16 235 16
2 Y1
4 Cb2 2
5 Y2 2
6 Cr2 3
7 Y3
3
4 Y2 Cb2 2
5
6 Y3 Cr2 3 2
7
1996 Jul 08
11
Bit allocation map
Table 4 DATA BYTE D7 0 0 CBENB OVLY07 OVLU07 OVLV07 OVLY77 OVLU77 OVLV77 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 0 0 DOWNB RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 FSC30 L21O06 L21O16 L21E06 L21E16 FSC22 FSC14 FSC06 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 BSTA6 BSTA5 DOWNA INPI 0 0 0 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 0 BLNVB5 BLNVB4 DECTYP BLNNL5 BLNNL4 0 BLCKL5 BLCKL4 GAINV6 GAINV5 GAINV4 GAINV3 BLCKL3 BLNNL3 BLNVB3 0 SECAM BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 GAINU6 GAINU5 GAINU4 GAINU3 CHPS6 CHPS5 CHPS4 CHPS3 OVLV76 OVLV75 OVLV74 OVLV73 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 OVLU76 OVLU75 OVLU74 OVLU73 OVLU72 OVLV72 OVLY76 OVLY75 OVLY74 OVLY73 OVLY72 OVLY71 OVLU71 OVLV71 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 OVLY70 OVLU70 OVLV70 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 OVLV06 OVLV05 OVLV04 OVLV03 OVLV02 OVLV01 OVLU06 OVLU05 OVLU04 OVLU03 OVLU02 OVLU01 OVLY06 OVLY05 OVLY04 OVLY03 OVLY02 OVLY01 DISKEY 0 0 0 FMT16 Y2C UV2C OVLY00 OVLU00 OVLV00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
1996 Jul 08
Slave Receiver (Slave Address 88H or 8CH)
REGISTER FUNCTION
SUB ADDRESS
Null
00
Philips Semiconductors
Null
39
Input port control
3A
OVL LUT Y0
42
OVL LUT U0
43
OVL LUT V0
44
OVL LUT Y7
57
OVL LUT U7
58
OVL LUT V7
59
Digital Video Encoder (EURO-DENC)
Chrominance phase
5A
12
Gain U
5B
Gain V
5C
Gain U MSB, black level
5D
Gain V MSB, blanking level, decoder type
5E
Blanking level VBI
5F
Null
60
Standard control
61
Burst amplitude
62
Subcarrier 0
63
Subcarrier 1
64
Subcarrier 2
65
Subcarrier 3
66
Line 21 odd 0
67
Line 21 odd 1
68
SAA7182; SAA7183
Line 21 even 0
69
Preliminary specification
Line 21 even 1
6A
DATA BYTE D7 SRCV11 HTRIG7 HTRIG10 SBLBN CCEN1 RCV2S7 RCV2E7 0 TTXHS7 TTXHE7 0 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7 FAL7 LAL7 0 0 0 0 0 0 0 0 0 0 0 0 0 LAL8 0 FAL8 LAL6 LAL5 LAL4 LAL3 TTXEVE8 0 0 0 FAL6 FAL5 FAL4 FAL3 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2 FAL2 LAL2 TTXOVE8 0 0 0 TTXHE10 TTXHE9 TTXHE8 0 TTXHS10 TTXHE6 TTXHE5 TTXHE4 TTXHE3 TTXHE2 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHS1 TTXHE1 TTXHS9 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8 0 0 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0 RCV2S0 RCV2E0 RCV2S8 TTXHS0 TTXHE0 TTXHS8 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8 0 0 0 0 PHRES1 PHRES0 0 0 FLC1 FLC0 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1996 Jul 08
RCV port control
6B
Trigger control
6C
Trigger control
6D
Philips Semiconductors
Multi control
6E
Closed caption/teletext control
6F
RCV2 output start
70
RCV2 output end
71
MSBs RCV2 output
72
TTX request H start
73
TTX request H end
74
MSBs TTX request H
75
TTX odd request V S
76
TTX odd request V E
77
Digital Video Encoder (EURO-DENC)
TTX even request V S
78
13
TTX even request V E
79
First active line
7A
Last active line
7B
MSBs vertical
7C
Null
7D
Null
7E
Null
7F
SAA7182; SAA7183
Preliminary specification
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
I2C-bus format Table 5 S Table 6 I2C-bus address; see Table 6 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
SAA7182; SAA7183
--------
DATA n
ACK
P
Explanation of Table 5 PART DESCRIPTION START condition 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S Slave address ACK Subaddress (note 2) DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A LOGIC LEVEL 0 1 Y2C FMT16 0 1 0 1 DISKEY CBENB 0 1 0 1 DESCRIPTION Cb/Cr data are two's complement. Cb/Cr data are straight binary. Default after reset. Y data are two's complement. Y data are straight binary. Default after reset. Selects Cb, Y, Cr, Y on 8 lines on MP port ("CCIR 656" compatible). Default after reset. Selects Cb, Cr on DP port and Y on MP port. OVL keying enabled for Y, C and CVBS outputs. Default after reset. OVL keying disabled for Y, C and CVBS outputs. Data from input ports are encoded. Default after reset. Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7.
DATA BYTE UV2C
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 8 Subaddress 42 to 59 DATA BYTE (note 1) COLOUR OVLY White Yellow Cyan Green Magenta Red Blue Black 107 (6BH) 107 (6BH) 82 (52H) 34 (22H) 42 (2AH) 03 (03H) 17 (11H) 240 (F0H) 234 (EAH) 212 (D4H) 209 (D1H) 193 (C1H) 169 (A9H) 163 (A3H) 144 (90H) 144 (90H) Notes OVLU 0 (00H) 0 (00H) 144 (90H) 172 (ACH) 38 (26H) 29 (1DH) 182 (B6H) 200 (C8H) 74 (4AH) 56 (38H) 218 (DAH) 227 (E3H) 112 (70H) 84 (54H) 0 (00H) 0 (00H) OVLV 0 (00H) 0 (00H) 18 (12H) 14 (0EH) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) 112 (70H) 84 (54H) 238 (EEH) 242 (F2H) 0 (00H) 0 (00H)
SAA7182; SAA7183
INDEX (note 2) 0 1 2 3 4 5 6 7
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with "CCIR 601" (Y, Cb, Cr), but two's complement, e.g. for a 100100 (upper number) or 10075 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A VALUE 68H 92H 82H A4H Note 1. Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. RESULT PAL-B/G and data from input ports PAL-B/G and data from look-up table NTSC-M and data from input ports NTSC-M and data from look-up table
DATA BYTE(1) CHPS
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 10 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS
SAA7182; SAA7183
REMARKS output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
variable gain for Cb signal; white-to-black = 92.5 IRE(1) input representation GAINU = 0 accordance with GAINU = 118 (76H) "CCIR 601" white-to-black = 100 IRE(2) GAINU = 0 GAINU = 125 (7DH) nominal GAINU for SECAM encoding value = 106 (6AH)
Notes 1. GAINU = -2.17 x nominal to +2.16 x nominal. 2. GAINU = -2.05 x nominal to +2.04 x nominal. Table 11 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION variable gain for Cr signal; input representation accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE(1) GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 GAINV = 0 GAINV = 175 (AFH) nominal GAINV for SECAM encoding Notes 1. GAINV = -1.55 x nominal to +1.55 x nominal. 2. GAINV = -1.46 x nominal to +1.46 x nominal. Table 12 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS IRE(1) output black level = 24 IRE output black level = 49 IRE output black level = 24 IRE output black level = 50 IRE REMARKS value = -129 (17FH) IRE(2) output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal REMARKS
variable black level; input white-to-sync = 140 representation accordance BLCKL = 0 with "CCIR 601" BLCKL = 63 (3FH) white-to-sync = 143 BLCKL = 0 BLCKL = 63 (3FH)
IRE(2)
Notes 1. Output black level/IRE = BLCKL x 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL x 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 13 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE(1) BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 BLNNL = 0 BLNNL = 63 (3FH) DECTYP RTCI logic 0 logic 1 Notes IRE(2)
SAA7182; SAA7183
REMARKS output blanking level = 17 IRE output blanking level = 42 IRE output blanking level = 17 IRE output blanking level = 43 IRE real time control input from SAA7151B real time control input from SAA7111
1. Output black level/IRE = BLNNL x 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL x 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. Table 14 Subaddress 5F DATA BYTE BLNVB DESCRIPTION variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 15 Subaddress 61: DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 858 total pixel clocks per line NTSC encoding (non-alternating V component) PAL encoding (alternating V component); default after reset enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); wide clipping for SECAM standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset no SECAM encoding; default after reset SECAM encoding activated luminance gain for white - black 100 IRE; default after reset luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs for CVBS, Y and C in normal operational mode; default after reset DACs for CVBS, Y and C forced to lowest output voltage DACs for R, G and B in normal operational mode; default after reset DACs for R, G and B forced to lowest output voltage DESCRIPTION 864 total pixel clocks per line; default after reset
1 SECAM YGS INPI DOWNA DOWNB 0 1 0 1 0 1 0 1 0 1
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 16 Subaddress 62A DATA BYTE RTCE LOGIC LEVEL 0 1 DESCRIPTION
SAA7182; SAA7183
no real time control of generated subcarrier frequency real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.16)
Table 17 Subaddress 62B DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 x nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 x nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 x nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 x nominal(4) fixed burst amplitude with SECAM encoding Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 18 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS REMARKS FSC3 = most significant byte FSC0 = least significant byte REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency f fsc 32 FSC = round ------- x 2 (in multiples of line f llc frequency); fllc = clock frequency (in see note 1 multiples of line frequency) Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). c) SECAM: ffsc = 274.304, fllc = 1728 FSC = 681786290 (28A33BB2H).
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 19 Subaddress 67 to 6A DATA BYTE(1) L21O0 L21O1 L21E0 L21E1 Note first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field DESCRIPTION
SAA7182; SAA7183
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format. Table 20 Subaddress 6B DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION polarity of RCV2 as output is active HIGH, rising edge is taken when input; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a `Composite-Blanking-Not' signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is defined by FAL and LAL (PRCV2 must be LOW) if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 0 1 ORCV1 TRCV2 SRCV1 0 1 0 1 - polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port; default after reset horizontal synchronization is taken from RCV2 port defines signal type on pin RCV1; see Table 21
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 21 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 SRCV10 0 1 0 VS FS FSEQ VS FS FSEQ AS INPUT
SAA7182; SAA7183
FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = SECAM = 0), eighth field (PAL = 1) or twelfth field (SECAM = 1) -
1
1
not applicable
not applicable
Table 22 Subaddress 6C, 6D DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 049H (054H) Table 23 Subaddress 6D DATA BYTE VTRIG LOGIC LEVEL - DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) Table 24 Subaddress 6E DATA BYTE SBLBN PHRES FLC LOGIC LEVEL 0 1 - - DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset vertical blanking is forced in accordance with "CCIR 624" (50 Hz) or RS170A (60 Hz) selects the phase reset mode of the colour subcarrier generator; see Table 25 field length control; see Table 26
Table 25 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset reset every two lines or SECAM-specific if bit SECAM = 1 reset every eight fields reset every four fields
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 26 Logic levels and function of FLC DATA BYTE FUNCTION FLC1 0 0 1 1 FLC0 0 1 0 1
SAA7182; SAA7183
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 27 Subaddress 6F DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - disables teletext insertion enables teletext insertion selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems Table 28 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 Line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields DESCRIPTION enables individual line 21 encoding; see Table 28
Table 29 Subaddress 70 to 72 DATA BYTE RCV2S start of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 0F2H (110H) RCV2E end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 67CH (68AH) DESCRIPTION
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Table 30 Subaddress 73 to 75 DATA BYTE TTXHS TTXHE DESCRIPTION start of signal on pin TTXRQ (standard for 50 Hz field rate = 13FH) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
SAA7182; SAA7183
end of signal on pin TTXRQ (standard for 50 Hz field rate = TTXHS + 1402 = 6B9H) values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
Table 31 Subaddress 76, 77 and 7C DATA BYTE TTXOVS TTXOVE DESCRIPTION first line of occurrence of signal on pin TTXRQ in odd field last line of occurrence of signal on pin TTXRQ in odd field
Table 32 Subaddress 78, 79 and 7C DATA BYTE TTXEVS TTXEVE DESCRIPTION first line of occurrence of signal on pin TTXRQ in even field last line of occurrence of signal on pin TTXRQ in even field
Table 33 Subaddress 7A to 7C DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse SUBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Slave Transmitter Table 34 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3
SAA7182; SAA7183
D2 0
D1 FSEQ
D0 O_E
CCRDO CCRDE
Table 35 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ 0 1 O_E 0 1 DESCRIPTION Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current Version is 000 binary. Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. Not first field of a sequence. During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields, SECAM = 12 fields. During odd field. During even field.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.3 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 2.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth 6
MGB707
Gv
(dB)
0 -6
-12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
Fig.5 Total luminance of Y and CVBS; luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
Fig.6 Detailed luminance of Y and CVBS; luminance transfer characteristic 2.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB708
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.7 Luminance transfer characteristic in RGB.
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB706
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.8 Colour difference transfer characteristic in RGB.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth
MGB705
10
Gv (dB) 8
6
4
2
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.9 Gain of SECAM pre-emphasis.
handbook,30 pagewidth full
MGB704
(deg)
20
10
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.10 Phase of SECAM pre-emphasis.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth
MGB703
20
Gv (dB) 16
12
8
4
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.11 Gain of SECAM anti-Cloche.
handbook, full pagewidth
MGB702
80
(deg) 60
40
20
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.12 Phase of SECAM anti-Cloche.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
CHARACTERISTICS VDDD = 4.75 to 5.25 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL Supply VDDD VDDA IDDD IDDA Inputs VIL VIH LOW level input voltage (except SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (LLC) ILI CI input leakage current input capacitance clocks data I/Os at high impedance Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except LLC, SDA, and XTALO) HIGH level output voltage (LLC) I2C-bus; VIL VIH II VOL IO TLLC tr tf tSU tHD SDA and SCL LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current VI = LOW or HIGH IOL = 3 mA during acknowledge note 2 note 2 note 2 digital supply voltage analog supply voltage digital supply current analog supply current note 1 note 1 PARAMETER CONDITIONS
SAA7182; SAA7183
MIN.
MAX.
UNIT
4.75 4.75 - - -0.5 2.0 2.4 - - - -
5.25 5.25 250 110
V V mA mA
+0.8
V
VDDD + 0.5 V VDDD + 0.5 V 1 10 8 8 A pF pF pF
0 2.4 2.6 -0.5 3.0 -10 - 3
0.6
V
VDDD + 0.5 V VDDD + 0.5 V
+1.5 +10 0.4 -
V A V mA
VDDD + 0.5 V
Clock timing (LLC) cycle time duty factor tHIGH/TLLC rise time fall time note 3 note 4 note 3 note 3 34 40 - - 41 60 5 6 - - ns % ns ns
Input timing input data set-up time (any other except CDIR, SCL, SDA, RESET, AP and SP) input data hold time (any other except CDIR, SCL, SDA, RESET, AP and SP) 6 3 ns ns
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 CL tOH tOD Vo(p-p) RI RL B ILE DLE Notes
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 5
30 +50
MHz 10-6 C pF fF pF
-50 0 8 - 1.5 -20% 3.5 -20%
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 70 - 80 1.5 +20% 3.5 +20%
Data and reference signal output timing output load capacitance output hold time output delay time 7.5 4 - 40 - 25 pF ns ns
CHROMA, Y, CVBS and RGB outputs output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs -3 dB note 6 1.9 18 80 10 - - 2.1 35 - - 2 1 V MHz LSB LSB
1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 k to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.13 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 0F8h (110h for 50 Hz) in this example in output mode (RCV2S).
Fig.14 Functional timing.
1996 Jul 08
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
handbook, full pagewidth
LLC
CREF
VP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase. The Cref signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to 0F2h (110h for 50 Hz) in this example in output mode (RCV2S).
Fig.15 Digital TV timing.
handbook, full pagewidth
H/L transition count start LOW 128
13
4 bits reserved HPLL increment
0 21
sequence reserved (2) 5 bits bit (1) reset reserved bit (1) FSCPLL increment (4)
0
RTCI time slot: 0 1
14 19 67 68
not used in SAA7182/83
valid sample
invalid sample
8/LLC
MGB700
(1) Sequence bit: PAL = logic 0 then (R - Y) line normal; PAL = logic 1 then (R - Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.16 RTCI timing.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
Teletext timing Time tFD is the time needed to interpolate input data TTX and inserting it into the CVBS and Y output signal, such that it appears at tTTX = 10.2 s after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. Since the pulse representing the TTXRQ signal is fully programmable in duration and rising/falling edges (TTXHS and TTXHE), it always can be ensured that the TTX data is inserted at the correct position of 10.2 s after the leading edge of outgoing horizontal synchronization pulse. Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits (maximum) at a text data rate of 6.9375 bits/s. The insertion window is not opened if the control bit TTXEN is zero. TELETEXT PROTOCOL The frequency relationship between TTX bit clock and the system clock LLC for 50 Hz field rate is given by the relationship of line frequency multiples, which means 1728/444.
SAA7182; SAA7183
Thus 37 TTX bits correspond to 144 LLC clocks, each bit has a duration of nearly 4 LLC clocks. The chip-internal sequencer and variable phase interpolation filter minimizes the phase jitter, and thus generates a bandwidth limited signal, which is digital-to-analog converted for the CVBS and Y outputs. At the TTX input, bit duration scheme repeats after 37 TTX bits or 144 LLC clocks. The protocol demands that TXX bits 10, 19, 28 and 37 are carried by three LLC samples, all others by four LLC samples. After a cycle of 37 TTX bits, the next bits with three LLC samples are bits 47, 56, 65 and 74; this scheme holds for all succeeding cycles of 37 TTX bits, until 360 TTX bits (including 16 run-in bits) are completed. For every additional line with TTX data, the bit duration scheme starts in the same way. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion.
handbook, full pagewidth
CVBS/Y tTTX textbit #: TTX 4 tPD tFD 3 4 1/LLC 4 3 4 1/LLC 1 2 3 4 5 6 7 8 9 10 11 12 tTTXWin 13 14 15 16 17 18 19 20 21 22 23 24
TTXRQ
MGB701
Fig.17 Teletext timing diagram.
1996 Jul 08
33
VSSD 100 nF VSSA 100 nF VSSA 15 k 100 nF VSSA 100 nF IRGB 63 35 (1) 61 RED 75 VSSA 0.7 V (p-p)(2) GREEN 75 VSSA 0.7 V (p-p)(2) 74 75 BLUE 74 0.7 V (p-p)(2) 68 74 72 70 64 60 57 54 IY/C/CVBS VDDA7 VDDA6 VDDA5 VSSA VDDA4 VDDA3 VDDA2 VDDA1 VSSA 100 nF VSSA 100 nF VSSA 100 nF
dbook, full pagewidth
1996 Jul 08
+5 V analog VSSA VSSA 15 k 100 nF 100 nF 35 (1) 58 74 35 (1) 55
10 H
10 pF
1 nF
X1 27.0 MHz (3)
10 pF
Philips Semiconductors
3rd harmonic
XTALI
XTALO
APPLICATION INFORMATION
44
45
digital inputs and outputs
100 nF
VSSD
VDDD1 5
100 nF
Digital Video Encoder (EURO-DENC)
VSSD
VDDD2 14
34
SAA7182 SAA7183
53 VrefH1 100 nF 100 nF VrefH2 VrefL2 75 76 3, 15, 24, 30, 39, 42, 51, 79, 81 VSSD1 to VSSD9 67
100 nF
VSSD
VDDD3 22
100 nF
VSSD
VDDD4 29
35 (1) 73
12 75
VSSA 1.23 V (p-p)(2) CVBS
100 nF
VSSD
VDDD5 38 35 (1) 71
100 nF
VSSD
VDDD6 41
20 75
VSSA 1.0 V (p-p)(2) Y
100 nF
VSSD
VDDD7 49 35 (1) 69
100 nF
VSSD
VDDD8 80
20 75 VSSA
MGB698
VSSA 0.62 V (p-p)(2) CHROMA
100 nF
VSSD
VDDD9 82
52
+5 V digital
VrefL1
VSSA
(1) Typical value. (2) For 100/100 colour bar. (3) Philips 12NC ordering code: 4312 065 02341.
SAA7182; SAA7183
Preliminary specification
Fig.18 Application environment of the EURO-DENC.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
PACKAGE OUTLINE PLCC84: plastic leaded chip carrier; 84 leads
SAA7182; SAA7183
SOT189-2
eD y 74 75 X 54 53 Z E A
eE
bp b1 wM 84 HE A A4 A1 (A 3) k1 Lp detail X 12 e D HD 0 5 scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
1
pin 1 index e
E
k
11 32 ZD
33
vM A B vMB 10 mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30 0.13
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
29.41 29.41 28.70 28.70 30.35 30.35 1.22 1.27 29.21 29.21 27.69 27.69 30.10 30.10 1.07
45 o
0.180 0.020 0.01 0.165
1.130 1.130 1.195 1.195 0.048 0.057 0.021 0.032 1.158 1.158 0.020 0.05 0.007 0.007 0.004 0.085 0.085 1.090 1.090 1.185 1.185 0.042 0.040 0.013 0.026 1.150 1.150
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT189-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Jul 08
35
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA7182; SAA7183
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 08
36
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7182; SAA7183
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jul 08
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
NOTES
SAA7182; SAA7183
1996 Jul 08
38
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
NOTES
SAA7182; SAA7183
1996 Jul 08
39
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7182_83_2 June 26, 1996 11:51 am SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
657021/1200/02/pp40 Date of release: 1996 Jul 08 Document order number: 9397 750 00951

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