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DATA SHEET
MOS INTEGRATED CIRCUIT
mPD78P368A
16/8 BIT SINGLE-CHIP MICROCOMPUTER
The mPD78P368A is produced by replacing the internal mask ROM of the mPD78366A with a one-time PROM or EPROM. One-time PROM products, in which data can be written once are effective for manufacture of small quantities of multiple products and early stage start-up of application. EPROM products, to which programs can be re-written after previously written programs have been erased, are suited for system evaluation. The following user's manual describes the details of functions. Be sure to read it before design.
mPD78366A User's Manual, Hardware: U10205E mPD78356 User's Manual, Instructions: IEU-1395
FEATURES * Compatible with the mPD78366A
* Can be replaced with the mPD78366A containing mask ROM on a full-production basis.
* Internal PROM: 48K bytes
* Data can be written once (one-time PROM product without an erasure window) * Written data can be erased by exposure to ultraviolet light and re-written electrically (EPROM product with an erasure window)
* PROM programming characteristics: Compatible with the mPD27C1001A * QTOPTM microcomputer
Remark The QTOP microcomputer is a single-chip microcomputer with a built-in one-time PROM that is totally supported by NEC. The support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 20 mm) 80-pin ceramic WQFN Internal ROM One-time PROM EPROM
mPD78P368AGF-3B9 mPD78P368AKL-S Note
Note Under development
In this manual, the description of the PROM is for both a one-time PROM and EPROM.
The information in this document is subject to change without notice.
Document No. U11373EJ1V0DS00 (1st edition) (Previous No. IP-3680) Date Published June 1996 P Printed in Japan
The mark H shows major revised points.
(c)
1996 1990
mPD78P368A
PIN CONFIGURATION (TOP VIEW)
(1) Normal operation mode (MODE0 = L, MODE1 = L) * 80-pin plastic QFP (14 20 mm)
mPD78P368AGF-3B9
* 80-pin ceramic WQFN
mPD78P368AKL-S
P85/TO05 P84/TO04 P83/TO03 P82/TO02 P81/TO01 P80/TO00 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P91/WR P90/RD ASTB
P93
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 P04/PWM0 P05/ TCUD/PWM1 P06/ TIUD/TO40 P07/ TCLRUD
WDTO IC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P92
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 VSS VDD AVDD AVREF P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVSS
VDD VSS X1 X2 MODE1 RESET P30/ TXD0 P31/RXD0 P32/SO/SB0 P33/SI/SBI P34/SCK P35/ TXD1 P36/RXD1
P24/INTP3/TI
P14
P15
P16
P17
VSS
MODE0
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2
Caution Directly connect the IC pin to VSS. Remark Pin compatible with the mPD78366AGF
2
P25/INTP4
P10
P11
P12
P13
mPD78P368A
P00-P07: P10-P17: P20-P25: P30-P36: P40-P47: P50-P57: P70-P77: P80-P85: P90-P93: RTP0-RTP3: NMI: INTP0-INTP4: TI: TIUD: TCUD: TCLRUD: ANI0-ANI7: TxD0, TxD1: RxD0, RxD1: Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 7 Port 8 Port 9 Real-time port Nonmaskable interrupt Interrupt from peripherals Timer input Timer input for up/down counter Timer control for up/down counter Timer clear for up/down counter Analog input Transmit data Receive data SI: SO: SB0, SB1: SCK: PWM0, PWM1: WDTO: MODE0, MODE1: AD0-AD7: A8-A15: ASTB: RD: WR: RESET: X1, X2: AVDD: AVSS: AVREF: VDD: VSS: IC: Serial input Serial output Serial bus Serial clock Pulse width modulation output Watchdog timer output Mode Address/data bus Address bus Address strobe Read strobe Write strobe Reset Crystal Analog VDD Analog VSS Analog reference voltage Power supply Ground Internally connected
TO00-TO05, TO40: Timer output
3
mPD78P368A
(2) PROM programming mode (MODE0/VPP = H, MODE1 = L) * 80-pin plastic QFP (14 20 mm)
mPD78P368AGF-3B9
* 80-pin ceramic WQFN
mPD78P368AKL-S
(L) A12 PGM A15 A14 A13 A11 A10 OE CE (L)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSS A0 A1 A2 A3 A4 A5 A6 A7
(Open) (G)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (G) D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD VDD (L)
VDD VSS
(G) (Open)
MODE1
(G)
A16
(L)
21 22 23 24
VSS
MODE0/VPP
A9
A8
Caution Symbols in parentheses denote how the pins not used in the PROM programming mode should be treated. L: G: Connect these pins to the VSS pins through separate resistors. Connect these pins to the VSS pins.
Open: Do not connect these pins to anything.
4
(G)
(L)
mPD78P368A
A0-A16: Address bus D0-D7: CE: OE: PGM: Data bus Chip enable Output enable Programming mode MODE0, MODE1: VPP: VDD: VSS: Programming mode set Programming power supply Power supply Ground
5
6
EXU Main RAM X2 RESET ASTB ALU WR MODE1 MODE0/ VPPNote 8 8 17 8 A8-A15 AD0-AD7 A0-A16 D0-D7
Note
PROM/RAM BCU X1
NMI
5
INTP RD PROM 48K x 8 & Peripheral RAM 1792 x 8
5
Programmable interrupt controller
BLOCK DIAGRAM
4
General registers 128 x 8 & Data memory 128 x 8
TO Micro sequence control Micro ROM
7
System control & Bus control & Prefetch control
TI
Timer/counter unit (Real-time pulse unit)
TIUD PGM CE OE
TCUD
TCLRUD
SCK
SO/SB0
SI/SB1 A/D converter
TxD
2
Serial interface (SBI) (UART) PWM
Watchdog timer
Port
RxD
2
2
4
6
8
8
8
7
6
8
8
8 2 AVDD WDTO ANI AVSS 4 PWM AVREF INTP2
P9
P8
P7
P3
P2
P1
P0
P5
P4
RTP
4
Real-time output port
mPD78P368A
Note Shading indicates the pins used in the PROM programming mode.
VSS
VDD
mPD78P368A
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1 1.2 1.3 NORMAL OPERATION MODE (MODE0 = L, MODE1 = L) ......................................................... PROM PROGRAMMING MODE (MODE0/VPP = H, MODE1 = L) ................................................ INPUT/OUTPUT CIRCUIT TYPE FOR EACH PIN AND HANDLING OF UNUSED PINS ..........
8
8 10 11
2. 3. 4.
MEMORY CONFIGURATION ................................................................................................... DIFFERENCES BETWEEN THE mPD78P368A AND mPD78366A ......................................... PROM PROGRAMMING ............................................................................................................
4.1 4.2 4.3 4.4 OPERATION MODE ........................................................................................................................ PROCEDURE FOR WRITING ON PROM (PAGE PROGRAM MODE) ............................... PROCEDURE FOR WRITING ON PROM (BYTE PROGRAM MODE) ................................ PROCEDURE FOR READING FROM PROM ...........................................................................
13 14 15
15 16 18 21
5. 6. 7. 8. 9.
ERASURE CHARACTERISTICS (mPD78P368AKL-S ONLY) ................................................ PROTECTIVE FILM COVERING THE ERASURE WINDOW (mPD78P368AKL-S ONLY) ........ SCREENING ONE-TIME PROM PRODUCTS .......................................................................... ELECTRICAL SPECIFICATIONS ............................................................................................. PACKAGE DRAWINGS .............................................................................................................
22 22 22 23 39 41 42
42 47 H H
10. RECOMMENDED SOLDERING CONDITIONS ...................................................................... APPENDIX A TOOLS ......................................................................................................................
A.1 A.2 DEVELOPMENT TOOLS ................................................................................................................ EMBEDDED SOFTWARE ...............................................................................................................
APPENDIX B DIMENSIONS OF THE CONVERSION SOCKET AND RECOMMENDED PATTERN ON BOARDS.........................................................................................
49
7
mPD78P368A
1. PIN FUNCTIONS
1.1 NORMAL OPERATION MODE (MODE0 = L, MODE1 = L) (1) Port pins
Pin name P00-P03 P04 P05 P06 P07 P10-P17
I/O I/O
Function Port 0. 8-bit I/O port. Can be specified as input or output bit by bit.
Dual-function pin RTP0-RTP3 PWM0 TCUD/PWM1 TIUD/TO40 TCLRUD
I/O
Port 1. 8-bit I/O port. Can be specified as input or output bit by bit. Port 2. Port used only for 6-bit input.
-
P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P35 P36 P40-P47
I
NMI INTP0 INTP1 INTP2 INTP3/TI INTP4
I/O
Port 3. 7-bit I/O port. Can be specified as input or output bit by bit.
TxD0 RxD0 SO/SB0 SI/SB1 SCK TxD1 RxD1
I/O
Port 4. 8-bit I/O port. Can be specified as input or output in units of 8 bits. Port 5. 8-bit I/O port. Can be specified as input or output bit by bit. Port 7. Port used only for 8-bit input. Port 8. 6-bit I/O port. Can be specified as input or output bit by bit. Port 9. 4-bit I/O port. Can be specified as input or output bit by bit.
AD0-AD7
P50-P57
I/O
A8-A15
P70-P77
I
ANI0-ANI7
P80-P85
I/O
TO00 - TO05
P90 P91 P92 P93
I/O
RD WR - -
8
mPD78P368A
(2) Non-port pins (1/2)
Pin name RTP0-RTP3
I/O O
Function Outputs a pulse in real time as triggered by a trigger signal sent from the real-time pulse unit. Nonmaskable interrupt request input External interrupt request input
Dual-function pin P00-P03
NMI INTP0 INTP1 INTP2 INTP3 INTP4 TI TCUD
I
P20 P21 P22 P23 P24/TI P25
I
External count clock input to timer 1 Input for the control signal to determine whether the up/down counter (timer 4) counts up or down. External count clock input to the up/down counter (timer 4) Clear signal input to the up/down counter (timer 4)
P24/INTP3 P05/PWM1
TIUD TCLRUD TO00-TO05 TO40 ANI0-ANI7 TxD0 TxD1 RxD0 RxD1 SCK SI SO I/O I O I I O O
P06/TO40 P07 P80-P85 P06/TIUD
Pulse output from the real-time pulse unit
Analog input to the A/D converter Serial data output from the asynchronous serial interface
P70-P77 P30 P35
Serial data input to the asynchronous serial interface
P31 P36
Serial clock I/O for the clock synchronous serial interface Serial data input to the clock synchronous serial interface in the 3-wire mode Serial data output from the clock synchronous serial interface in the 3-wire mode Serial data I/O for the clock synchronous serial interface in the SBI mode
P34 P33/SB1 P32/SB0
SB0 SB1 PWM0 PWM1 WDTO
I/O
P32/SO P33/SI
O
PWM signal output
P04 P05/TCUD
O
Output for the signal which indicates the watchdog timer overflowed. (A nonmaskable interrupt is generated.) Multiplexed address/data bus used when external memory is expanded Address bus used when external memory is expanded
-
AD0-AD7 A8-A15 ASTB
I/O
P40-P47 P50-P57 -
O
Output for the timing signal used in externally latching address information output from the AD0 to AD7 and A8 to A15 pins, in order to access the external memory Read strobe signal output to the external memory Write strobe signal output to the external memory
RD WR
P90 P91
9
mPD78P368A
(2) Non-port pins (2/2)
Pin name MODE0 MODE1 RESET X1 X2 AVREF AVDD AVSS VDD VSS IC
I/O I
Function Input for the control signal which sets the operation mode. Normally, both MODE0 and MODE1 are directly connected to the VSS pin. System reset input Crystal input pin for the system clock. A clock signal provided externally is input to the X1 pin. The reversed signal of the clock signal is input to the X2 pin. A/D converter reference voltage input Analog power supply for the A/D converter Ground for the A/D converter Positive power supply Ground Internally connected. Directly connect the IC pin to VSS.
Dual-function pin -
I I - I - - - - -
- -
- - - - - -
1.2 PROM PROGRAMMING MODE (MODE0/VPP = H, MODE1 = L)
Pin name MODE0/VPP MODE1 A0-A16 D0-D7 PGM CE OE VDD VSS
I/O I I I I/O I I I
Function PROM programming mode set/programming supply voltage PROM programming mode set Address bus Data bus Program input Enable PROM Read strobe to PROM Positive power supply GND
10
mPD78P368A
1.3 INPUT/OUTPUT CIRCUIT TYPE FOR EACH PIN AND HANDLING OF UNUSED PINS Table 1-1 lists the input and output circuit type for each pin and how to handle it when it is not used. Fig. 1-1 shows the circuits. Table 1-1 Input/Output Circuit Type for Each Pin and Recommended Connection Methods for Unused Pins
Pin P00/RTP0-P03/RTP3 P04/PWM0 Output state: P05/TCUD/PWM1 P06/TIUD/TO40 P07/TCLRUD P10-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3/TI P25/INTP4 P30/TxD0 P31/RxD0 Output state: P32/SO/SB0 P33/SI/SB1 P34/SCK P35/TxD1 P36/RxD1 P40/AD0-P47/AD7 P50/A8-P57/A15 P70/ANI0-P77/ANI7 P80/TO00-P85/TO05 P90/RD Output state: P91/WR P92, P93 ASTB WDTO MODE0, MODE1 RESET AVREF, AVSS AVDD 5 19 1 2 - Connected to the VSS pin. Connected to the VDD pin. Connected to the VSS pin. - 9 5-A Connected to the VSS pin. Input state: Each pin is connected to the VDD or VSS pin via a separate resistor. Open 5-A 8-A 5-A Input state: Each pin is connected to the VDD or VSS pin via a separate resistor. Open 2 2-A Connected to the VSS pin. I/O circuit type 5-A Recommended connection method Input state: Each pin is connected to the VDD or VSS pin via a separate resistor. Open
11
mPD78P368A
Fig. 1-1 Input/Output Circuits of Each Pin
Type 1
Type 5-A
VDD P-ch VDD P-ch IN/OUT N-ch
VDD
Pull-up enable
P-ch IN N-ch
Data Output disable Input enable
Type 2
Type 8-A
Pull-up enable Data Output disable VDD P-ch
VDD P-ch
IN
IN/OUT N-ch
Schmitt trigger input with hysteresis characteristics
Type 2-A
VDD
Type 9 Comparator P-ch IN
P-ch Pull-up enable
N-ch Vref
+ - (Threshold voltage)
IN Schmitt trigger input with hysterisis characteristics
Input enable Type 19
Type 5
VDD P-ch IN/OUT
Data Output disable
OUT N-ch
N-ch
Input enable
12
mPD78P368A
2. MEMORY CONFIGURATION
The mPD78P368A can access memory of up to 64K bytes. Fig. 2-1 shows the memory map. Fig. 2-1 Memory Map
MODE 0, 1 = LL FFFFH Special function register (SFR) (256 x 8)
FEFFH FE80H
FF00H FEFFH
General register (128 x 8) Macro service control (32 x 8)
Main RAM (256 x 8) Data memory FE00H FDFFH Peripheral RAM (1792 x 8) F700H F6FFH Memory space (64K x 8)
FE25H FE06H
Data area (2048 x 8) F700H
BFFFH Program area External memoryNote (14080 x 8) 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area (64 x 8) 0040H 003FH Vector table area (64 x 8) 0000H 0000H CALLF instruction entry area (2048 x 8) Program area
Program memory Data memory
C000H BFFFH
Internal PROM (49152 x 8)
Note Access in the external memory expansion mode. Caution When word access (including the stack operation) to the main RAM space (FE00H to FEFFH) is executed, the addresses specified in the operand must be even numbers.
13
mPD78P368A
3. DIFFERENCES BETWEEN THE mPD78P368A AND mPD78366A
The mPD78P368A is produced by replacing the internal mask ROM of the mPD78366A with a 48K-byte PROM. Both have the same functions except some differences in ROM specifications, such as write and verify modes. Table 3-1 shows the differences. In this manual, the functions specific to the mPD78P368A are explained. For details of the other functions, refer to the mPD78366A document. Table 3-1 Differences between the mPD78P368A and mPD78366A
Part number Item ROM Internal program memory (Electrical write) PROM programming pin Setting of MODE0 and MODE1 48K bytes One-time PROM (Data can be written once) Provided * Normal operation mode MODE0, 1 = LL * PROM programming mode MODE0, 1 = HL 80-pin plastic QFP 80-pin ceramic WQFN EPROM (Data can be written multiple times)
mPD78P368A
mPD78366A
32K bytes Mask ROM
Not provided * Normal operation mode MODE0, 1 = LL * ROM-less mode MODE0, 1 = HH 80-pin plastic QFP
Package Electrical characteristics Others
They differ in supply current and other factors. Since each product has a different circuit scale and mask layout, the noise immunity and noise radiation of each product differ.
Cautions 1. The PROM and mask ROM products differ in noise immunity and noise radiation. Use not ES products but CS products (mask ROM products) to evaluate them thoroughly when considering the change from the PROM products to the mask ROM products during processes from preproduction to volume production. 2. Connect the MODE0 and MODE1 pins directly to the VDD or VSS pin.
14
mPD78P368A
4. PROM PROGRAMMING
The mPD78P368A is provided with an electrically writable PROM of 48K 8 bits. When programming this PROM, use the MODE0/VPP and MODE1 pins to set the mPD78P368A to the PROM programming mode. The mPD78P368A provides programming characteristics compatibility with the mPD27C1001A. Table 4-1 Pin Functions in Programming Mode
Function Address input Data input Program pulse Chip enable Output enable Program voltage Mode control
Normal operation mode P00-P07, P21, P20, P80-P85, P30 P40-P47 ASTB P91 P90 MODE0/VPP MODE1
Programming mode A0-A16 D0-D7 PGM CE OE
4.1 OPERATION MODE To enter the program write/verify mode, set each pin as follows: MODE0/VPP = H, MODE1 = L. In addition, any of the operation modes listed in Table 4-2 can be selected by setting the CE, OE, and PGM pins in this mode. Set the mPD78P368A to the read mode in order to read the contents of PROM. Handle unused pins as described in PIN CONFIGURATION (2). Table 4-2 Operation Modes for PROM Programming
Mode Page data latch Page program Byte program Program verify Program inhibit MODE1 L CE H H L L L L H OE L H H L L H L H PGM H L L H L H H +5 V +5 V MODE0/VPP +12.5 V VDD +6.5 V D0-D7 Data input High impedance Data input Data output High impedance
Read Output disable Standby
Data output High impedance High impedance
Remark : L or H
15
mPD78P368A
4.2 PROCEDURE FOR WRITING ON PROM (PAGE PROGRAM MODE)
The following is a procedure for writing on PROM. (See Fig. 4-1.) In the page program mode, data is written in units of pages (four bytes). When write data completes midway of a page, latch FFH after the data so that the data fits into pages. (1) (2) (3) (4) (5) (6) (7) (8) Always set each pin as follows: MODE0/VPP = H and MODE1 = L. Connect unused pins according to PIN CONFIGURATION (2). Apply +6.5 V to the VDD pin and +12.5 V to the VPP pin. Input an initial address to the A0 to A16 pins. Clear the page counter. Data latch mode. Input write data to the D0 to D7 pins and input an active-low pulse to the OE pin. Increment the address and the page counter. Repeat step (5) for a page (four bytes). Input a 0.1 ms program pulse (active low) to the PGM pin. Verify mode. Checks if data has been written in PROM. Apply a low level to the CE pin, input an active-low pulse to the OE pin, and then read the write data from the D0 to D7 pins. Repeat this for a page (four bytes). When verification completes, apply a high level to the CE pin. * If data has been written, go to step (10). * If not, repeat steps (7) and (8). If no data is written yet after the steps have been repeated 10 times, go to step (9). (9) Assume the device to be defective and stop write operation. (10) Increment the address. (11) Repeat steps (4) to (10) until the address exceeds the last address. Fig. 4-2 is a timing chart of these steps (2) to (9).
16
mPD78P368A
Fig. 4-1 Flowchart of Procedure for Writing (Page Program Mode)
(1)
Start writing
(2)
Apply power supply voltage
(3)
Set an initial address
(4)
Clear the counter to 0
(5)
Latch write dataNote
Increment the address and counter
(6) < 4 bytes Counter
= 4 bytes
(7)
Input a program pulse
Write failure (up to 9th)
(8) Write failure (10th) Verify mode
Write succeeded (10) Increment the address
(11) Last address Last address
> Last address Write is completed
(9) Defective device
Note If write data does not fill a page, latch FFH for the rest of the page.
17
mPD78P368A
Fig. 4-2 PROM Write/Verify Timing Chart (Page Program Mode)
Page data latch Page program Program verify
A2 - A16
Address input
A0, A1 Data input D0 - D7 Hi-Z
Address input Data output Hi-Z Hi-Z
+12.5 V MODE0/VPP VDD +6.5 V VDD VDD
CE (input)
PGM (input)
OE (input)
4.3
PROCEDURE FOR WRITING ON PROM (BYTE PROGRAM MODE)
The following is a procedure for writing on PROM. (See Fig. 4-3.) (1) (2) (3) (4) (5) (6) Always set each pin as follows: MODE0/VPP = H and MODE1 = L. Connect unused pins according to PIN CONFIGURATION (2). Apply +6.5 V to the VDD pin and +12.5 V to the MODE0/VPP pin, and input a low-level signal to the CE pin. Input an initial address to the A0 to A16 pins. Input write data to the D0 to D7 pins. Input a 0.1 ms program pulse (active low) to the PGM pin. Verify mode. Checks if data has been written in PROM. Input an active-low pulse to the OE pin and read the write data from the D0 to D7 pins. * If data has been written, go to step (8). * If not, repeat steps (4) to (6). If no data is written yet after the steps have been repeated 10 times, go to step (7). (7) (8) (9) Assume the device to be defective and stop write operation. Increment the address. Repeat steps (4) to (8) until the address exceeds the last address. Fig. 4-4 is a timing chart of these steps (2) to (7).
18
mPD78P368A
Fig. 4-3 Flowchart of Procedure for Writing (Byte Program Mode)
(1)
Start writing
(2)
Apply power supply voltage
(3)
Set an initial address
(4)
Input write data
(5)
Input a program pulse
(6) Write failure (up to 9th) Verify mode Write failure (10th)
Write succeeded (8) Increment the address
(9) Last address Last address
> Last address Write is completed
(7) Defective device
19
mPD78P368A
Fig. 4-4 PROM Write/Verify Timing Chart (Byte Program Mode)
Byte program
Program verify
A0 - A16
Address input
D0 - D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
+12.5 V MODE0/ VPP VDD +6.5 V VDD VDD
CE (input)
PGM (input)
OE (input)
20
mPD78P368A
4.4 PROCEDURE FOR READING FROM PROM
The following is a procedure for reading out the contents of PROM to the external data bus (D0 to D7). (1) (2) (3) (4) (5) Always set each pin as follows: MODE0/VPP = H and MODE1 = L. Connect unused pins according to PIN CONFIGURATION (2). Apply +5 V to the VDD and MODE0/VPP pins. Input the address of data to be read into the A0 to A16 pins. Read mode (CE = L, OE = L) Output the data on the D0 to D7 pins. Fig. 4-5 is a timing chart of these steps (2) to (5). Fig. 4-5 PROM Read Timing Chart
A0 - A16
Address input
CE (input)
OE (input)
D0 - D7
Hi-Z
Data output
Hi-Z
21
mPD78P368A
5. ERASURE CHARACTERISTICS (mPD78P368AKL-S ONLY)
Data written in the mPD78P368AKL-S program memory can be erased (FFH); therefore users can write other data in the memory. To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally, ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data is as follows: * Intensity of ultraviolet light erasing time: 15 W*s/cm2 min. * Erasing time: 15 to 20 minutes (When using a 12,000 mW/cm2 ultraviolet lamp. It may, however, take more time due to lamp deterioration, dirt on the erasure window, or the like.) The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter is attached to the ultraviolet lamp, remove the filter before erasure.
6. PROTECTIVE FILM COVERING THE ERASURE WINDOW (mPD78P368AKL-S ONLY) m
After the erasure window of the mPD78P368AKL-S has been exposed to sunlight or a fluorescent lamp for a long time, data in EPROM may be erased and the internal circuits may malfunction. To prevent these failures, the erasure window should be covered with a protective film when it is not used for erasure. EPROM package products with a window are supplied with a NEC-guaranteed protective film when they are delivered.
7.
SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (mPD78P368AGF-3B9) due to their structure
before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125 C for 24 hours. NEC offers a charged service called QTOP microcomputer service. This service includes writing to one-time PROM, marking, screening, and verification. Ask your sales representative for details.
22
mPD78P368A
8. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Power supply voltage Symbol VDD AVDD VPP AVSS Input voltage VI Pins other than P70/ANI0-P77/ANI7 Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD + 0.5 Unit V V V V V
H
Output voltage Low-level output current
VO IOL
Note
-0.5 to VDD + 0.5 20 4.0
V mA mA
Output pins other than those in the note Total of all output pins High-level output current IOH All output pins Total of all output pins Analog input voltage A/D converter reference input voltage Operating ambient temperature Storage temperature VIAN AVREF TA Tstg P70/ANI0-P77/ANI7 pins
200 -3.0 -25 AVSS - 0.5 to AVDD + 0.5 AVSS - 0.5 to AVDD + 0.5 -40 to +85 -60 to +150
mA mA mA V V C C
Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, P10-P17, and P80/TO00-P85/TO05 pins. Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values. RECOMMENDED OPERATING CONDITIONS
Oscillation frequency 3 MHz - fXX - 8 MHz TA -40 to +85 C VDD +5.0 V 10 %
CAPACITANCE (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V except measured pins Conditions Min. Typ. Max. 20 20 20 Unit pF pF pF
23
mPD78P368A
OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Resonator Ceramic resonator or crystal Recommended circuit Parameter Oscillation frequency (fXX)
VSS X1 X2
Min. 3
Max. 8
Unit MHz
C1
C2
External clock
X1 X2 Open HCMOS inverter
X1 input frequency (fX)
3
8
MHz
X1 rise/fall time (tXR, tXF)
0
30
ns
X1 input high-/low-level width (tWXH, tWXL)
40
170
ns
Caution When using system clock oscillation circuits, to reduce the effect of the wiring capacitance, etc, wire the area indicated by dotted-line as follows: * Make the wiring as short as possible. * Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which varying high currents flow. * Make sure that the ground point of the oscillation circuit capacitor is always at the same electric potential as VSS. Do not allow the wiring to be grounded to a ground pattern in which very high currents are flowing. * Do not extract signals from the oscillation circuit.
24
mPD78P368A
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter Low-level input voltage Symbol VIL1 VIL2 High-level input voltage VIH1 VIH2 Low-level output voltage VOL1 VOL2 VOL3 High-level output voltage Input leakage current Output leakage current VDD supply current VOH ILI ILO IDD1 IDD2 Data retention voltage Data retention current VDDDR IDDDR
Note 1 Note 2 Note 1 Note 2 Note 3 Note 4 Note 5
Conditions
Min. 0 0 2.2 0.8VDD
Typ.
Max. 0.8 0.2VDD
Unit V V V V
IOL = 2.0 mA IOL = 15 mA IOL = 10 mA VDD - 1.0
0.45 1.5 1.5
V V V V
IOH = -400 mA 0 V - VI - VDD, AVDD = VDD 0 V - VO - VDD, AVDD = VDD Operating mode HALT mode STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5.0 V 10 %
10 10 70 45 2.5 2 10 15 60 10 50 150 120 70
mA mA
mA mA V
mA mA
Ky
Pull-up resistance
RL
VI = 0 V
Notes 1. Pins other than those specified in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/SO/ SB0, P33/SI/SB1 and P34/SCK pins. 3. Pins other than those specified in Notes 4 and 5. 4. P80/TO00-P85/TO05 pins (When IOL = 15 mA is in operation, up to three pins can be ON simultaneously.) 5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins (When IOL = 10 mA is in operation, up to four pins can be ON simultaneously.) as well as P10-P17 pins (When IOL = 10 mA is in operation, up to four pins can be ON simultaneously.). Caution When the P80-P85, P00-P07, and P10-P17 pins are not used under the conditions specified in Notes 4 and 5, they have the same characteristics as in Note 3.
25
mPD78P368A
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V, CL = 100 pF, fXX = 8 MHz) Read/Write Operation (when general-purpose memory is connected)
Parameter System clock cycle time Address setup time (vs. ASTB O) Address hold time (vs. ASTB O) RD O AE address float time Address AE data input time RD O AE data input time ASTB O AE RD O delay time Data hold time (vs. RD *) RD * AE address active time RD low-level width ASTB high-level width WR O AE data output time ASTB O AE WR O delay time WR * AE ASTB * delay time Data setup time (vs. WR *) Data hold time (vs. WR *) WR low-level width Symbol tCYK tSAST tHSTA tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDWOD tDSTW tDWST tSODW tHWOD tWWL 15 78 57 8 63 15 0 17 63 14 21 Conditions Min. 62.5 7 11 24 100 49 Max. 166.7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCYK-dependent Bus Timing Definition
Parameter tSAST tHSTA tWSTH tDSTR tWRL tDAID tDRID tDRA tDSTW tDWST tWWL tDWOD tSODW Arithmetic expression (0.5 + a) T - 24 0.5T - 20 (0.5 + a) T - 17 0.5T - 16 (1.5 + n) T - 30 (2.5 + a + n) T - 56 (1.5 + n) T - 44 0.5T - 14 0.5T - 16 1.5T - 15 (1.5 + n) T - 30 0.5T - 10 (1 + n) T - 5 Min./Max. Min. Min. Min. Min. Min. Max. Max. Min. Min. Min. Min. Max. Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.) 2. a becomes 1 when the address wait is inserted. Otherwise, it becomes 0. 3. n refers to the number of wait cycles that is inserted by specifying the PWC register. 4. Only the bus timings indicated in this table depend on tCYK.
26
mPD78P368A
SERIAL OPERATION (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK SCK output SCK input Serial clock low-level width tWSKL SCK output SCK input Serial clock high-level width tWSKH SCK output SCK input SI setup time (vs. SCK *) SI hold time (vs. SCK *) SCK O AE SO delay time tSRXSK tHSKRX tDSKTX R = 1 ky, C = 100 pF Conditions Internal 8 dividing External clock Internal 8 dividing External clock Internal 8 dividing External clock Min. 500 500 210 210 210 210 80 80 210 Max. Unit ns ns ns ns ns ns ns ns ns
UP/DOWN COUNTER OPERATION (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter TIUD high-/low-level width Symbol tWTIUH, tWTIUL Conditions Other than mode 4 Mode 4 TCUD high-/low-level width tWTCUH, tWTCUL Other than mode 4 Mode 4 TCLRUD high-/low-level width TCUD setup time (vs. TIUD *) TCUD hold time (vs. TIUD *) TIUD setup time (vs. TCUD) TIUD hold time (vs. TCUD) TIUD & TCUD cycle time tWCLUH, tWCLUL tSTCU tHTCU tS4TIU tH4TIU tCYC tCYC4 Mode 3 Mode 3 Mode 4 Mode 4 Other than mode 4 Mode 4 Min. 2T 4T 2T 4T 2T T T 2T 2T 4 2 Max. Unit ns ns ns ns ns ns ns ns ns MHz MHz
Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)
27
mPD78P368A
OTHER OPERATIONS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter NMI high-/low-level width RESET high-/low-level width INTP0 high-/low-level width Symbol tWNIH, tWNIL tWRSH, tWRSL tWI0H, tWI0L Ts = T Ts = 4T Ts = 8T Ts = 16T INTP1 high-/low-level width tWI1H, tWI1L Ts = T Ts = 4T Ts = 8T Ts = 16T INTP2 high-/low-level width tWI2H, tWI2L Ts = T Ts = 4T INTP3(TI) high-/low-level width tWI3H, tWI3L Ts = T Ts = 4T Ts = 8T Ts = 16T Ts = 64T Ts = 128T Ts = 256T INTP4 high-/low-level width tWI4H, tWI4L Ts = T Ts = 4T Ts = 8T Ts = 16T Conditions Min. 2 1.5 250 1.0 2.0 4.0 250 1.0 2.0 4.0 250 1.0 250 1.0 2.0 4.0 16.0 32.0 64.0 250 1.0 2.0 4.0 Max. Unit
ms ms
ns
ms ms ms
ns
ms ms ms
ns
ms
ns
ms ms ms ms ms ms
ns
ms ms ms
Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.) 2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.
28
mPD78P368A
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD - 0.5 V - AVDD - VDD)
Parameter Resolution Total error Note 1 4.5 V - AVREF - A VDD 3.4 V - AVREF - A VDD Quantization error Conversion time tCONV 62.5 ns - tCYK < 80 ns 80 ns - tCYK - 166.6 ns Sampling time tSAMP 62.5 ns - tCYK < 80 ns 80 ns - tCYK - 166.6 ns Zero-scale error Note 1 4.5 V - AVREF - A VDD 3.4 V - AVREF - A VDD Full-scale error Note 1 4.5 V - AVREF - A VDD 3.4 V - AVREF - A VDD Nonlinearity error Note 1 4.5 V - AVREF - A VDD 3.4 V - AVREF - A VDD Analog input voltage Note 2 VIAN RAN When not sampling When sampling Reference voltage AVREF1 current AVDD supply current A/D converter data retention current AVREF AIREF AIDD AIDDDR Operating mode STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10 % 3.4 1.0 2.0 2 10 -0.3 10
Note 3
Symbol
Conditions
Min. 10
Typ.
Max.
Unit bit
0.4 0.7 1/2 208 169 8 6 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVREF + 0.3
%FSR %FSR LSB tCYK tCYK tCYK tCYK LSB LSB LSB LSB LSB LSB V MW
Analog input impedance
AVDD 3.0 6.0 10 50
V mA mA
mA mA
Notes 1. The quantization error is excluded. 2. When -0.3 V - VIAN - 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed with the 10-bit resolution. When AVREF - VIAN - AVREF + 0.3 V, the conversion result becomes 3FFH. 3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown below. (The values in the diagram are TYP. values; they are not guaranteed values.)
1 k Analog input pin 25 pF (Input capacitance included) 1.4 pF
29
mPD78P368A
Cautions 1. When using the P70/ANI0-P77/ANI7 pins for both digital and analog inputs, the previously described characteristics are not guaranteed. Therefore, ensure that all of the eight P70/ ANI0-P77/ANI7 pins are used either for analog input or digital input. 2. When using the P70/ANI0-P77/ANI7 pins as digital input, make sure to set that AVDD = VDD, and AVSS = VSS. AC Timing Test Point
VDD 0.8VDD or 2.2 V Test point 0.2VDD or 0.8 V 0V 0.2VDD or 0.8 V 0.8VDD or 2.2 V
30
mPD78P368A
Read Operation
tCYK (CLK)
A8 - A15 (output) tSAST AD0 - AD7 (input/output) Hi-Z tDAID
High-order address
High-order address
Low-order address (output) tWSTH
Hi-Z
Data (input)
Hi-Z
Low-order address (output)
Hi-Z
tHRID
ASTB (output) tHSTA tFRA RD (output) tDSTR tDRID tWRL tDRA
Write Operation
(CLK)
A8 - A15 (output) tSAST AD0 - AD7 (output) Low-order address (output) tWSTH ASTB (output) tHSTA WR (output) tDSTW
High-order address
High-order address
Undefined
Data (output) tHWOD
Low-order address (output)
tDWST
tDWOD tWWL
tSODW
31
mPD78P368A
Serial Operation
tCYSK tWSKL SCK tDSKTX SO tWSKH
SI tSRXSK tHSKRX
Up/Down Counter (Timer 4) Input Timing
tWTIUH
TIUD
tSTCU tHTCU tWTCUL TCUD tWTCUH
tWTIUL
tWCLUH
TCLRUD
tWCLUL
TIUD tS4TIU tH4TIU tS4TIU tH4TIU
TCUD
32
mPD78P368A
Interrupt Input Timing
tWNIH tWNIL
0.8VDD NMI 0.2VDD
tWInH
tWInL
0.8VDD INTPn 0.2VDD
Remark n = 0 - 4 Reset Input Timing
tWRSH tWRSL
0.8VDD RESET 0.2VDD
33
mPD78P368A
DC PROGRAMMING CHARACTERISTICS (TA = 25 5 C, VSS = 0 V)
Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VDDP supply voltage Symbol VIH SymbolNote 1 VIH Conditions Min. 2.4 Typ. Max. VDDP + 0.3 Unit V
VIL
VIL
-0.3
0.8 10
V
ILIP VOH
ILI VOH
0 - VI - VDDPNote 2 IOH = -400 mA IOL = 2.1 mA 2.4
mA
V
VOL
VOL
0.45 10
V
ILO
-
0 - VO - VDDP, OE = VIH
mA
VDDP
VCC
Program memory write mode Program memory read mode
6.25 4.5 12.2 VDD - 0.6
6.5 5.0 12.5 VDD
6.75 5.5 12.8 VDD + 0.6 50 50 50 100
V V V V mA mA mA
VPP supply voltage
VPP
VPP
Program memory write mode Program memory read mode
VDDP supply current
IDD
IDD
Program memory write mode Program memory read mode
VPP supply current
IPP
IPP
Program memory write mode Program memory read mode
mA
Notes 1. Symbols for the corresponding mPD27C1001A 2. The VDDP represents the VDD pin as viewed in the programming mode.
34
mPD78P368A
AC PROGRAMMING CHARACTERISTICS (TA = 25 5 C, VSS = 0 V) PROM Write Mode (Page Program Mode)
Parameter Address set up time CE set time Input data setup time Address hold time SymbolNote 1 tAS tCES tDS tAH tAHL tAHV Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE OE pulse width in the data latch PGM setup time CE hold time OE hold time tDH tDF tVPS tVDSNote 2 tPW tOES tOE tLW tPGMS tCEH tOEH 1 2 2 2 Conditions Min. 2 2 2 2 2 0 2 0 1 1 0.095 2 1.0 0.105 250 Typ. Max. Unit
ms ms ms ms ms ms ms
ns ms ms ms
ms ms ms ms ms ms
Notes 1. These symbols (except tVDS) correspond to those of the mPD27C1001A. 2. For mPD27C1001A, read tVDS as tVCS.
35
mPD78P368A
PROM Write Mode (Byte Program Mode)
Parameter Address set up time CE set time Input data setup time Address hold time Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time Valid data delay time from OE SymbolNote 1 tAS tCES tDS tAH tDH tDF tVPS tVDSNote 2 tPW tOES tOE Conditions Min. 2 2 2 2 2 0 1 1 0.095 2 1.0 0.105 250 Typ. Max. Unit
ms ms ms ms ms
ns ms ms ms
ms ms
Notes 1. These symbols (except tVDS) correspond to those of the mPD27C1001A. 2. For mPD27C1001A, read tVDS as tVCS. PROM Read Mode
Parameter Data output time from address CE O AE data output time OE O AE data output time Data hold time to OE * Data hold time to address Symbol Note tACC tCE tOE tDF tOH Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL 0 0 Min. Typ. Max. 1.0 1.0 1.0 250 Unit
ms ms ms
ns ns
Note These symbols correspond to those of the mPD27C1001A.
36
mPD78P368A
PROM Write Mode Timing (Page Program Mode)
Page data latch Page program Program verify
A2 - A16 tAS A0, A1 tDS D0 - D7 Hi-Z tVPS VPP VPP VDDP tVDS VDDP + 1.5 VDDP VDDP tCES VIH CE VIL VIH PGM VIL VIH OE VIL tLW tOES tPW tCEH tOEH Data input tDH Hi-Z tPGMS tOE Data output tDF Hi-Z tAHL tAHV
tAH
37
mPD78P368A
PROM Write Mode Timing (Byte Program Mode)
Program
Program verify
A0 - A16 tAS Hi-Z tDS VPP VPP VDDP VDDP + 1.5 VDDP VDDP tVDS VIH CE VIL tCES VIH PGM VIL VIH OE VIL tOES tOE tPW tVPS Hi-Z tDH tDF Data input Data output tAH Hi-Z
D0 - D7
Cautions 1. VDDP must be applied before VPP, and must be cut after VPP. 2. VPP including overshoot must not exceed +13.5 V. 3. Plugging in or out the board with the VPP pin supplied with +12.5 V may adversely affect its reliability. PROM Read Mode Timing
A0 - A16
Valid address
CE tCE OE tDFNote 2 tACCNote 1 D0 - D7 Hi-Z tOE
Note 1
tOH Data output Hi-Z
Notes 1. For reading within tACC, the delay of the OE input from falling edge of CE must be within tACC - tOE. 2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
38
mPD78P368A
9. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14 20)
A B
64 65
41 40
detail of lead end
CD
S Q R
80 1
25 24
F G H P I
M
J
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P80GF-80-3B9-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
39
mPD78P368A
80 PIN CERAMIC WQFN
A B Q
U1
T 80 1
D
C
K
W
H
I
M
Z
F
G
J
R
X80KW-80A1
NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K Q R S T U1 W Z
MILLIMETERS
INCHES
20.0 0.25 19.0 13.4 14.2 0.2 1.84 3.56MAX. 0.51 0.1 0.08 0.8 (T.P.) 1.00.15 C0.3 0.8 1.1
0.787+0.011 -0.010 0.748 0.528 0.559 0.008 0.072 0.141MAX. 0.02 0.004 0.003 0.031 (T.P.) + 0.007 0.039 - 0.006 C0.012 0.031 0.043
7.62
2.6 0.750.15 0.10
0.3
0.102 0.03+0.006 - 0.007 0.004
40
S
mPD78P368A
10. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device H
Mounting Technology Manual (C10535J).
For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 10-1. Surface Mount Type Soldering Conditions
mPD78P368AGF-3B9: 80-Pin Plastic QFP (14 20 mm)
Recommended condition symbol IR35-207-2
Soldering method Infrared reflow
Soldering conditions Package peak temperature: 235 C, Duration: 30 sec. max. (210 C or above) Number of times: 2 max. Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 C afterward) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking.
VPS
Package peak temperature: 215 C, Duration: 40 sec. max. (200 C or above) Number of times: 2 max. Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 C afterward) Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Solder bath temperature: 260 C or less, Time: 10 sec. max., Number of times: 1, Pre-heating temperature: 120 C max. (Package surface temperature) Exposure limit: 7 days Note (20 hours of pre-baking is required at 125 C afterward)
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
Pin temperature: 300 C or less Duration: 3 sec. max. (per side of device)
-
Note Maximum number of days during which the product can be stored at a temperature of 25 C and a relative humidity of 65 % or less after dry-pack package is opened. Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
41
mPD78P368A
APPENDIX A TOOLS
A.1 DEVELOPMENT TOOLS The following tools are provided for developing a system that uses the mPD78P368A: Language processor
78K/III series relocatable assembler (RA78K3)
This relocatable program can be used for all 78K/III series emulators. With its macro functions, it allows the user to improve program development efficiency. A structured-programming assembler is also provided, which enables explicit description of program control structures. This assembler could improve productivity in program production and maintenance. Host machine OS PC-9800 series MS-DOSTM Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/ATTM or compatibles HP9000 series 700 TM PC DOSTM 3.5-inch 2HC 5.25-inch 2HC HP-UXTM DAT Part number
mS5A13RA78K3 mS5A10RA78K3 mS7B13RA78K3 mS7B10RA78K3 mS3P16RA78K3 mS3K15RA78K3 mS3R15RA78K3
SPARCstationTM SunOSTM NEWS TM 78K/III series C compiler (CC78K3) NEWS-OSTM
Cartridge tape (QIC-24)
This C compiler can be used for all 78K/III series emulators. The compiler converts programs written in C language into object codes executable on the microcomputer. When the compiler is used, the 78K/III series relocatable assembler package (RA78K3) is needed. Host machine OS PC-9800 series MS-DOS Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles HP9000 series 700 SPARCstation NEWS PC DOS 3.5-inch 2HC 5.25-inch 2HC HP-UX DAT Part number
mS5A13CC78K3 mS5A10CC78K3 mS7B13CC78K3 mS7B10CC78K3 mS3P16CC78K3 mS3K15CC78K3 mS3R15CC78K3
SunOS NEWS-OS
Cartridge tape (QIC-24)
Remark It is guaranteed that the relocatable assembler and C compiler run only under the OSs on the corresponding host machines described above.
42
mPD78P368A
PROM programming tools
Hardware PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcomputer containing PROM independently or from a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. Programmer adapter for writing programs to the mPD78P368A. Used with a PROM programmer such as the PG-1500. PA-78P368GF : For mPD78P368AGF PA-78P368KL : For mPD78P368AKL This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine OS PC-9800 series MS-DOS Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC Part number
PA-78P368GF PA-78P368KL
Software
PG-1500 controller
mS5A13PG1500 mS5A10PG1500 mS7B13PG1500 mS7B10PG1500
Remark It is guaranteed that the PG-1500 controller runs only under the OSs on the corresponding host machines described above.
Debugging tools (when the IE controller is used)
Hardware IE-78350-R In-circuit emulator for developing and debugging an application system. For debugging, connect the emulator to the host machine. I/O emulation board for emulating peripheral hardware such as the I/O ports of the target device. Emulation probe for connecting the IE-78350-R to the target system. One EV-9200G-80 conversion socket is provided for connection to the target system. This control program allows the user to control the IE-78350-R from the host machine. Its automatic command execution function ensures more efficient debugging. Host machine OS PC-9800 series MS-DOS Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC Part number
IE-78365-R-EM1
EP-78365GF-R EV-9200G-80 Software IE-78350-R control program (IE controller)
mS5A13IE78365A mS5A10IE78365A mS7B13IE78365A mS7B10IE78365A
H H H H
Remark It is guaranteed that the IE controller runs only under the OSs on the corresponding host machines described above.
43
mPD78P368A
Configuration of development tools (when the IE controller is used)
Host machine: PC-9800 series IBM PC/AT EWS
RS-232-C
IE-78350-R in-circuit emulator + IE-78365-R-EM1 I/O emulation board (option) Software RS-232-C PROM programmer Relocatable assembler C compiler PG-1500 controller
Emulation probe
EP-78365GF-R + Socket for connecting the emulation probe and target systemNote
PG-1500 IE controller Device containing PROM
EV-9200G-80
PD78P368AGF
PD78P368AKL
+ Target system
+ Programmer adapter
PA-78P368GF
PA-78P368KL
Note The socket is supplied with the emulation probe. Remarks 1. The PG-1500 can be directly connected to the host machine via the RS-232-C interface. 2. In this figure, the distribution media of software is represented by the 3.5-inch floppy disk.
44
mPD78P368A
Debugging tools (when the integrated debugger is used)
Hardware IE-784000-R In-circuit emulator for developing and debugging an application system. For debugging, connect the emulator to the host machine. Emulation board for emulating peripheral hardware such as the I/O ports of the target device. I/O emulation board for emulating peripheral hardware such as the I/O ports of the target device. Emulation probe for connecting the IE-784000-R to the target system. One EV9200G-80 conversion socket is provided for connection to the target system. Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine. Interface adapter and cable when a PC-9800 series notebook is used as the host machine. Interface adapter when the IBM PC/AT is used as the host machine. Interface adapter and cable when the EWS is used as the host machine. Program for controlling the in-circuit emulator for the 78K/III series. The integrated debugger (ID78K3) is used together with the device file (DF78365). Debugging can be performed for the source program written in C, structured assembly language, or assembly language. The ID78K3 can display various information simultaneously on the host machine screen divided into multiple areas. This ensures efficient debugging. Host machine OS PC-9800 series MS-DOS + WindowsTM PC DOS + Windows Distribution media 3.5-inch 2HD 5.25-inch 2HD 3.5-inch 2HC 5.25-inch 2HC 3.5-inch 2HC 5.25-inch 2HC
IE-78350-R-EM-A Note
IE-78365-R-EM1
EP-78365GF-R EV-9200G-80 IE-70000-98-IF-B
IE-70000-98N-IF
IE-70000-PC-IF-B IE-78000-R-SV3 Software Integrated debugger (ID78K3)
Part number
mSAA13ID78K3 mSAA10ID78K3 mSAB13ID78K3 mSAB10ID78K3 mSBB13ID78K3 mSBB10ID78K3
IBM PC/AT or compatibles (Japanese Windows) IBM PC/AT or compatibles (Windows) Device file (DF78365)
File which contains the device-specific information. The device file (DF78365) is used together with the assembler (RA78K3), C compiler (CC78K3), or integrated debugger (ID78K3).
Host machine PC-9800 series
OS MS-DOS
Distribution media 3.5-inch 2HD 5.25-inch 2HD
Part number
mS5A13DF78365 mS5A10DF78365 mS7B13DF78365 mS7B10DF78365
IBM PC/AT or compatibles
PC DOS
3.5-inch 2HC 5.25-inch 2HC
Note Under development Remark It is guaranteed that the integrated debugger and device file run only under the OSs on the corresponding host machines described above.
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mPD78P368A
Configuration of development tools (when the integrated debugger is used)
Host machine: PC-9800 series IBM PC/AT EWS
IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B
Software RS-232-C
IE-784000-R in-circuit emulator + IE-78350-R-EM-A emulation board (option) + IE-78365-R-EM1 I/O emulation board (option)
Emulation probe
EP-78365GF-R Relocatable assembler C compiler PG-1500 controller PROM programmer PG-1500 Integrated debugger Device file EV-9200G-80 + Socket for connecting the emulation probe and target systemNote
Device containing PROM
PD78P368AGF
PD78P368AKL
+ Target system
+ Programmer adapter
PA-78P368GF
PA-78P368KL
Note The socket is supplied with the emulation probe. Remarks 1. In this figure, the host machine is represented by the desktop personal computer. 2. In this figure, the distribution media of software is represented by the 3.5-inch floppy disk.
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mPD78P368A
A.2 EMBEDDED SOFTWARE To improve the efficiency of program development and simplify the maintenance of systems incorporating this microcontroller, the following embedded software is provided. Real-time OS
Real-time OS (RX78K/III) Note This operating system was designed to provide a multitasking environment for control applications that require real-time processing. System performance is improved by using the idling CPU for other processing. RX78K/III provides system calls that conform to mITRON specifications. The RX78K/III package provides the RX78K/III nucleus and a tool (Configurator) that is used for creating multiple information tables. Host machine OS PC-9800 series MS-DOS Part number Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC Undecided Undecided Undecided Undecided
Note Under development Caution Before purchasing this software, complete the purchase application sheet and sign the software license agreement. Remark To use the RX78K/III real-time operating system, the optional RA78K3 assembler package is required.
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mPD78P368A
Fuzzy inference development support system
Tool for creating fuzzy knowledge data (FE9000, FE9200) This program supports the input/editing and simulation of fuzzy knowledge data (fuzzy rules and membership functions). Host machine OS PC-9800 series MS-DOS Part number Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles Translator (FT78K3) Note PC DOS
mS5A13FE9000 mS5A10FE9000 mS7B13FE9200 mS7B10FE9200
+
3.5-inch 2HC 5.25-inch 2HC
Windows
This program converts fuzzy knowledge data, obtained using the tool for creating fuzzy knowledge data, into an assembler source program for RA78K3. Host machine OS PC-9800 series MS-DOS Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC Part number
mS5A13FT78K3 mS5A10FT78K3 mS7B13FT78K3 mS7B10FT78K3
Fuzzy inference module (FI78K/III)Note
This program performs fuzzy inference by linking the fuzzy knowledge data converted by Translator. Host machine OS PC-9800 series MS-DOS Part number Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC
mS5A13FI78K3 mS5A10FI78K3 mS7B13FI78K3 mS7B10FI78K3
Fuzzy inference debugger (FD78K/III)
This software supports the evaluation and adjustment of fuzzy knowledge data at the hardware level, by using an in-circuit emulator. Host machine OS PC-9800 series MS-DOS Distribution media 3.5-inch 2HD 5.25-inch 2HD IBM PC/AT or compatibles PC DOS 3.5-inch 2HC 5.25-inch 2HC Part number
mS5A13FD78K3 mS5A10FD78K3 mS7B13FD78K3 mS7B10FD78K3
Note Under development
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mPD78P368A
APPENDIX B DIMENSIONS OF THE CONVERSION SOCKET AND RECOMMENDED PATTERN ON BOARDS
Fig. B-1 Dimensions of the Conversion Socket (EV-9200G-80)(Reference)
Based on EV-9200G-80 (1) Package drawing (in mm)
A B G
F
N
S
T D C E U
R
EV-9200G-80-G0 INCHES 0.984 0.799 0.157 0.569 0.748 4-C 0.11 0.031 0.433 0.866 0.972 0.197 0.638 0.744 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005
O
P
EV-9200G-80
1 No.1 pin index Q
H I J ITEM A B C D E F G H I J K L M O N P Q R S T U MILLIMETERS 25.0 20.30 4.0 14.45 19.0 4-C 2.8 0.8 11.0 22.0 24.7 5.0 16.2 18.9 8.0 7.8 2.5 2.0 1.35 0.35 0.1
2.3 1.5
0.091 0.059
M
K
L
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mPD78P368A
Fig. B-2 Recommended Pattern on Boards for the Conversion Socket (EV-9200G-80)(Reference)
Based on EV-9200G-80 (2) Pad drawing (in mm)
G H
L
D
E
F
J M K C B A EV-9200G-80-P0 INCHES 1.012 0.827 0.031+0.002 -0.001 x 0.906=0.724 +0.003 -0.002 0.598 0.783 0.433+0.004 -0.003 0.217+0.001 -0.002 0.197+0.003 -0.004 0.098+0.002 -0.001 0.02+0.001 -0.002
ITEM A B C D E F G H I J K L M Caution
MILLIMETERS 25.7 21.0 0.80.02 x 23=18.40.05
0.80.02 x 15=12.00.05 0.031+0.002 x 0.591=0.472 +0.003 -0.001 -0.002 15.2 19.9 11.00 0.08 5.50 0.03 5.00 0.08 2.50 0.03 0.5 0.02
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207).
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I
mPD78P368A
Cautions on CMOS Devices
Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. TRON stands for The Realtime Operating system Nucleus. ITRON stands for Industrial TRON.
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mPD78P368A
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed The customer must judge the need for license
: mPD78P368AKL-S : mPD78P368AGF-3B9
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94. 11
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