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CDP1878C
March 1997
CMOS Dual Counter-Timer
Description
The CDP1878C is a dual counter-timer consisting of two 16bit programmable down counters that are independently controlled by separate control registers. The value in the registers determine the mode of operation and control functions. Counters and registers are directly addressable in memory space by any general industry type microprocessors, in addition to input/output mapping with the CDP1800 series microprocessors. Each counter-timer can be configured in five modes with the additional flexibility of gate-level control. The control registers in addition to mode formatting, allow software start and stop, interrupt enable, and an optional read control that allows a stable readout from the counters. Each countertimer has software control of a common interrupt output with an interrupt status register indicating which counter-timer has timed out. In addition to the interrupt output, true and complemented outputs are provided for each counter-timer for control of peripheral devices. This type is supplied in 28-lead dual-in-line ceramic packages (D suffix), and 28-lead dual-in-line plastic packages (E suffix).
Features
* Compatible with General Purpose and CDP1800 Series Microprocessor Systems * Two 16-Bit Down Counters and Two 8-Bit Control Registers * 5 Modes Including a Versatile Variable-Duty Cycle Mode * Programmable Gate-Level Select * Two-Complemented Output Pins for Each CounterTimer * Software-Controlled Interrupt Output * Addressable in Memory Space or CDP1800-Series I/O Space
Ordering Information
PART NUMBER CDP1878CE CDP1878CD TEMP. RANGE PACKAGE PKG. NO. E28.6 N28.6
-40oC to +85oC PDIP -40oC to +85oC SBDIP
Pinout
CDP1878C (DIP) TOP VIEW MODE
INT 1 TAO 2 TAO 3 TAG 4 TACL 5 RD 6 IO/MEM 7 28 VDD 27 DB7 26 DB6 25 DB5 24 DB4 23 DB3 22 DB2 21 DB1 20 DB0 19 TBO 18 TBO 17 TBG 16 TBCL 15 RESET
TABLE 1. MODE DESCRIPTION FUNCTION Outputs change when clock decrements counter to "0" One clockwide output pulse when clock decrements counter to "0" Outputs change when clock decrements counter to "0". Retriggerable APPLICATION Event counter
1 Timeout
2 Timeout Strobe
Trigger pulse
TPB/WR 8 TPA 9 CS 10 A0 11 A1 12 A2 13 VSS 14
3 Gate-Controlled One Shot
Time-delay generation
4 Rate Generator Repetitive clockwide output pulse 5 Variable-Duty Cycle Repetitive output with programmed duty cycle
Time-base generator Motor control
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1341.2
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CDP1878C
Absolute Maximum Ratings
DC Supply-Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1878C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 50 12 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time Minimum Clock Pulse Width Maximum Clock Input Frequency
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: SYMBOL MIN 4 VSS tR, tF tWL, tWH fCL 200 DC MAX 6.5 VDD 5 1 UNITS V V s ns MHz
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5% Except as noted: CONDITIONS VO (V) 0.4 4.6 0.5, 4.5 0.5, 9.5 Any Input VIN (V) 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 VDD (V) 5 5 5 5 5 5 5 5 5 LIMITS (NOTE 1) TYP 0.02 3.2 -2.3 0 5 1.5 5 10
PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 2) Output Voltage High-Level (Note 2) Input Low Voltage Input High Voltage Input Leakage Current Operating Current (Note 3) Input Capacitance Output Capacitance NOTES:
SYMBOL IDD IOL IOH VOL VOH VIL VIH IIN IDD1 CIN COUT
MIN 1.6 -1.15 4.9 3.5 -
MAX 200 0.1 1.5 1 3 7.5 15
UNITS A mA mA V V V V A mA pF pF
1. Typical values are for TA = +25oC and nominal VDD. 2. IOL = IOH = 1A 3. Operating current measured at 200kHz for VDD = 5V, with open outputs (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2MHz).
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CDP1878C Functional Diagram
JAM REGISTER A RESET RD TPB/WR IO/MEM TPA CS A2 A1 A0 VDD VSS 8-BIT EXTERNAL BUS DATA BUS DRIVERS INT AND STATUS REGISTER JAM REGISTER B GATE B COUNTER B CONTROL REGISTER B AND MODE CONTROL TBO TBO CLOCK B HOLDING REGISTER B INT GATE A I-O CONTROL AND LOGIC COUNTER A CONTROL REGISTER A AND MODE CONTROL TAO TAO CLOCK A HOLDING REGISTER A
FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS TERMINAL VDD - VSS DB0-DB7 TPB/WR, RD A0, A1, A2 TACL, TBCL TAG, TBG Power Data to and from device Directional Control Signals Addresses that select counters or registers Clocks used to decrement counters Gate inputs that control counters USAGE TERMINAL TAO, TAO TBO, TBO TPA CS INT RESET IO/MEM USAGE Complemented outputs of Timer A Complemented outputs of Timer B Used with CDP1800-series processors, tied high otherwise Active high input that enables device Low when counter is "0" When active, TAO, TBO are low, TAO, TBO are high. Interrupt status register is cleared. Tied high in CDP1800 input/output mode, otherwise tied low
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CDP1878C
REGISTER TRUTH TABLE ADDRESS A2 1 1 0 0 1 1 1 0 0 1 1 1 0 0 A1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 A0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 X X X Not Used Not Used X X X X X X X ACTIVE TPB/WR X X RD REGISTER COUNTER Write Counter A MSB Read Counter A MSB Write Counter A LSB Read Counter A LSB Control Register A Write Counter B MSB Read Counter B MSB Write Counter B LSB Read Counter B LSB Control Register B Interrupt Status Register
Programming Model
BUS 7 BUS 0 BUS 7 BUS 0
CONTROL REGISTER WRITE ONLY
CONTROL REGISTER WRITE ONLY
HOLDING REGISTER LSB READ ONLY HOLDING REGISTER MSB
JAM REGISTER LSB WRITE ONLY JAM REGISTER MSB
HOLDING REGISTER LSB READ ONLY HOLDING REGISTER MSB
JAM REGISTER LSB WRITE ONLY JAM REGISTER MSB
COUNTER A REGISTERS
COUNTER B REGISTERS
BUS 7 X X 0 0 0 0
BUS 0 0 0
READ ONLY TIMER A TIMER B
INTERRUPT STATUS REGISTER
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CDP1878C Functional DescriptIon
The dual counter-timer consists of two programmable 16-bit down counters, separately addressable and controlled by two independent 8-bit control registers. The word in the control register determines the mode and type of operation that the counter-timer performs. Writing to or reading from a counter or register is enabled by selective addressing during a write or read cycle. The data is placed on the data bus by the microprocessor during the write cycle or read from the counter during the read cycle. Data to and from the counters and to the control registers is in binary format. Each counter-timer consists of three parts. The first is the counter itself, a 16-bit down counter that is decremented on the trailing edge of the clock input. The second is the jam register that receives the data when the counter is written to. The word in the control register determines when the jam register value is placed into the counter. The third part is the holding register that places the counter value on the data bus when the counter is read. When the counter has decremented to zero, three events occur. The first involves the common interrupt output pin that, if enabled, becomes active low. The second is the setting of a bit in the interrupt status register. This register can be read to determine which counter-timer has timed out. The third event is the logic change of the complemented output pins. In addition to the clock input used to decrement the counter, a gate input is available to enable or initiate operation. The counter-timers are independent and can have different mode operations. Write Operation The counters and registers are separately addressable and are programmed via the data bus when the chip is selected with the TPB/WR pin active. Normal sequencing requires that the counter jam register be loaded first with the required value Control Register
7 JAM ENABLE 1 = ENABLE 0 = DISABLE HOLDING REGISTER CONTROL 1 = FREEZE HOLDING REGISTER 0 = UPDATE CONTINUOUSLY START/STOP CONTROL 1 = START COUNTER 0 = STOP COUNTER 6 5 4 3 2 1 0
(most significant and least significant byte in any order), and then the control register be accessed and loaded with the control word. The trailing edge of the TPB/WR pulse will latch the control word into the control register. The trailing edge of the first clock to occur with gate valid will cause the counter to be jammed with its initial value. The counter will decrement on the trailing edge of succeeding clocks as long as the gate is valid, until it reaches zero. The output levels will then change, and if enabled, the interrupt output will become active and the appropriate timer bit will be set in the interrupt status register. The interrupt output and the interrupt status register can be cleared (to their inactive state) by addressing the control register with the TPB/WR line active For example, if counter A times out, control register A must be accessed to reset the interrupt output high and reset the timer A bit in the status register low. Timer B bit in the status register will be unaffected. Read Operation Each counter has a holding register that is continuously being updated by the counter and is accessed when the counter is addressed during read cycles. Counter reads are accomplished by halting the holding register and then reading it, or by reading the holding register directly. If the holding register is read directly, data will appear on the bus if the counters are addressed with the RD line active. However, if the clock decrements the counter between the two read operations (most and least significant byte), an inaccurate value will be read. To preclude this from happening, writing a "1" into bit 6 of the control register and then addressing and reading the counter will result in a stable reading. This operation prevents the holding register from being updated by the counter and does not affect the counter's operation. The interrupt status register is read by addressing either control register with the RD line active. A "1" in bit 7 indicates Timer A has timed out and a "1" in bit 6 indicates Timer B has timed out. Bits 0-5 are zeros.
GATE LEVEL SELECT 1 = POSITIVE (HIGH) 0 = NEGATIVE (LOW) INTERRUPT ENABLE 1 = ENABLE 0 = DISABLE
MODE SELECT 001 = MODE 1 010 = MODE 2 011 = MODE 3 100 = MODE 4 101 = MODE 5 PLUS BIT 7 = 0
Bits 0, 1 and 2 Mode Selects - See Mode Timing Diagrams (Figures 1, 2, 3, 4, and 5). Note: When selecting a mode, the timer outputs TAO and TBO are set low, and TAO and TBO are set high. If bits 0, 1 and 2 are all zero's when the control register is loaded, no mode is selected, and the counter-timer outputs are unaffected. Issuing mode 6 will cause an indeterminate condition of the counter, issuing mode 7 is equivalent to issuing mode 5.
Mode 1 - Timeout Mode 2 - Timeout Strobe Mode 3 - Gate Controlled One Shot Mode 4 - Rate Generator Mode 5 - Variable-Duty Cycle No Mode selected. Counter outputs unaffected
BIT 7 BIT 2 BIT 1 BIT 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0
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CDP1878C
Bit 3 - Gate Level Select - All modes require an enabling signal on the gate to allow counter operation. This enabling signal is either a level or a pulse (edge). Positive gate level or edge enabling is selected by writing a "1" into this bit and negative (low) enabling is selected when bit 3 is "0". Bit 4 - Interrupt Enable - Setting this bit to "1" enables the INT output, and setting it to "0" disables it. When reset, the INT output is at a high level. If the interrupt enable bit in the control register is enabled and the counter decrements to zero, the INT output will go low and will not return high until the counter-timer is reset or the selected control register is written to. Example: If timer B times out, control register B must be accessed to reset the INT output high. If the interrupt enable bit is set to "0", the counter's timeout will have no effect on the lNT output. In mode 5, the variable-duty cycle mode, the lNT pin will become active low when the MSB in the counter has decremented to zero. Bit 5 - Start/Stop Control - This bit controls the clock input to the counter and must be set to "1" to enable it. Writing a "0" into this location will halt operation of the counter. Operation will not resume until the bit is set to "1". Bit 6 - Holding Register Control - Since the counter may be decrementing during a read cycle, writing a "1" into this location will hold a stable value in the hold register for subsequent read operations. Rewriting a "1" into bit 6 will cause an update in the holding register on the next trailing clock edge. If this location contains a "0", the holding register will be updated continuously by the value in the counter. Bit 7 - Jam Enable - When this bit is set to "1 "during a write to the control register, the 16-bit value in the jam register will be available to the counter; TAO and TBO are reset low and TAO and TBO are set high. On the trailing edge of the first input clock signal with the gate valid this value will be latched in the counter, the counter outputs TAO and TBO will be set high and the TAO and TBO will be reset low. Setting bit 7 to "0" will leave the counter value unaffected. This location should be set to "0" any time a write to the control register must be performed without changing the present counter value. If the value in the jam register has not been changed, writing a "1" into bit 7 of the control register with zeros in bits 0,1, and 2 (mode select) will reload the counter with the old value and leave the mode unchanged. If the value in the jam register is changed, then the next write to the control register (with bit 7 a "1") must include a valid mode select (i.e., at least 1 of the bits 0,1, or 2 must be a "1"). In mode 3, the hardware start is enabled by writing a "0" into bit 7. If a "1" is written to bit 7, the timeout will start immediately and mode 3 will resemble mode 1.
Mode Descriptions
MODE CONTROL REGISTER GATE CONTROL Selectable High or Low Level Enables Operation
1
Timeout XXXXX001 BUS 7 BUS 0
Mode 1 After the count is loaded into the jam register and the control register is written to with the jam-enable bit high on the trailing edge of the first clock after the gate is valid, TXO goes high and TXO goes low. The input clock decrements the counter as long as the gate remains valid. When it reaches zero TXO goes low and TXO goes high, and if enabled, the
COUNTER VALUE CLOCK 5 WR CONTROL REGISTER 4 3 2 1 1 0 FFFF 5 4
interrupt output is set low. Writing to the counter while it is decrementing has no effect on the counter value unless the control register is subsequently written to with the jamenable bit high. After timeout the counter remains at FFFF unless reloaded.
3
2
1
1
0
STALL COUNTER
GATE
TXO
INT
LOAD COUNT = 5
FIGURE 1. TIMEOUT (MODE 1) TIMING WAVEFORMS
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CDP1878C
MODE CONTROL REGISTER GATE CONTROL Selectable High or Low Level Enables Operation
2
Timeout Strobe XXXXX010 BUS 7 BUS 0
Mode 2 Operation of this mode is the same as mode 1, except the outputs will change for one clock period only and then return
COUNTER VALUE CLOCK 3 WR CONTROL REGISTER 2 1 0 3 SEE NOTE 3 2 1 0 3 2 1 0
to the condition of TXO high and TXO low, and the counter is reloaded
3 3 2 1
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 2. TIMEOUT STROBE (MODE 2) TIMING WAVEFORMS NOTE: Write to control register with mode selects = 0
MODE
CONTROL REGISTER
GATE CONTROL Selectable Positive or Negative Going Edge Initiates Operation
3
Gate Controlled One-Shot 0XXXX011 BUS 7 BUS 0
Mode 3 After the jam register is loaded with the required value, the gate edge will initiate this mode. TXO will be set high, and TXO will be set low. The clock will decrement the counter. When zero is reached, TXO will go low and TXO will be high, and the interrupt output will be set low. The counter is retrigCOUNTER VALUE CLOCK 3 WR CONTROL REGISTER GATE 2 1 0 3 3 2 1 3
gerable: While the counter is decrementing, a gate edge or write to the control register with the jam-enable bit high, will load the counter with the jam register value and restart the one-shot operation.
2
1
0
3
3
2
TXO
INT
LOAD COUNT = 3
FIGURE 3. GATE CONTROLLED ONE-SHOT (MODE 3) TIMING WAVEFORMS
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CDP1878C
MODE CONTROL REGISTER GATE CONTROL Selectable High or Low Level Enables Operation
4
Rate Generator XXXXX100 BUS 7 BUS 0
Mode 4 A repetitive clock-wide output pulse will be output, with the time between pulses equal to the counter's value, (trailing edge to leading edge). This model is software started with a write to the control register if the gate level is valid. If the counter is written to while decrementing, the new value will
COUNTER VALUE CLOCK 3 WR CONTROL REGISTER GATE 2 1 0 3 2 1 0 3 N 3 2
not affect the counter's operation until the present timeout has concluded, unless the control register is written to with the jam-enable bit high. If the gate input (TAG or TBG) is used to start this mode, the first cycle following the gate going true is indeterminate.
1 0 3 2 1 0 3 N
TXO
INT
LOAD COUNT = 3
FIGURE 4. RATE GENERATORS (MODE 4) TIMING WAVEFORMS
MODE
CONTROL REGISTER
GATE CONTROL Selectable High or Low Level Enables Operation
5
Variable Duty Cycle XXXXX101 BUS 7 BUS 0
Mode 5 After the mode is initiated, the outputs will remain at one level until the clock decrements the least significant byte of the counter to N+1. The outputs will then change level and the counter decrements the most significant byte to N+1. The process will then repeat, resulting in a repetitive output
COUNTER VALUE CLOCK 2 WR CONTROL REGISTER GATE 1 0 1 0 2 1 0 1 2 1
with a duty cycle directly controlled by the value in the counter. The output period will be equal to LSB+MSB+2. The interrupt output will become active after the MSB is loaded into the counter and decrements to zero.
0 1 0 2 1 0 1
TXO
LSB
MSB
LSB
INT
LOAD COUNT LSB = 2 AND MSB = 1
FIGURE 5. VARIABLE-DUTY CYCLE (MODE 5) TIMING WAVEFORMS NOTE: In order to avoid unwanted starts when selecting mode 3 or 4, the gate signal must be set to the opposite level that will be programmed.
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CDP1878C
Setting the Control Register The following will illustrate a counter write and subsequent reads that places stable, accurate values on the data bus from the counter-timer. The counter is addressed and the required values are loaded with a write operation. The control register is addressed next and loaded with B9H.
Function Pin Description
DB7 - DB0 - 8-bit bidirectional bus used to transfer binary information between the microprocessor and the dual counter-timer. VDD , VSS - Power and ground for device. A0, A1, and A2 - Addresses used to select counters or registers. TPB/WR, RD - Directional signals that determine whether data will be placed on the bus from a counter or the interrupt status register (RD active) (memory mapped), or data on the bus will be placed into a counter or control register (TPB/WR active). The following connections are required between the microprocessor and the counter-timer in the CDP1800series input/output mapping mode.
MICROPROCESSOR COUNTER-TIMER MRD RD TPB TPB/WR TPA TPA N Lines Address Lines and IO/MEM to VDD
BUS 7 1 0 1 1 1 0
BUS 0 0 1 CONTROL REGISTER = B9H MODE 1 SELECTED
LOAD COUNTER WITH JAM REGISTER
POSITIVE GATE ENABLING REQUIRED INTERRUPT OUTPUT ENABLED
HOLDING REGISTER CONTINUOUSLY UPDATED BY COUNTER
COUNTER START
FIGURE 6.
The counter will now decrement with each input clock pulse while the gate is valid. Assuming the counter has not decremented to zero and its value is to be read without affecting the counter's operation, a write to the control register is performed. 78H is loaded into the control register.
During an output instruction, data from the memory is strobed into the counter-timer during TPB when RD is active, and latched on TPB's trailing edge. Data is read from the counter-timer when RD is not active between the trailing edges of TPA and TPB. See Figures 11, 12, and 13. TACL, TBCL - Clocks used to decrement the counter. TAG, TBG - Gate inputs used to control counter. TAO, TAO - Complemented outputs of Timer A.
BUS 7 0 1 1 1 1 0
BUS 0 0 0 CONTROL REGISTER = 78H
TBO, TBO - Complemented outputs of Timer B. INT - Common interrupt output. Active when counter decrements to zero. RESET - Active low signal that resets counter outputs (TAO, TBO low, TAO, TBO high). The interrupt output is set high and the status register is cleared. IO/MEM - Tied high in CDP1800-series input/output mode, otherwise tied low.
COUNTER VALUE UNAFFECTED
UNCHANGED
COUNTER OUTPUTS UNAFFECTED
FREEZE HOLDING REGISTER
FIGURE 7.
The counter is addressed and read operations are performed.
TPA - Tied to TPA of the CDP1800-series microprocessors. During memory mapping, it is used to latch the high order address bit for the chip select. In the CDP1800 input/output mode, it is used to gate the N lines. When the counter-timer is used with other microprocessors, or when the high order address of the CDP1800-series microprocessors is externally latched, it is connected to VDD . CS - An active high signal that enables the device.
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CDP1878C
CLOCK XTAL CLEAR MWR MRD TPA MAO MA1 ADDRESS LINES MA2 MA7 VSS INT MEMORY CDP1802
TACL, TBCL RESET TPB/WR RD TPA A0 A1 A2 CS IO/MEM INT COUNTER - TIMER DB0 - DB7
TAG GATE INPUTS TBG TAO TAO TIMER OUTPUTS TBO TBO
DATA BUS
FIGURE 8. TYPICAL CDP1802 MEMORY-MAPPED SYSTEM
TPA
LATCH HIGH-ORDER ADDRESS FOR CS
ADDRESS
HIGH BYTE
LOW BYTE
TPB/WR
DATA LATCHED
DATA FROM CPU TO COUNTER-TIMER
VALID DATA
FIGURE 9. CDP1800-SERIES MEMORY-MAPPING WRITE CYCLE TIMING WAVEFORMS
TPA
ADDRESS
HIGH BYTE
LOW BYTE OUTPUT DRIVERS
RD DATA FROM COUNTER-TIMER TO CPU
ENABLED
DISABLED
VALID DATA
FIGURE 10. CDP1800-SERIES MEMORY-MAPPING READ CYCLE TIMING WAVEFORMS
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CDP1878C
CLOCK XTAL CLEAR TPA MRD TPB N0 N1 ADDRESS LINES N2 VDD INT MEMORY CDP1802
TACL, TBCL RESET TPA RD TPB/WR A0 A1 A2 CS IO/MEM INT COUNTER - TIMER DB0 - DB7
TAG GATE INPUTS TBG TAO TAO TIMER OUTPUTS TBO TBO
DATA BUS
FIGURE 11. TYPICAL CDP1802 INPUT/OUTPUT-MAPPED SYSTEM
TPA
RD
N LINES
TPB/WR
DATA LATCHED
DATA FROM MEMORY TO COUNTER-TIMER
VALID DATA
FIGURE 12. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION
TPA
OUTPUT DRIVERS ENABLED
RD OUTPUT DRIVERS DISABLED
TPB/WR
N LINES DATA FROM COUNTER-TIMER TO MEMORY
VALID DATA
FIGURE 13. CDP1800-SERIES INPUT/OUTPUT-MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION
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Dynamic Electrical Specifications
PARAMETER READ CYCLE TIMES (See Figure 14) Data Access from Address Read Pulse Width Data Access from Read Address Hold after Read Output Hold after Read Chip Select Setup to TPA NOTES: 1. Time required be a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. tDA tRD tDR tRH tDH tCS 400 0 50 50 350 250 ns ns ns ns ns ns at TA = -40 to +85oC, VDD = 5V 5%, Input tR, tF = 10ns, CL = 50pF and 1 TTL Load (NOTE 1) MIN (NOTE 2) TYP MAX UNITS
SYMBOL
TPA tCS tRH
ADDRESS/CHIP SELECT
tRD READ
DATA TO CPU
tDR tDA tDH
FIGURE 14. READ CYCLE TIMING WAVEFORMS
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CDP1878C
Dynamic Electrical Specifications
PARAMETER WRITE CYCLE TIMES (See Figure 15) Address Setup to Write Write Pulse Width Data Setup to Write Address Hold after Write Data Hold after Write Chip Select Setup to TPA NOTES: 1. Time required by a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. tAS tWR tDS tAH tWH tCS 150 150 200 50 50 50 ns ns ns ns ns ns at TA = -40 to +85oC, VDD = 5V 5%, Input tR, tF = 10ns, CL = 50pF and 1 TTL Load (NOTE 1) MIN (NOTE 2) TYP MAX UNITS
SYMBOL
TPA tCS tAH
ADDRESS/CHIP SELECT
tAS WRITE
tWR
DATA TO COUNTER-TIMER
tDS
tWH
FIGURE 15. WRITE CYCLE TIMING WAVEFORMS
C
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