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PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD178P018A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD178P018ANote is a device in which the internal mask ROM of the PD178018A is replaced with a onetime PROM or EPROM. Because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multipledevice production, and early development and time-to-market. The PD178P018A is a PROM version corresponding to the PD178004A, 178006A, and 178016A. Note Caution Under development The PD178P018AKK-T does not maintain planned reliability when used in your system's massproduced products. Please use only experimentally or for evaluation purposes during trial manufacture. For more information on functions, refer to the following User's Manuals. Be sure to read them when designing. PD178018A Subseries User's Manual: To be prepared 78K/0 Series User's Manual Instruction: U12326E FEATURES * Pin-compatible with mask ROM version (except for VPP pin) * Internal PROM: 60 Kbytes * PD178P018AGC : One-time programmable (ideally suited for small-lot production) * PD178P018AKK-T : Reprogrammable (ideally suited for system evaluation) * Internal high-speed RAM: 1 024 bytes * Internal expansion RAM: 2 048 bytes * Buffer RAM: 32 bytes * Can be operated in the same power supply voltage as the mask ROM version (During PLL operation: VDD = 4.5 to 5.5 V) The electrical specifications (power supply current, etc.) and PLL analog specifications of the PD178P018A differ from that of mask ROM versions. So, these differences should be considered and verified before application sets are mass-produced. In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions. The information in this document is subject to change without notice. Document No. U12642EJ1V0DS00 (1st Edition) Date Published July 1997 N Printed in Japan (c) 1997 PD178P018A APPLICATIONS Car stereo, home stereo systems ORDERING INFORMATION Part Number Package 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin ceramic WQFN (14 x 14 mm, 0.65-mm pitch) Internal ROM One-Time PROM EPROM Quality Grade Standard Not applicable PD178P018AGC-3B9 Note PD178P018AKK-T Note Note Under planning Please refer to the Quality grade on NEC Semiconductor Devices (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. PD178018A SUBSERIES AND PD178003 SUBSERIES EXPANSION 80 pins PD178P018A Note PROM : 60 KB RAM : 3 KB 80 pins PD178018A ROM : 60 KB RAM : 3 KB PD178018A Subseries 80 pins PD178016A ROM : 48 KB RAM : 3 KB 80 pins PD178006A ROM : 48 KB RAM : 1 KB 80 pins PD178004A ROM : 32 KB RAM : 1 KB 80 pins PD178003 Note ROM : 24 KB RAM : 0.5 KB PD178003 Subseries 80 pins PD178002 Note ROM : 16 KB RAM : 0.5 KB Note Under development 2 PD178P018A FUNCTION DESCRIPTION (1/2) Item Internal memory * PROM * RAM High-speed RAM Expansion RAM Buffer RAM General register Instruction cycle Instruction set : 1 024 bytes : 2 048 bytes : 32 bytes : 60 Kbytes Function 8 bits x 32 registers (8 bits x 8 registers x 4 banks) With variable instruction execution time function 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (with 4.5-MHz crystal resonator) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulate (set, reset, test, Boolean operation) BCD Adjust, etc. 62 1 54 4 3 pins pin pins pins pins I/O port Total : * CMOS input : * CMOS I/O : * N-ch open-drain I/O : * N-ch open-drain output : A/D converter Serial interface 8-bit resolution x 6 channels * 3-wire/SBI/2-wire/I2 C bus Note mode selectable : 1 channel * 3-wire serial I/O mode (with automatic transmit/receive function of up to 32 bytes) : 1 channel * * * * Basic timer (timer carry FF (10 Hz)) : 8-bit timer/event counter : 8-bit timer (D/A converter: PWM output) : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Buzzer (BEEP) output Vectored interrupt source Test input Maskable Non-maskable Software 1.5 kHz, 3 kHz, 6 kHz Internal: 8, external: 7 Internal: 1 Internal: 1 Internal: 1 Note When using the I2 C bus mode (including when this mode is implemented by program without using the peripheral hardware), consult your local NEC sales representative when you place an order for mask. 3 PD178P018A (2/2) Item PLL frequency synthesizer Division mode Function Two types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOH and VCOL pins) 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Error out output: 2 (EO0 and EO1 pins Note 1) Unlock detectable by program * Frequency measurement * AMIFC pin: for 450-kHz count * FMIFC pin: for 450-kHz/10.7-MHz count 8-/9-bit resolution x 3 channels (shared by 8-bit timer) * HALT mode * STOP mode * Reset via the RESET pin * Internal reset by watchdog timer * Reset by power-ON clear circuit (3-value detection) * Detection of less than 4.5 V Note 2 (CPU clock: fX) * Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application) * Detection of less than 2.5 V Note 2 (in STOP mode) * VDD = 4.5 to 5.5 V (with PLL operating) * VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less) * VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX) * 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) * 80-pin ceramic WQFN (14 x 14 mm, 0.65-mm pitch) Reference frequency Charge pump Phase comparator Frequency counter D/A converter (PWM output) Standby function Reset Power supply voltage Package Notes 1. The EO1 pin can be set to high impedance for the PD178P018A. The following figure shows an application example. PD178P018A EO0 EO1 VCOH VCOL LPF VCO To Mixer LPF : Low path filter VCO : Voltage controlled oscillator * To lock to a target frequency at high speed Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF voltage control potential. * Normal state Setting only the EO0 pin to error out output maintains the LPF stable. 2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these values. 4 PD178P018A PIN CONFIGURATIONS (TOP VIEW) (1) Normal operating mode * 80-PIN PLASTIC QFP (14 x 14 mm, 0.65-mm pitch) PD178P018AGC-3B9 Note * 80-PIN CERAMIC WQFN (14 x 14 mm, 0.65-mm pitch) PD178P018AKK-T Note P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 REGOSC REGCPU RESET P125 P124 P123 P122 P121 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P132/PWM0 P133/PWM1 P134/PWM2 P40 P41 P42 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P120 GND VDD X1 X2 P37 P36/BEEP P35 P34/TI2 P33/TI1 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 GNDPORT VDDPORT P43 P44 P45 P46 P47 AMIFC FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 P50 P51 P52 Note Under development Connect Connect Connect Connect the VPP pin to GND directly. the VDDPORT and VDDPLL pins to VDD. the GNDPORT and GNDPLL pins to GND. each of the REGOSC and REGCPU pins to GND via a 0.1-F capacitor. Cautions 1. 2. 3. 4. P53 VPP 5 PD178P018A AMIFC ANI0 to ANI5 BEEP BUSY EO0, EO1 FMIFC GND GNDPLL GNDPORT INTP0 to INTP6 P00 to P06 P10 to P15 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P120 to P125 P132 to P134 : : : : : : : : : : : : : : : : : : : AM Intermediate Frequency Counter Input A/D Converter Input Buzzer Output Busy Output Error Out Output FM Intermediate Frequency Counter Input Ground PLL Ground Port Ground Interrupt Inputs Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 Port 13 PWM0 to PWM2 REGCPU REGOSC RESET SB0, SB1 SCK0, SCK1 SCL SDA0, SDA1 SI0, SI1 SO0, SO1 STB TI1, TI2 VCOL, VCOH VDD VDDPLL VDDPORT VPP X1, X2 : : : : : : : : : : : : : : : : : : PWM Output Regulator for CPU Power Supply Regulator for Oscillator Reset Input Serial Data Bus Input/Output Serial Clock Input/Output Serial Clock Input/Output Serial Data Input/Output Serial Data Input Serial Data Output Strobe Output Timer Clock Input Local Oscillation Input Power Supply PLL Power Supply Port Power Supply Programming Power Supply Crystal Resonator Connection 6 PD178P018A (2) PROM programming mode * 80-PIN PLASTIC QFP (14 x 14 mm) PD178P018AGC-3B9 Note * 80-PIN CERAMIC WQFN PD178P018AKK-T Note RESET VDD VDD (L) Open GND VDD PGM (L) A9 (L) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 D7 D6 D5 D4 D3 D2 D1 D0 (L) CE OE (L) A15 A14 A13 A12 (L) Open A0 A1 A2 GND VDD A3 A4 A5 A6 A7 GND (L) (L) Note Under planning (L) : GND : RESET : Open : Individually connect to GND via a pull-down resistor. Connect to GND. Set to the low level. Leave open. Cautions 1. 2. 3. 4. A0 to A16 CE D0 to D7 : Address Bus : Chip Enable : Data Bus GND OE PGM : Ground : Output Enable : Program Open VPP A8 A16 A10 A11 VDD RESET : Reset VDD : Power Supply VPP : Programming Power Supply (L) 7 PD178P018A BLOCK DIAGRAM TI1/P33 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 PORT 0 P00 6 6 P01 to P06 P10 to P15 TI2/P34 PORT 1 8-bit TIMER3 PORT 2 8 P20 to P27 WATCHDOG TIMER PORT 3 8 P30 to P37 BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10 to ANI5/P15 INTP0/P00 to INTP6/P06 PORT 4 78K/0 CPU CORE PROM (60 Kbytes) PORT 5 8 P40 to P47 SERIAL INTERFACE 0 8 P50 to P57 PORT 6 SERIAL INTERFACE 1 RAM (3 072 bytes) 6 A/D CONVERTER D/A CONVERTER (PWM) 7 INTERRUPT CONTROL FREQUENCY COUNTER 8 P60 to P67 PORT 12 6 P120 to P125 PORT 13 3 P132 to P134 3 PWM0/P132 to PWM2/P134 BEEP/P36 RESET X1 X2 VDDPORT GNDPORT VDD BUZZER OUTPUT RESET SYSTEM CONTROL CPU PERIPHERAL AMIFC FMIFC PLL EO0 EO1 VCOL VCOH PLL VOLTAGE REGULATOR VOLTAGE REGULATOR VOSC VCPU VDDPLL GNDPLL REGOSC REGCPU GND VPP 8 PD178P018A CONTENTS 1. PIN FUNCTION LIST .......................................................................................................................... 1.1 Pins in Normal Operating Mode ............................................................................................... 1.2 Pins in PROM Programming Mode ........................................................................................... 1.3 Pins Input/Output Circuits and Recommended Connection of Unused Pins ...................... 2. PROM PROGRAMMING .................................................................................................................... 2.1 Operating Modes ........................................................................................................................ 2.2 PROM Write Procedure ............................................................................................................. 2.3 PROM Read Procedure .............................................................................................................. 10 10 12 13 16 16 18 22 3. PROGRAM ERASURE (PD178P018AKK-T ONLY) ..................................................................... 23 4. OPAQUE FILM ON ERASURE WINDOW (PD178P018AKK-T ONLY) ..................................... 23 5. ONE-TIME PROM VERSION SCREENING .................................................................................... 23 6. ELECTRICAL SPECIFICATIONS (PRELIMINARY) .......................................................................... 24 7. PACKAGE DRAWINGS ..................................................................................................................... 46 APPENDIX A. DIFFERENCES BETWEEN PD178018A AND PD178018 SUBSERIES ................... 48 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 49 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 53 9 PD178P018A 1. PIN FUNCTION LIST 1.1 Pins in Normal Operating Mode (1) Port pins Pin Name P00 I/O Input Port 0. 7-bit input/output port. Function Input only After Reset Alternate Function Input INTP0 INTP1 to INTP6 ANI0 to ANI5 P01 to P06 I/O P10 to P15 I/O Input/output mode can be specified bit-wise. Input Input Port 1. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 2. 8-bit input/output port. Input/output mode can be specified bit-wise. P20 P21 P22 P23 P24 P25 P26 P27 I/O Input SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL P30 to P32 I/O P33 P34 P35 P36 P37 P40 to P47 I/O Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise. Input TI1 TI2 -- -- BEEP -- Port 4. 8-bit input/output port. Input/output mode can be specified in 8-bit units. Test input flag (KRIF) is set to 1 by falling edge detection. Port 5. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Middle voltage N-ch open-drain input/output port. LEDs can be driven directly. Input -- P50 to P57 I/O Input -- P60 to P63 I/O P64 to P67 Input -- P120 to P125 I/O Port 12. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 13. 3-bit output port. N-ch open-drain output port. Input -- P132 to P134 Output -- PWM0 to PWM2 10 PD178P018A (2) Non-port pins (1 of 2) Pin Name INTP0 to INTP6 SI0 SI1 SO0 SO1 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCL STB BUSY TI1 TI2 BEEP Output Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit busy input External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) Buzzer output A/D converter analog input PWM output Input Input -- Input Input Input I/O Serial interface serial clock input/output Input I/O Serial interface serial data input/output Input Output Serial interface serial data output Input I/O Input Function External maskable interrupt inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). Serial interface serial data input After Reset Alternate Function Input P00 to P06 Input Input P25/SB0/SDA0 P20 P26/SB1/SDA1 P21 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P27/SCK0 P23 P24 P33 P34 P36 P10 to P15 P132 to P134 ANI0 to ANI5 Input PWM0 to PWM2 EO0, EO1 VCOL VCOH AMIFC FMIFC RESET X1 X2 REGOSC REGCPU VDD GND VDDPORT GNDPORT VDDPLL Note GNDPLL Note Output Output Input Input Input Input Input Input -- -- -- -- -- -- -- -- -- Error out output from charge pump of the PLL frequency synthesizer Inputs PLL local band oscillation frequency (In HF, MF mode). Inputs PLL local band oscillation frequency (In VHF mode). Inputs AM intermediate frequency counter. Inputs FM intermediate frequency counter. System reset input Crystal resonator connection for system clock oscillation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Regulator for oscillator. Connected to GND via a 0.1-F capacitor. Regulator for CPU power supply. Connected to GND via a 0.1-F capacitor. Positive power supply Ground Positive power supply for port block Ground for port block Positive power supply for PLL Ground for PLL -- -- -- -- -- -- -- -- Note Connect a capacitor of approximately 1 000 pF between VDDPLL pin and GNDPLL pin. 11 PD178P018A (2) Non-port pins (2/2) Pin Name VPP I/O -- Function High-voltage applied during program write/verification. Connected directly to GND in normal operating mode. After Reset Alternate Function -- -- 1.2 Pins in PROM Programming Mode Pin Name RESET I/O Input Function PROM programming mode setting When +5 V or +12.5 V is applied to VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. PROM programming mode setting and high-voltage applied during program write/verification. Address bus Data bus PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input in PROM programming mode. Positive power supply Ground potential VPP A0 to A16 D0 to D7 CE OE PGM VDD GND Input Input I/O Input Input Input -- -- 12 PD178P018A 1.3 Pins Input/Output Circuits and Recommended Connection of Unused Pins Table 1-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 1-1 for the configuration of the input/output circuit of each type. Table 1-1. Type of I/O Circuit of Each Pin Pin Name P00/INTP0 P01/INTP1 to P06/INTP6 P10/ANI0 to P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30 to P32 P33/TI1, P34/TI2 P35 P36/BEEP P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67 P120 to P125 P132/PWM0 to P134/PWM2 EO0 EO1 VCOL, VCOH AMIFC, FMIFC VPP -- -- Connected to GND or GNDPORT directly 19 DTS-EO1 DTS-EO3 DTS-AMP Input Set to disabled status by software and open Output Set to the low-level output by software and open Open I/O Circuit Type 2 8 11-A 8 5 8 5 8 10 I/O Input I/O Recommended Connections of Unused Pins Connected to GND or GNDPORT Set in general-purpose input port mode by software and individually connected to VDD, VDDPORT, GND, or GNDPORT via a resistor. 5 8 5 5-G 5 13-D 5 13 PD178P018A Figure 1-1. Types of Pin Input/Output Circuits (1/2) Type 2 Type 8 VDD data IN output disable N-ch P-ch IN/OUT Schmitt-Triggered Input with Hysteresis Characteristics Type 5 Type 10 VDD data P-ch IN/OUT output disable input enable N-ch open-drain output disable data VDD P-ch IN/OUT N-ch Type 5-G Type 11-A VDD VDD data P-ch IN/OUT IN/OUT output disable comparator + - data P-ch N-ch P-ch output disable N-ch N-ch VREF (Threshold voltage) input enable Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively. 14 PD178P018A Figure 1-1. Types of Pin Input/Output Circuits (2/2) Type 13-D IN/OUT data output disable VDDPLL N-ch DW VDD OUT RD P-ch UP N-ch GNDPLL Middle-Voltage Input Buffer P-ch Type DTS-EO3 Type 19 Type DTS-AMP VDDPLL OUT N-ch IN Type DTS-EO1 VDDPLL DW P-ch OUT UP N-ch GNDPLL Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively. 15 PD178P018A 2. PROM PROGRAMMING The PD178P018A has an internal 60-Kbyte PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to "PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode." Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be specified). They cannot be written by a PROM writer which cannot specify the write address. 2.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 2-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 2-1. Operating Modes of PROM Programming Pin Operating Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET VPP VDD CE OE PGM D0 to D7 Remark x : L or H 16 PD178P018A (1) Read mode Read mode is set if CE = L and OE = L are set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple PD178P018As are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, and OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H and OE = H. Then, program verification can be performed, if CE = L and OE = L are set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L and OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X times (X 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, and OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple PD178P018As are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 17 PD178P018A 2.2 PROM Write Procedure Figure 2-1. Page Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 X=X+1 0.1-ms Program Pulse No X = 10? Yes Verify 4 bytes Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Fail Pass Verify All Bytes All Pass Fail Write End Defective Product Remark G = Start address N = Program last address 18 PD178P018A Figure 2-2. Page Program Mode Timing Page Data Latch Page Program Program Verify A2 to A16 A0, A1 D0 to D7 Data Input VPP VPP VDD Data Output VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 19 PD178P018A Figure 2-3. Byte Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 0.1-ms Program Pulse No X = 10? Yes Address = Address + 1 Vefity Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Fail Pass Verify All Bytes All Pass Fail Write End Defective Product Remark G = Start address N = Program last address 20 PD178P018A Figure 2-4. Byte Program Mode Timing Program Program Verify A0 to A16 D0 to D7 Data Input Data Output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. 2. 3. VDD should be applied before VPP, and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. 21 PD178P018A 2.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in "PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode". (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0 to A16 pins. (4) Read mode (5) Output data to D0 to D7 pins. The timings of the above steps (2) to (5) are shown in Figure 2-5. Figure 2-5. PROM Read Timings A0 to A16 Address Input CE (Input) OE (Input) D0 to D7 Hi-Z Data Output Hi-Z 22 PD178P018A 3. PROGRAM ERASURE (PD178P018AKK-T ONLY) The PD178P018AKK-T is capable of erasing (FFH) the data written in a program memory and rewriting. To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the programmed data is as follows: * UV intensity x erasure time: 30 W*s/cm2 or more * Erasure time: 40 min. or more (When a UV lamp of 12 000 W/cm 2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.) When erasing the contents of the data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter. 4. OPAQUE FILM ON ERASURE WINDOW (PD178P018AKK-T ONLY) To protect from an intentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when EPROM contents erasure is not performed. 5. ONE-TIME PROM VERSION SCREENING The one-time PROM version (PD178P018AGC-3B9) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below. Storage Temperature 125 C Storage Time 24 hours 23 PD178P018A 6. ELECTRICAL SPECIFICATIONS (PRELIMINARY) Caution The following electrical specifications are preliminary values for this product. When designing, be sure to refer to the data sheet describing the official electrical specifications. PD178P018A Data Sheet: to be prepared ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Parameter Power supply voltage Symbol VDD VPP Input voltage VI1 VI2 VI3 Output voltage Output withstand voltage Analog input voltage Output current high VO VBDS P132 to P134 N-ch open-drain Excluding P60 to P63 P60 to P63 A9 N-ch open-drain PROM programming mode Test Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +16 -0.3 to +13.5 -0.3 to VDD + 0.3 16 Unit V V V V V V V VAN IOH P10 to P15 1 pin Analog input pin -0.3 to VDD + 0.3 -10 -15 V mA mA P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P125 total P10 to P15, P20 to P27, P40 to P47, P50 to P55, P132 to P134 total Output current low IOL Note 1 pin Peak value r.m.s. value Operating ambient temperature Storage temperature Tstg TA -15 mA 15 7.5 -40 to +85 mA mA C C -65 to +150 Note r.m.s. (root mean square) value should be calculated as follows: [r.m.s value] = [Peak value] x duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. RECOMMENDED SUPPLY VOLTAGE RANGES (TA = -40 to +85 C) Parameter Power supply voltage Symbol VDD1 VDD2 Test Conditions During CPU operation and PLL operation. While the CPU is operating and the PLL is stopped. Cycle Time: TCY 0.89 s While the CPU is operating and the PLL is stopped. Cycle Time: TCY = 0.44 s MIN. 4.5 3.5 TYP. MAX. 5.5 5.5 Unit V V VDD3 4.5 5.5 V Remark TCY: Cycle Time (Minimum instruction execution time) 24 PD178P018A DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (1/3) Parameter Input voltage high Symbol VIH1 P10 P30 P40 P64 to to to to P15, P32, P47, P67, Test Conditions P21, P23, P35 to P37, P50 to P57, P120 to P125 MIN. 0.7 VDD TYP. MAX. VDD Unit V VIH2 P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch open-drain) P10 P30 P40 P64 to to to to P15, P32, P47, P67, P21, P23, P35 to P37, P50 to P57, P120 to P125 0.85 VDD VDD V VIH3 0.7 VDD 15 V Input voltage low VIL1 0 0.3 VDD V VIL2 P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch open-drain) 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V, IOH = -1 mA 3.5 V VDD < 4.5 V, IOH = -100 A 0 0.15 VDD V VIL3 0 0 VDD - 1.0 0.3 VDD 0.2 VDD V V V Output voltage high VOH1 VDD - 0.5 V Output voltage low VOL1 P50 to P57, P60 to P63 VDD = 4.5 to 5.5 V, IOH = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0.4 2.0 V P01 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P120 to P125, P132 to P134 VOL2 SB0, SB1, SCK0 0.4 V VDD = 4.5 to 5.5 V, N-ch open-drain pulled-up (R = 1 K) 0.2 VDD V Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. 25 PD178P018A DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) Parameter Input leakage current high Symbol ILIH1 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P132 to P134 VOUT = 15 V P10 to P15, P30 to P37, P50 to P57, P120 to P125, Test Conditions P10 to P15, P30 to P37, P50 to P57, P120 to P125, VIN = VDD MIN. TYP. MAX. 3 (2/3) Unit A ILIH2 Input leakage current low ILIL1 VIN = 15 V VIN = 0 V 80 -3 A A ILIL2 Output leakage current high Output leakage current low Output off leak current ILOH -3 Note 3 A A A A ILOL P132 to P134 VOUT = 0 V -3 1 ILOF EO0, EO1 VOUT = VDD, VOUT = 0 V Note When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes -200 A (MAX.) only in one clock cycle (at no wait). It remains at -3 A (MAX.) for other than an input instruction. Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. REFERENCE CHARACTERISTICS (TA = 25 C, VDD = 5 V) Parameter Output current high Symbol IOH1 EO0 EO1 (EOCON0 = 0) Output current low IOL1 EO0 EO1 (EOCON0 = 0) VOUT = 1 V 3.5 Test Conditions VOUT = VDD - 1 V -1.8 6 MIN. TYP. -4 MAX. (1/2) Unit mA mA mA mA 26 PD178P018A DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) Parameter Power supply current Note 1 IDD2 Symbol IDD1 Test Conditions While the CPU is operating and the PLL is stopped fX = 4.5-MHz operation TCY = 0.89 s Note 2 (3/3) MIN. TYP. 2.5 MAX. 15 Unit mA TCY = 0.44 s Note 3 VDD = 4.5 to 5.5 V TCY = 0.89 s Note 2 4.0 27 mA IDD3 While the CPU is operating and the PLL is stopped HALT Mode. Pin X1 sine wave input VIN = VDD fX = 4.5-MHz operation When the crystal is oscillating 1 4 mA IDD4 TCY = 0.44 s Note 3 VDD = 4.5 to 5.5 V TCY = 0.44 s TCY = 0.89 s 1.6 6 mA Data hold power supply voltage VDDR1 VDDR2 VDDR3 4.5 3.5 2.7 5.5 5.5 5.5 V V V When the crystal oscillation is stopped When power off by Power On Clear is detected While the crystal oscillation is stopped TA = 25 C, VDD = 5 V Data hold power supply current IDDR1 IDDR2 2 2 4 30 A A Notes 1. The port current is not included. 2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register (OSMS) is set to 00H. 3. When PCC is set to 00H and OSMS is set to 01H. Remarks 1. TCY: Cycle Time (Minimum instruction execution time) 2. fX: System clock oscillation frequency. REFERENCE CHARACTERISTICS (TA = 25 C, VDD = 5 V) Parameter Power supply current Symbol IDD5 Test Conditions During CPU operation and PLL operation. VCOH pin sine wave input fIN = 130 MHz, VIN = 0.15 Vp-p TCY = 0.44 s Note (2/2) MIN. TYP. 7 MAX. Unit mA Note When the Processor Clock Control register (PCC) is set to 00H, and the Oscillation Mode Select register (OSMS) is set to 01H. Remark TCY: Cycle Time (Minimum instruction execution time) 27 PD178P018A AC CHARACTERISTICS (1) BASIC OPERATION (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) Parameter Cycle time (Minimum instruction execution time) TI1, TI2 input frequency TI1, TI2 input high/ low-level width Interrupt input high/ low-level width RESET low-level width tTIH, tTIL TINTH, TINTL tRSL fTI Symbol TCY fXX = fX/2 fXX = fX Note 1 Test Conditions , fX = 4.5-MHz operation 4.5 VDD 5.5 V 3.5 VDD < 4.5 V MIN. 0.89 0.44 0.89 0 0 111 1.8 8/fsam Note 3 TYP. MAX. 14.22 7.11 7.11 4.5 275 Unit s s s MHz kHz ns Note 2 , fX = 4.5-MHz operation 4.5 VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 VDD 5.5 V 3.5 V VDD < 4.5 V INTP0 INTP1 to INTP6 s s s s 10 10 Notes 1. When the Oscillation Mode Selection register (OSMS) is set to 00H. 2. When OSMS is set to 01H. 3. In combination with bits 0 (SCS0) and 1 (SCS1) of the Sampling Clock Select register (SCS), selection of fsam is possible among fXX/2 N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4). Remarks 1. fXX: System clock frequency (fX or fX/2) 2. fX: System clock oscillation frequency TCY vs VDD (when system clock fXX is operating at fX/2) TCY vs VDD (when system clock fXX is operating at fX) 60 60 10 Cycle Time TCY [s] Operation Guaranteed Range 2.0 1.0 0.5 0.4 Cycle Time TCY [s] 10 2.0 1.0 0.5 0.4 Operation Guaranteed Range 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] Power Supply Voltage VDD [V] 28 PD178P018A (2) SERIAL INTERFACE (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pF Note MIN. 800 1 600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns Note C is the load capacitance of the SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns SCK0 cycle time SCK0 high-/low-level width tKH2, tKL2 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rising or falling edge time tSIK2 tKSI2 tKSO2 tR2, tF2 Note C is the load capacitance of the SO0 output line. 29 PD178P018A (iii) SBI mode (SCK0 ... internal clock output) Parameter SCK0 cycle time Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 R = 1 k 4.5 V VDD 5.5 V MIN. 800 3 200 tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns C = 100 pF Note 3.5 V VDD < 4.5 V Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. (iv) SBI mode (SCK0 ... external clock input) Parameter SCK0 cycle time Symbol tKCY4 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) tSIK4 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rising or falling edge time tKSB tSBK tSBH tSBL tR4, tF4 tKSI4 tKSO4 R = 1 k 4.5 V VDD 5.5 V MIN. 800 3 200 400 1 600 100 300 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 1 000 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns C = 100 pF Note 3.5 V VDD < 4.5 V Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. 30 PD178P018A (v) 2-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Test Conditions R = 1 k C = 100 pF Note MIN. 1 600 tKCY5/2 - 160 TYP. MAX. Unit ns ns ns ns ns ns ns ns 4.5 V VDD 5.5 V tKCY5/2 - 50 3.5 V VDD < 4.5 V tKCY5/2 - 100 SB0, SB1 setup time (to SCK0) tSIK5 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 300 350 400 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI5 tKSO5 600 0 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) 2-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k C = 100 pF tR6, tF6 Note Test Conditions MIN. 1 600 650 800 100 tKCY6/2 TYP. MAX. Unit ns ns ns ns ns SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 at rising or falling edge time 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 0 0 300 500 1 000 ns ns ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. 31 PD178P018A (vii) I2C bus mode (SCL ... internal clock output) Parameter SCL cycle time SCL high-level width SCL low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time (from SCL) SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width Symbol tKCY7 tKH7 tKL7 tSIK7 tKSI7 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V tKSB Test Conditions R = 1 k C = 100 pF Note MIN. 10 tKCY7 - 160 tKCY7 - 50 200 0 TYP. MAX. Unit s ns ns ns ns tKSO7 0 0 200 300 500 ns ns ns tSBK tSBH 400 500 ns ns Note R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines. (viii) I 2C bus mode (SCL ... external clock input) Parameter Symbol tKCY8 tKH8, tKL8 tSIK8 tKSI8 4.5 V VDD 5.5 V Test Conditions MIN. 1 000 400 200 0 TYP. MAX. Unit ns ns ns ns SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL rising or falling edge time tKSO8 R = 1 k 0 0 200 300 500 ns ns ns C = 100 pF Note 3.5 V VDD < 4.5 V tKSB tSBK tSBH tR8, tF8 400 500 1 000 ns ns ns Note R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines. 32 PD178P018A (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter SCK1 cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high-/low-level width tKH9, tKL9 SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) tKSI9 tKSO9 C = 100 pF Note MIN. 800 1 600 tKCY9/2 - 50 tKCY9/2 - 100 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns 300 ns Note C is the load capacitance of the SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input) Parameter Symbol tKCY10 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns SCK1 cycle time SCK1 high-/low-level width tKH10, tKL10 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) SCK1 rising or falling edge time tSIK10 tKSI10 tKSO10 tR10, tF10 Note C is the load capacitance of the SO1 output line. 33 PD178P018A (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock output) Parameter SCK1 cycle time Symbol tKCY11 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high-/low-level width tKH11, tKL11 SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSPS tKSI11 tKSO11 tSBD tSBW tBYS 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V C = 100 pF Note tKCY11/2 - 100 tKCY11 - 30 100 MIN. 800 1 600 tKCY11/2 - 50 tKCY11/2 - 100 100 150 400 300 tKCY11/2 + 100 tKCY11 + 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns tBYH 100 150 2tKCY11 ns ns ns Note C is the load capacitance of the SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock input) Parameter Symbol tKCY12 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns SCK1 cycle time SCK1 high-/low-level width tKH12, tKL12 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) SCK1 rising or falling edge time tSIK12 tKSI12 tKSO12 tR12, tF12 Note C is the load capacitance of the SO1 output line. 34 PD178P018A AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD TI Timing 1/fTI tTIL tTIH TI1, TI2 Interrupt Input Timing tINTL tINTH INTP0 to INTP6 RESET Input Timing tRSL RESET 35 PD178P018A Serial Transfer Timing 3-Wire Serial I/O Mode: tKCYm tKLm tRn SCK0, SCK1 tKHm tFn tSIKm tKSIm SI0, SI1 Input Data tKSOm SO0, SO1 Output Data Remark m = 1, 2, 9, 10 n = 2, 10 SBI Mode (Bus Release Signal Transfer): tKL3, 4 tR4 SCK0 tKCY3, 4 tKH3, 4 tF4 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 36 PD178P018A SBI Mode (Command Signal Transfer): tKCY3, 4 tKL3, 4 tR4 SCK0 tSIK3, 4 tKH3, 4 tF4 tKSB tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 2-Wire Serial I/O Mode: tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKH5, 6 tF6 tKSO5, 6 tKSI5, 6 SB0, SB1 I 2C Bus Mode: tF8 SCL tKL7, 8 tR8 tKCY7, 8 tSIK7, 8 tKSO7, 8 tKSB tSBK tKSB tKSI7, 8 tKH7, 8 SDA0, SDA1 tSBH tSBK 37 PD178P018A 3-Wire Serial I/O Mode with Automatic Transmit/Receive Function: SO1 D2 D1 D0 D7 SI1 D2 tSIK11, 12 tKSO11, 12 D1 tKSI11, 12 tKH11, 12 D0 D7 tF12 SCK1 tR12 tKL11, 12 tKCY11, 12 STB tSBD tSBW 3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing): SCK1 7 8 9 Note 10 Note tBYH 10 + n Note tSPS 1 tBYS BUSY (Active high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. 38 PD178P018A A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Resolution Conversion total error Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN 22.2 15/fXX 0 VDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 3.0 44.4 Unit bit LSB s s V Remarks 1. fXX: System clock frequency (fX/2) 2. fX: System clock oscillation frequency PLL CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN1 fIN2 fIN3 Test Conditions VCOL Pin MF Mode Sine wave input VIN = 0.1 Vp-p VCOL Pin HF Mode Sine wave input VIN = 0.2 Vp-p VCOH Pin VHF Mode Sine wave input VIN = 0.15 Vp-p MIN. 0.5 9 60 TYP. MAX. 3 55 160 Unit MHz MHz MHz IFC CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN4 Test Conditions AMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note FMIFC Pin FMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note FMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note MIN. 0.4 TYP. MAX. 0.5 Unit MHz fIN5 10 11 MHz fIN6 0.4 0.5 MHz Note The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at an input amplitude condition of VIN = 0.15 Vp-p. 39 PD178P018A PROM PROGRAMMING CHARACTERISTICS DC CHARACTERISTICS (1) PROM Write Mode (TA = 25 5 C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol Symbol Note VIH VIL VOH VOL ILI VPP VDD IPP IDD VIH VIL VOH VOL ILI VPP VCC IPP ICC PGM = VIL IOH = -1 mA IOL = 1.6 mA 0 VIN VDD -10 12.2 6.25 12.5 6.5 Test Conditions MIN. 0.7 VDD 0 VDD - 1.0 0.4 +10 12.8 6.75 50 50 TYP. MAX. VDD 0.3 VDD Unit V V V V A V V mA mA (2) PROM Read Mode (TA = 25 5 C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current Output leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol Symbol Note VIH VIL VOH1 VOH2 VOL ILI ILO VPP VDD IPP IDD VIH VIL VOH1 VOH2 VOL ILI ILO VPP VCC IPP ICCA1 VPP = VDD CE = VIL, VIN = VIH IOH = -1 mA IOH = -100 A IOL = 1.6 mA 0 VIN VDD 0 VOUT VDD, OE = VIH -10 -10 VDD - 0.6 4.5 VDD 5.0 Test Conditions MIN. 0.7 VDD 0 VDD - 1.0 VDD - 0.5 0.4 +10 +10 VDD + 0.6 5.5 100 50 TYP. MAX. VDD 0.3 VDD Unit V V V V V A A V V A mA Note Corresponding PD27C1001A symbol. 40 PD178P018A AC CHARACTERISTICS (1) PROM Write Mode (a) Page program mode (TA = 25 5 C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Address setup time (to OE ) OE setup time CE setup time (to OE ) Input data setup time (to OE ) Address hold time (from OE ) Symbol Symbol Note tAS tOES tCES tDS tAH tAHL tAHV Input data hold time (from OE ) Data output float delay time from OE VPP setup time (to OE ) VDD setup time (to OE ) Program pulse width Valid data delay time from OE OE pulse width during data latching PGM setup time CE hold time OE hold time tPGMS tCEH tOEH tPGMS tCEH tOEH 2 2 2 tVPS tVDS tPW tOE tLW tVPS tVCS tPW tOE tLW 1 1.0 1.0 0.095 0.1 0.105 1 ms ms ms tDH tDF tAS tOES tCES tDS tAH tAHL tAHV tDH tDF Test Conditions MIN. 2 2 2 2 2 2 0 2 0 250 TYP. MAX. Unit s s s s s s s s ns s s s s s (b) Byte program mode (TA = 25 5 C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Address setup time (to PGM ) OE set time CE setup time (to PGM ) Input data setup time (to PGM ) Address hold time (from OE ) Input data hold time (from PGM ) Data output float delay time from OE VPP setup time (to PGM ) VDD setup time (to PGM ) Program pulse width Valid data delay time from OE OE hold time tVPS tVDS tPW tOE tOEH tVPS tVCS tPW tOE -- 2 1.0 1.0 0.095 0.1 0.105 1 ms ms ms tDF tDF 0 250 ns Symbol Symbol Note tAS tOES tCES tDS tAH tDH tAS tOES tCES tDS tAH tDH Test Conditions MIN. 2 2 2 2 2 2 TYP. MAX. Unit s s s s s s s s Note Corresponding PD27C1001A symbol. 41 PD178P018A (2) PROM Read Mode (TA = 25 5 C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Data output delay time from address Data output delay time CE Data output delay time OE Data output float delay time from OE Data hold time to address tOH tOH CE = OE = VIL 0 ns tCE tOE tDF tCE tOE tDF OE = VIL CE = VIL CE = VIL 0 800 200 60 ns ns ns Symbol Symbol Note tACC tACC Test Conditions CE = OE = VIL MIN. TYP. MAX. 800 Unit ns Note Corresponding PD27C1001A symbol. (3) PROM Programming Mode Setting (TA = 25 C, VSS = 0 V) Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. 10 TYP. MAX. Unit s 42 PD178P018A PROM Write Mode Timing (page program mode) Page Data Latch Page Program Program Verify A2 to A16 tAS A0, A1 tDS D0 to D7 Hi-Z tDH Hi-Z tPGMS Data Output tDF Hi-Z tAHL tAHV tVPS VPP VPP VDD tVDS VDD + 1.5 VDD VDD Data Input tOE tAH tCES VIH CE VIL VIH PGM VIL tLW VIH OE VIL tOES tPW tCEH tOEH 43 PD178P018A PROM Write Mode Timing (byte program mode) Program Program Verify A0 to A16 tAS Hi-Z tDS VPP VPP VDD tVPS VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL tOES tOE tCES tPW Hi-Z tDH tDF Hi-Z tAH D0 to D7 Data Input Data Output tVDS tOEH Cautions 1. 2. 3. VDD should be applied before VPP, and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. PROM Read Mode Timing A0 to A16 Effective Address VIH CE VIL tCE VIH OE VIL tACC Note1 D0 to D7 Hi-Z tOE Note 1 tDF Note 2 tOH Data Output Hi-Z Notes 1. If you want to read within the range of tACC, make the OE input delay time from the fall of CE a maximum of tACC - tOE. 2. tDF is the time from when either OE or CE first reaches VIH. 44 PD178P018A PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0 to A16 Effective Address 45 PD178P018A 7. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end CD S Q R 80 1 21 20 F G H P I M J K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. S80GC-65-3B9-4 46 PD178P018A 80 PIN CERAMIC WQFN A B K Q T U1 C D W 80 H IM J 1 R S X80KW-65A-1 MILLIMETERS 14.0 0.2 13.6 13.6 14.0 0.2 1.84 3.6 MAX. 0.45 0.10 0.06 0.65 (T.P.) 1.0 0.15 C 0.3 0.825 0.825 R 2.0 9.0 2.1 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 C 0.012 0.032 0.032 R 0.079 0.354 0.083 0.030+0.006 -0.007 0.004 U Z NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K Q R S T U U1 W Z F G 47 PD178P018A APPENDIX A. DIFFERENCES BETWEEN PD178018A AND PD178018 SUBSERIES Product Name PD178018A Subseries PD178004A PD178006A PD178016A PD178018A PD178P018A Note PD178004 PD178018 Subseries PD178006 PD178016 PD178018 PD178P018 Item PLL frequency synthesizer Reference frequency EO0 pin output format EO1 pin output format 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Buffer type 11 types selectable by program (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 kHz) Buffer type Constant-current power supply type EO1 pin highNot supported impedance function Supported Not supported Note Under development Remark The mask ROM of mask versions (PD178018A and PD178018) is replaced with one-time PROM or EPROM in the one-time PROM versions (PD178P018A and PD178P018). 48 PD178P018A APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD178P018A Subseries. Language Processing Software RA78K/0 Notes 1, 2, 3, 4 CC78K/0 Notes 1, 2, 3, 4 Notes 1, 2, 3, 4, 8 Notes 1, 2, 3, 4 78K/0 Series common assembler package 78K/0 Series common C compiler package DF178018 PD178018A Subseries common device file 78K/0 Series common C compiler library source file CC78K/0-L PROM Writing Tools PG-1500 PG-178P018GC PA-178P018KK-T PG-1500 controller Notes 1, 2 PG-1500 control program PROM writer Program writer adapters connected to a PG-1500 Debugging Tools IE-78000-R IE-78000-R-A IE-78000-R-BK IE-178018-R-EM IE-78000-R-SV3 IE-70000-98-IF-B In-circuit emulator common to 78K/0 Series In-circuit emulator common to 78K/0 Series (for the integrated debugger) Break board common to 78K/0 Series Emulation board common to PD178018A Subseries Interface adapter and cable when using EWS as a host machine (for IE-78000-R-A) Interface adapter when using the PC-9800 Series (except notebooks) as a host machine (for IE-78000-R-A) IE-70000-98N-IF Interface adapter and cable when using the PC-9800 Series notebook as a host machine (for IE-78000-R-A) IE-70000-PC-IF-B EP-78230GC-R EV-9200GC-80 EV-9900 SM78K0 ID78K0 Notes 5, 6, 7 Interface adapter when using IBM PC/ATTM as a host machine (for IE-78000-R-A) Emulation probe common to PD78234 Subseries Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type) Jig used when removing the PD178P018AKK-T from the EV-9200GC-80. 78K/0 series common system simulator Integrated debugger for IE-78000-R-A IE-78000-R screen debugger Notes 4, 5, 6, 7 Notes 1, 2 Notes 1, 2, 4, 5, 6, 7, 8 SD78K/0 DF178018 PD178018A Subseries device file 49 PD178P018A Real-Time OS RX78K/0 Notes 1, 2, 3, 4 MX78K0 Notes 1, 2, 3, 4 78K/0 Series real-time OS 78K/0 Series OS Notes 1. 2. 3. 4. 5. 6. 7. 8. PC-9800 Series (MS-DOS TM) based IBM PC/AT and compatibles (PC DOS TM/IBM DOSTM/MS-DOS) based HP9000 Series 300 TM (HP-UXTM) based HP9000 Series 700 TM (HP-UXTM ) based, SPARCstationTM (SunOS TM) based, EWS4800 Series (EWS-UX/V) based PC-9800 Series (MS-DOS + WindowsTM ) based IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based NEWS TM (NEWS-OSTM ) based Under development Fuzzy Inference Development Support System FE9000 Note 1/FE9200 Note 2 FT9080 FI78K0 Note 1 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger /FT9085 Note 3 Notes 1, 3 Notes 1, 3 FD78K0 Notes 1. PC-9800 Series (MS-DOS) based 2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based 3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0, and RX78K/0 are used in combination with the DF178018. 50 PD178P018A CONVERSION SOCKET DRAWING AND RECOMMENDED FOOTPRINT Figure B-1. Drawing of EV-9200GC-80 (for Reference only) Based on EV-9200GC-80 (1) Package drawing (in mm) A E B F M N O D C R S J K EV-9200GC-80 1 No.1 pin index P G H I EV-9200GC-80-G1E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 Q INCHES 0.709 0.567 0.567 0.709 4-C 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 L 51 PD178P018A Figure B-2. Recommended Footprint of EV-9200GC-80 (for Reference only) Based on EV-9200GC-80 (2) Pad drawing (in mm) G J K D E F H L C B A EV-9200GC-80-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 19.7 15.0 INCHES 0.776 0.591 0.591 0.776 0.236+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001 0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486+0.003 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.093+0.001 -0.002 0.091 0.062+0.001 -0.002 Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). 52 I PD178P018A APPENDIX C. RELATED DOCUMENTS Device Documents Title Document No. (Japanese) Document No. (English) PD178018A Subseries User's Manual 78K/0 Series User's Manual--Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table To be prepared U12326J U10904J U10903J To be prepared U12326E -- -- -- U10121E PD178018A Subseries Special Function Register Table 78K/0 Series Application Note Basics (II) To be prepared U10121J Development Tool Documents (User's Manual) Title RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series C Compiler Operation Language CC78K/0 C Compiler Operation Language CC78K/0 C Compiler Application Notes CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller IBM PC Series (PC DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-178018-R-EM EP-78230 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User open Interface Specifications Reference Reference Guide Introduction Reference SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based Introduction Reference Programming Know-how Document No. (Japanese) EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 U10668J EEU-985 U10181J U10092J Document No. (English) EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 U10668E EEU-1515 U10181E U10092E ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J U11151E U11539E U11649E U10539E -- EEU-1414 U11279E Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. 53 PD178P018A Related Documents for Embedded Software (User's Manual) Title 78K/0 Series Realtime OS Basics Installation 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System--Translator 78K/0 Series Fuzzy Inference Development Support System--Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System --Fuzzy Inference Debugger EEU-858 EEU-921 EEU-1441 EEU-1458 Basics Document No. (Japanese) U11537J U11536J U12257J EEU-829 EEU-862 Document No. (English) -- -- -- EEU-1438 EEU-1444 Other Documents Title IC Package Manual Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control System Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcomputer-related Product Guide (Products by other Manufacturers) Document No. (Japanese) C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E -- MEI-1202 -- Document No. (English) Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc. 54 PD178P018A [MEMO] 55 PD178P018A [MEMO] 56 PD178P018A [MEMO] 57 PD178P018A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 58 PD178P018A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 59 PD178P018A Purchase of NEC I2 C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2 C Standard Specification as defined by Philips. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed : PD178P018AKK-T The customer must judge the need for license : PD178P018AGC-3B9 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 60 |
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