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TC7135
4-1/2 Digit A/D Converter
Features
* * * * * * * * * * * * * Low Rollover Error: 1 Count Max Nonlinearity Error: 1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1pA Low Zero Reading Drift: 2V/C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages
General Description
The TC7135 4-1/2 digit A/D converter (ADC) offers 50ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto zero cycle reduces zero error to below 10V and zero drift to 0.5V/C. Source impedance errors are minimized by a 10pA maximum input current. Rollover error is limited to 1 count. Microprocessor based measurement systems are supported by BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor based measurement systems.
Functional Block Diagram
SET VREF = 1V VREF IN 100k -5V 1 2 V-
TC7135
UNDERRANGE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Clock Input 120kHz
Applications
* Precision Analog Signal Processor * Precision Sensor Interface * High Accuracy DC Measurements
Device Selection Table
Part Number TC7135CLI TC7135CPI TC7135CBU Package 28-Pin PLCC 28-Pin PDIP 64-Pin PQFP Temperature Range 0C to +70C 0C to +70C 0C to +70C
REF IN OVERRANGE 3 ANALOG STROBE COMMON Analog GND 4 RUN/HOLD INT OUT 1F 0.47F 5 DIGTAL GND AZ IN 6 BUFF OUT POLARITY 100k 7 CLOCK IN C 100 Signal 1F 8 REF k BUSY Input CREF+ 9 -INPUT (LSD) D1 0.1F 10 D2 +INPUT 11 D3 +5V V+ 12 D5 (MSD) D4 13 B1 (LSB) (MSB) B8 14 B2 B4
2002 Microchip Technology Inc.
DS21460B-page 1
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TC7135
Package Types
28-Pin PDIP
INT OUT ANALOG COM REF IN STROBE
VREF IN ANALOG COM INT OUT 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY AZ IN BUFF OUT C REFCREF+ - INPUT 1 2 3 4 5 6 7 8 9
28-Pin PDIP
28 UNDERRANGE 27 OVERRANGE
V-
OR
UR
26 STROBE 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY
4 AZ IN 5 BUFF OUT 6 REF CAP- 7 REF CAP+ 8 -INPUT 9 +INPUT 10 V + 11
3
2
1
28 27 26
TC7135
22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2
TC7135
22 CLOCK IN 21 BUSY 20 19 18 D1 (LSD) D2 D3
+INPUT 10 V+ 11 (MSD) D5 12 (LSB) B1 13 B2 14
12 13 14 15 16 17 18
D4
(MSD) D5
(MSB) B8
(LSB) B1
D3
B2
B4
17 D4 16 B8 (MSB) 15 B4
64-Pin PQFP
RUN/HOLD CLOCK IN STROBE DGND
POL
BUSY
NC
NC
NC
NC
NC
NC
NC NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 OVERRANGE 7 UNDERRANGE 8 NC 9 V- 10 REF IN 11 ANALOG COM 12 NC 13 NC 14 NC 15 NC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 l 48 NC 47 NC 46 NC 45 D3 44 D4 43 B8 42 B4
TC7135
NC
41 B2 40 NC 39 B1 38 D5 37 NC 36 NC 35 NC 34 NC 33 NC
D1 -INPUT
BUFF OUT
D2
+INPUT
INT OUT
AZ IN
NC
NC
NC
NC
NC
NC
NOTE: NC = No internal connection.
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C REF +
C REF -
NC
V+
2002 Microchip Technology Inc.
TC7135
1.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Positive Supply Voltage..........................................+6V Negative Supply Voltage ....................................... - 9V Analog Input Voltage (Pin 9 or 10) .... V+ to V- (Note 2) Reference Input Voltage (Pin 2) ...................... V+ to VClock Input Voltage ........................................ 0V to V+ Operating Temperature Range ............... 0C to +70C Storage Temperature Range ............ - 65C to +150C Package Power Dissipation; (TA 70C) 28-Pin PDIP ..................................... 1.14 28-Pin PLCC .................................... 1.00 64-Pin PQFP .....................................1.14
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
TC7135 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TA = +25C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Parameter Min Typ Max Unit Test Conditions
Analog
Display Reading with Zero Volt Input TC Z TC FS NL DNL FSE IIN eN Digital IIL IIH VOL V OH Input Low Current Input High Current Output Low Voltage Output High Voltage; B1, B2, B4, B8, D 1 -D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency -- -- -- 2.4 4.9 10 0.08 0.2 4.4 4.99 100 10 0.4 5 5 Zero Reading Temperature Coefficient Full Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation Full Scale Symmetry Error (Rollover Error) Input Leakage Current Noise -0.0000 -- -- -- -- +0.9996 -- -- -- 0.0000 0.5 -- 0.5 0.01 +0.9999 0.5 1 15 +0.0000 2 5 1 -- +1.0000 1 10 -- Display Reading Note 2 and Note 3 VIN = 0V, (Note 4) VIN = 2V, (Note 4 and Note 5) Note 6 Note 6 VIN = VREF, (Note 2) -VIN = +VIN, (Note 7) Note 3 Peak-to-Peak Value not Exceeded 95% of Time VIN = 0V VIN = +5V IOL = 1.6mA IOH = 1mA IOH = 10A
V/C
ppm/C Count LSB Display Reading Count pA
VP-P
A A
V V V
FCLK Note 1: 2: 3: 4: 5: 6: 7: 8:
0
200
1200
kHz
Note 8
Limit input current to under 100A if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30C TA +70C .External reference temperature coefficient less than 0.01ppm/C. -2V VIN +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies.
2002 Microchip Technology Inc.
DS21460B-page 3
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TC7135
TC7135 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TA = +25C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Power Supply V+ VI+ IPD Note 1: 2: 3: 4: 5: 6: 7: 8: Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation 4 -3 -- -- -- 5 -5 1 0.7 8.5 6 -8 3 3 30 V V mA mA mW FCLK = 0Hz FCLK = 0Hz FCLK = 0Hz Parameter Min Typ Max Unit Test Conditions
Limit input current to under 100A if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30C TA +70C .External reference temperature coefficient less than 0.01ppm/C. -2V VIN +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies.
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2002 Microchip Technology Inc.
TC7135
2.0 PIN DESCRIPTIONS
The description of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number 28-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PIN FUNCTION TABLE
Symbol VREF IN ANALOG COMMON INT OUT AZ IN BUFF OUT CREFCREF+ -INPUT +INPUT V+ D5 B1 B2 B4 B8 D4 D3 D2 D1 BUSY CLOCK IN POLARITY Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. Reference capacitor input. Reference capacitor negative connection. Reference capacitor input. Reference capacitor positive connection. Analog input. Analog input negative connection. Analog input. Analog input positive connection. Positive power supply input. Digit drive output. Most Significant Digit (MSD) Binary Coded Decimal (BCD) output. Least Significant Bit (LSB) BCD output. BCD output. BCD output. Most Significant Bit (MSB) Digit drive output. Digit drive output. Digit drive output. Digit drive output. Least Significant Digit (LSD) Busy output. At the beginning of the signal-integration phase, BUSY goes High and remains High until the first clock pulse after the integrator zero crossing. Clock input. Conversion clock connection. Polarity output. A positive input is indicated by a logic High output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. Digital logic reference input. Run / Hold input. When at a logic High, conversions are performed continuously. A logic Low holds the current data as long as the Low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. Over range output. A logic High indicates that the analog input exceeds the full scale input range. Under range output. A logic High indicates that the analog input is less than 9% of the full scale input range. Description
24 25 26 27 28
DGND RUN/HOLD STROBE OVERRANGE UNDERRANGE
2002 Microchip Technology Inc.
DS21460B-page 5
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TC7135
3.0
3.1
DETAILED DESCRIPTION
Dual Slope Conversion Principles
(All Pin Designations Refer to 28-Pin DIP)
ent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1).
The TC7135 is a dual slope, integrating A/D converter. An understanding of the dual slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration Reference voltage integration (de-integration)
FIGURE 3-1:
BASIC DUAL SLOPE CONVERTER
Integrator Comparator + Clock Control Logic Counter VIN VREF VIN 1/2 VREF Variable Reference Integrate Time Switch Drive
Analog Input Signal
The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down." A simple mathematical equation relates the input signal, reference voltage, and integration time:
REF Voltage
Phase Control Polarity Control
Display
Integrator Output
EQUATION 3-1:
TINT VREF T DEINT 1 VIN(T)DT = R C RINTC INT 0 INT INT where: VREF TINT = Reference voltage = Signal integration time (fixed)
Fixed Signal Integrate Time
3.2
TC7135 Operational Theory
TDEINT = Reference voltage integration time (variable). For a constant VIN:
The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. The TC7135 measurement cycle contains four phases: 1. 2. 3. 4. System zero Analog input signal integration Reference voltage integration Integrator output zero
EQUATION 3-2:
VIN = VREF TDEINT TINT
The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inher-
Internal analog gate status for each phase is shown in Figure 3-1.
TABLE 3-1:
INTERNAL ANALOG GATE STATUS
SWI Closed Closed* Closed Closed Closed SWRI+ SWRISWZ Closed SWR Closed SW1 Closed SWIZ Reference Figures Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5
Conversion Cycle Phase System Zero Input Signal Integration Reference Voltage Integration Integrator Output Zero *Note:
Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
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TC7135
3.2.1 SYSTEM ZERO 3.2.3
During this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging CAZ (auto zero capacitor) with a compensating error voltage. With a zero input voltage the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to ANALOG COMMON. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages (see Figure 3-2).
REFERENCE VOLTAGE INTEGRATION
The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is:
EQUATION 3-3:
Reading = 10,000 [Differential Input] VREF
FIGURE 3-4:
REFERENCE VOLTAGE INTEGRATION CYCLE
Analog Input Buffer
+ RINT CINT
SWI
FIGURE 3-2:
SWI +IN SWRI- SWRI+
SYSTEM ZERO PHASE
Analog Input Buffer
+ CSZ SWIZ SWZ RINT CINT
+IN SWRI- SWRI+
CSZ SWIZ SWZ SWZ
SWZ
Integrator
SWZ SWRI+ SWRI-
SWZ
Integrator
Analog Common
SWI - IN SW1
Switch Open Switch Closed
3.2.2
ANALOG INPUT SIGNAL INTEGRATION
The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; - 1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. See Figure 2-3
FIGURE 3-3:
INPUT SIGNAL INTEGRATION PHASE
Analog Input Buffer
+ RINT CINT
SWRI- SWRI+
CSZ SWIZ SWZ
SWZ SWRI+ SWRI-
SWZ
Integrator
SWZ
SWZ SWRI+ SWRI-
Integrator
Analog Common
SWI - IN
SW1
Switch Open Switch Closed
.
2002 Microchip Technology Inc.
-
+
REF IN
+
SWR
-
CREF
Comparator To Digital Section
Analog Common
SWI - IN SW1
Switch Open Switch Closed
DS21460B-page 7
-
-
+
REF IN
+
+IN
-
SWI
-
+
REF IN
+
-
SWR
CREF
Comparator
Analog Common
SWRI+ SWRI-
To Digital Section
- IN
SWI
SW1
Switch Open Switch Closed
3.2.4
INTEGRATOR OUTPUT ZERO
This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5).
FIGURE 3-5:
INTEGRATOR OUTPUT ZERO PHASE
Analog Input Buffer
+ RINT CINT CSZ SWIZ SWZ
SWI + IN SWRI- SWRI+
SWR
CREF
+ +
REF IN
SWR
CREF
Comparator To Digital Section
Comparator To Digital Section
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TC7135
4.0
4.1
ANALOG SECTION FUNCTIONAL DESCRIPTION
Differential Inputs
FIGURE 4-1:
USING AN EXTERNAL REFERENCE
V+
The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.
V+
TC7135
REF IN ANALOG COMMON
10k
MCP1525 2.5 VREF 1F
10k
Analog Ground
4.2
Analog Common Input
ANALOG COMMON is used as the -INPUT return during auto zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, -INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON.
4.3
Reference Voltage Input
The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1.
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TC7135
5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION
The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs.
FIGURE 5-1:
DIGITAL SECTION FUNCTIONAL DIAGRAM
Polarity
D5 MSB
D4 Digit
D3 Drive Multiplexer
D2 Signal
D1 LSB 13 B1 14 B2 Data 15 B4 Output 16 B8
From Analog Section Polarity FF Zero Cross Detect Latch Latch Latch Latch
Latch
Counters
Control Logic 24 DGND 22 Clock In 25 RUN/ HOLD 27 28 26 STROBE 21 Busy
Overrange Underrange
2002 Microchip Technology Inc.
DS21460B-page 9
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TC7135
FIGURE 5-2: TIMING DIAGRAMS FOR OUTPUTS
5.2
STROBE Output
Integrator Output
Signal System Integrate Reference 10,000 Zero Integrate 10,001 Counts 20,001 Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts
During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D 1, D2, D3, D5) (see Figure 5-3). D 5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D 4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D 1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784.
Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan
D5 D4 D3 D2 D1 * First D5 of System Zero and Reference Integrate One Count Longer Signal Integrate * D4 D3 D2 Reference Integrate
100 Counts STROBE Auto Zero Digit Scan for Overrange * D5
FIGURE 5-3:
STROBE SIGNAL LOW FIVE TIMES PER CONVERSION
TC835 Outputs Busy
*
End of Conversion
D1
B1-B8
D5 (MSD) Data
D4 Data
D3 Data
D2 Data
D1 (LSD) Data
D5 Data
5.1
RUN/HOLD Input
STROBE 200 Counts
Note Absence of STROBE 200 Counts
When left open, this pin assumes a logic "1" level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic "0," the measurement cycle in progress will be completed, data held and displayed, as long as the logic "0" condition exists. A positive pulse (>300nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001count auto zero phase. At the end of this phase the busy signal goes high.
D5
201 Counts 200 Counts 200 Counts 200 Counts 200 Counts
D4
D3
D2
D1
*Delay between Busy going Low and First STROBE pulse is dependent on Analog Input.
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TC7135
5.3 BUSY Output
At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic "0" state after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto zero cycle.
5.4
OVERRANGE Output
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic "1." The overrange output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800 counts), the underrange register bit is set at the end of BUSY. The bit is set low at the next signal integration phase.
5.6
POLARITY Output
A positive input is registered by a logic "1" polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications.
5.7
Digit Drive Outputs
Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2, and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic "0" state.
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TC7135
6.0
6.1
6.1.1
TYPICAL APPLICATIONS
Component Value Selection
INTEGRATING RESISTOR
The dielectric absorption of the reference and auto zero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery.
The integrating resistor RINT is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor, CINT. Both the buffer amplifier and the integrator have a class A output stage, with 100A of quiescent current. A 20A drive current gives negligible linearity errors. Values of 5A to 40A give good results. The exact value of an integrating resistor for a 20A current is easily calculated.
6.1.4
REFERENCE VOLTAGE
The analog input required to generate a full scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made.
EQUATION 6-1:
RINT = Full scale voltage 20A
6.2
6.2.1
Conversion Timing
LINE FREQUENCY REJECTION
6.1.2
INTEGRATING CAPACITOR (C INT)
The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For 5V supplies and ANALOG COMMON tied to supply ground, a 3.5V to 4V full scale integrator swing is adequate. A 0.10F to 0.47F is recommended. In general, the value of CINT is given by:
A signal integration period at a multiple of the 60Hz line frequency will maximize 60Hz "line noise" rejection. A 100kHz clock frequency will reject 50Hz, 60Hz and 400Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2).
TABLE 6-1:
CONVERSION RATE VS. CLOCK FREQUENCY
Conversion Rate (Conv./Sec.) 2.5 3 5 7.5 10 20 30
Oscillator Frequency (kHz) 100 120 200 300 400 800 1200
EQUATION 6-2:
CINT = [10,000 x clock period] x IINT Integrator output voltage swing (10,000) (clock period) (20A) Integrator output voltage swing A very important characteristic of the integrating capacitor C INT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.
=
6.1.3
AUTO ZERO AND REFERENCE CAPACITORS
The size of the auto zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible.
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TC7135
TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY
Line Frequency Rejection (Hz) 60
Oscillator Frequency (kHz) 300 200 150 120 100 40 33-1/3 250 166-2/3 125 100 100
ator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0, Typical Applications. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR.
50
6.4
50, 60,400
Zero Crossing Flip Flop
The conversion rate is easily calculated:
EQUATION 6-3:
Reading 1/sec = Clock Frequency (Hz) 4000
6.3
High Speed Operation
The maximum conversion rate of most dual slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3sec delay, at a clock frequency of 160 kHz (6sec period), Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50V input, 1 to 2 with 150V, 2 to 3 at 250V, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count, or counts, caused by comparator delay, will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the compar-
The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result.
6.5
Generating a Negative Supply
A negative voltage can be generated from the positive supply by using a TC7660 (see Figure 6-1).
FIGURE 6-1:
NEGATIVE SUPPLY VOLTAGE GENERATOR
+5V 11
V+
8 1 (-5V) 10F + 4 + 10F 2 3 5
TC7135
V-
TC7660
24
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TC7135
FIGURE 6-2: 4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON ANODE LED DISPLAY
+5V
20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33F 1F 5 AZ IN POL 23 4.7k b 1F c 7 7 X7 5 RBI DM7447A 16 +5V 9-15 7 7
100k 200kHz 100k + Analog Input -
6 BUFF OUT 22 F IN 10
TC7135
CREF- 7 CREF+ 8 16 B8 15 B4 14 B2 B1 13 V+ 11 V+
Blank MSD On Zero 6 D 2 C 1 B 7 A
+INPUT -INPUT
1F
9
3 ANALOG COMMON REF V - IN 12 -5V 100k
MCP1525 1F
FIGURE 6-3:
R2
RC OSCILLATOR CIRCUIT
R1 C FO
FIGURE 6-4:
COMPARATOR CLOCK CIRCUITS
+5V
16k 56k
1k
Gates are 74C04
1. F O = 1 2C(0.41 RP + 0.7 R1) , RP = R1 R2 R1 + R2
16k 0.22F
a. If R1 = R 2 = R 1, F 0.55/RC b. If R2 >> R 1, F 0.45/R1C c. If R2 << R 1, F 0.72/R 1C 2. Examples: a. F = 120kHz, C = 420pF R1 = R 2 10.9 k b. F = 120kHz, C = 420pF, R2 = 50k R1 = 8.93k c. F = 120 kHz, C = 220 pF, R2 = 5k R1 = 27.3k
R2 100k C1 0.1F
R2 100k
+5V
(c)
DS21460B-page 14
-
3
+
2
LM311 4 1
2002 Microchip Technology Inc.
-
3
+ 4 6
2
8 7 1
VOUT
LM311
30k 390pF
R4 2k
C2 10pF 7 R3 50k VOUT
TC7135
FIGURE 6-5:
+5V
4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY
+5V SET VREF = 1V -5V 1 V-
MCP1525 1F
100 k
27 REF IN OR 26 3 ANALOG STROBE GND 2 25
TC7135
UR
28 150 47 k 10 150 11 12 9 8 7
Analog GND 0.33F
100 k + SIG IN -
4 INT RUN/HOLD OUT 24 5 DGND AZ IN 23 6 BUFF POLARITY OUT 100 k 7 22 CREF+ CLK IN 1F 21 8C REFBUSY 20 9 -INPUT (LSD) D1 0.1 10 19 +INPUT D2 F 11 18 D3 +5V V+ 12 17 D4 D5 (MSD) 1F 13 16 B1 (LSB) (MSB) B8 14 B4 15 B2
13 MC14513 6 14 15 16 17 18 5 4 3 2 1 +5V
FOSC = 200kHz
2002 Microchip Technology Inc.
DS21460B-page 15
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TC7135
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
7.2
Taping Forms
Component Taping Orientation for 28-Pin PLCC Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
28-Pin PLCC
24 mm
16 mm
750
13 in
Component Taping Orientation for 64-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
64-Pin PQFP
32 mm
24 mm
250
13 in
NOTE: Drawing does not represent total number of pins.
(c)
DS21460B-page 16
2002 Microchip Technology Inc.
TC7135
7.3 Package Dimensions
28-Pin PDIP (Wide)
PIN 1
.555 (14.10) .530 (13.46)
1.465 (37.21) 1.435 (36.45)
.610 (15.49) .590 (14.99)
.200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92)
.040 (1.02) .020 (0.51)
.015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50)
3MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.022 (0.56) .015 (0.38) Dimensions: inches (mm)
28-Pin PLCC
PIN 1
.495 (12.58) .485 (12.32) .456 (11.58) .450 (11.43)
.050 (1.27) TYP.
.021 (0.53) .013 (0.33) .032 (0.81) .026 (0.66) .430 (10.92) .390 (9.91)
.456 (11.58) .450 (11.43) .495 (12.58) .485 (12.32) .180 (4.57) .165 (4.19)
.020 (0.51) MIN. .120 (3.05) .090 (2.29)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21460B-page 17
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TC7135
7.3 Packaging Dimensions (Continued)
64-Pin PQFP
PIN 1 .018 (0.45) .012 (0.30) .009 (0.23) .005 (0.13)
7 MAX.
.041 (1.03) .031 (0.78)
.555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95)
.031 (0.80) TYP.
.555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95)
.010 (0.25) TYP. .120 (3.05) .100 (2.55) .130 (3.30) MAX.
Dimensions: inches (mm)
(c)
DS21460B-page 18
2002 Microchip Technology Inc.
TC7135
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21460B-page 19
TC7135
NOTES:
DS21460B-page 20
2002 Microchip Technology Inc.
TC7135
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21460B-page 21
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Germany
Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Hong Kong SAR
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
04/20/02
(c)
DS21460B-page 22
2002 Microchip Technology Inc.
*B06412SD*

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