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| S6B33B0A 144 RGB Segment & 177 Common Driver For 65,536 Color STN LCD August. 12. 2002 Ver. 1.1 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate ( board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light. 2. 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 S6B33B0A Specification Revision History Version 0.0 0.1 0.2 0.3 1.0 1.1 Content Original Neglect the more past version than version 0.0 Add the schottky barrier diode connection between VEE and VSS at the system application diagram Append the schottky barrier diode specification Append the addressing condition for the 256 color and 4.096 color mode Append the power on/off sequences. Definition of TBD items Modify REG_OUT range: 1.8 to 1.9V -> 1.8 to 2.2V Add the DC spec for VIN2, DC2IN, VIN45. Date Mar. 2002 May. 2002 June. 2002 June. 2002 July. 2002 Aug. 2002 2 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD CONTENTS INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 BLOCK DIAGRAM ......................................................................................................................................... 2 PAD CONFIGURATION ................................................................................................................................. 3 PIN CONFIGURATION................................................................................................................................... 5 PAD CENTER COORDINATES ...................................................................................................................... 6 PIN DESCRIPTION .......................................................................................................................................11 PIN DESCRIPTION .......................................................................................................................................12 FUNCTIONAL DESCRIPTION .......................................................................................................................15 MPU INTERFACE ..................................................................................................................................15 DISPLAY DATA RAM .............................................................................................................................19 INSTRUCTION DESCRIPTION ......................................................................................................................28 INSTRUCTION PARAMETER ........................................................................................................................56 POWER ON/OFF SEQENCE .........................................................................................................................59 SPECIFICATIONS .........................................................................................................................................61 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................61 OPERATING VOLTAGE .........................................................................................................................61 DC CHARACTERISTICS (1) ...................................................................................................................62 DC CHARACTERISTICS (2) ...................................................................................................................63 DC CHARACTERISTICS (3) ...................................................................................................................64 DC CHARACTERISTICS (4) ...................................................................................................................65 DC CHARACTERISTICS (5) ...................................................................................................................66 AC CHARACTERISTICS .........................................................................................................................67 SYSTEM APPLICATION DIAGRAM ...............................................................................................................71 3 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD INTRODUCTION S6B33B0A is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. With onchip CR oscillator circuit, the display-timing signal is generated without being sent from MPU. Also, it is capable of using 8bit/16bit data bus alternatively and operating with 68/80-series MPU in asynchronous. Due to the LCD driving signal (144 RGB X 177 output) corresponding to the display data and the internal bit-map display RAM of 144 x176 x16-bit, S6B33B0A is capable of operating max. 144 RGB x 177 dot LCD panels in low-power consumption. Being the segment RGB 3-output, one pixel is 16-bit data and S6B33B0A can max display 65,536 color. FEATURES Driver Output - - - - 144 RGB x 177 Gray Scale Function 65,536 color display of R: 32 gray scale, G: 64 gray scale, B: 32 gray scale 4,096 color display of R: 16 gray scale, G: 16 gray scale, B: 16 gray scale 256 color display of R: 8 gray scale, G: 8 gray scale, B: 4 gray scale On-chip Display Data RAM - - Capacity: 144 x 16 x 176 = 405.504k bits Burst RAM write function Display Mode - - - - - - Normal display mode: Entire duty displaying Partial display mode: Partial duty displaying Standby mode: Internal display clocks off Area scroll mode: Particular area scrolling Microprocessor Interface 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series 3/4 Pin SPI (only write operation) On-chip Low Power Analog Circuit - - - On-chip CR oscillator (Internal cap. & external resistor), external clock available Voltage converter / Voltage regulator / Voltage follower On-chip electronic contrast control (256 steps) Operating Voltage Range - - - - VDD : 1.8 to 3.3 [V] (without Internal Regulator), 2.4 to 3.3 [V] (With internal Regulator) VIN1: 2.4 to 3.6 [V] Display operating voltage(V1): 2.0 to 4.0 V LCD Operating Voltage Range : Max. 20 V Low Power Consumption - 650 A Typ. (Refer to DC CHARACTERISTICS (2)) Package Type - COG (Output Pad Pitch Min. 40 m) 1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 BLOCK DIAGRAM VDD3, VDD3R VDD,VDDO VSS VCC V1IN VMIN V0IN VEE VIN45 VOUT45 C11P C11M C12M C12P VIN1 VIN2 V1OUT V1T INTRS VMOUT DC2OUT DC2IN C21P C21M C22P C22M C23P C23M C24P C24M VRN C31P C31M VRP VSS,VSSA,VSSB,VSSO SEGA0 SEGA143 SEGB0 - - SEGB143 COM0 - - - COM176 SEGC0 SEGC143 CDIR SEG Driving Circuit COM Driving Circuit Oscillator Circuit OSC1 OSC2 OSC3 OSC4 OSC5 432 Decoder Circuit 2304 176 CL FR PM Voltage Converter/ Voltage Regulator/ Voltage Follower Display data RAM 176 X 2304 LCD System Control Circuit I/O Buffer X - Address Control Circuit Y - Address Control Circuit Bus Holder MPU System Control Circuit MPU INTERFACE CS1B CS2 D/I(RS) RDB WRB MPU[1:0] PS RSTB DB<15:0> REG_OUT REG_ENB Power Regulator Circuit Instruction Decoder Status Figure 1. Block Diagram 2 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD PAD CONFIGURATION 777 778 279 278 ....................... .. Y X (0,0) S6B33B0 836 1 TOM ............ . ALIGN KEY 220 219 PAD Figure 2. S6B33B0A Chip Pad Configuration Table 1. S6B33B0A Pad Dimensions Item Chip size (with S/L 120m) Pad pitch 1 to 219 220 to 278, 279 to 777, 778 to 836 1 to 219 Bumped pad size Bumped pad height 220 to 278, , 778 to 836 279 to 777 All pad 70 150 25 17 Pad No. Size X 20644 90 40 70 25 150 m Y 2870 Unit 3 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 COG Align Key Coordinate 30m 30m 30m 30m 30m 30m 30m 30m 30m 30m 42m ILB Align Key Coordinate 108m 108m 42m (8618,-855) (8670,820) 108 m 42m 60m (-8100,780) 108m 42 m (-8270,-928) Figure 3. COG Align Key Coordinate Figure 4. ILB Align Key Coordinate TOM(TEG On Main chip) Coordinate 220um ( -8050 , 540 ) 220um (- 7780 , 540 ) COF Align Key Coordinate 70um (-10085,1268) 580u m 50um 70um 70um (10155,1268) 20um (- 8270 , - 40) ( -8000 , -40) (-7780 , - 90) (-10155,1198) (10085,1198) (- 8000 , -670 ) 4 580u m S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD PIN CONFIGURATION COM54 COM55 COM56 COM0 COM1 COM2 : : : : : : : : : : : : COM57 COM58 COM59 : : : COM84 COM85 COM86 SEGC0 SEGB0 SEGA0 SEGC1 SEGB1 SEGA1 SEGC2 SEGB2 SEGA2 : : : : : : : : : : : : : : : : : : : : : : : : : : SEGC141 SEGB141 SEGA141 SEGC142 SEGB142 SEGA142 SEGC143 SEGB143 SEGA143 COM176 COM175 COM174 : : : COM146 COM145 COM144 COM143 COM142 COM141 : : : : : : : : : : : : COM89 COM88 COM87 VOIN C31M C31P VRP VCC C21M VEE VRM C24M C24P C23M C23P C22M C22P C21M C21P DC2IN DC2OUT VMIN VMOUT V1T V1OUT V1IN C12M C12P C11M C11P VOUT45 VIN45 VIN2 VIN1(VIN1A) VDD1(VDD3=VDD3R) REG_OUT VDD(VDDO) OSC1 OSC2 OSC3 OSC4 OSC5 INTRS REG_ENB VSS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RDB WRB RS RSTB PM FR CL TEST0 TEST1 TEST2 CS2 CS1B CDIR MPU0 MPU1 PS VOIN Figure 5. S6B33B0A Chip Pin Configuration S6B33B0 (Top View) 5 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 PAD CENTER COORDINAT ES Table 2. Pad Center Coordinates [Unit: m] No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X -9808 -9718 -9628 -9538 -9448 -9358 -9268 -9178 -9088 -8998 -8908 -8818 -8728 -8638 -8548 -8458 -8368 -8278 -8188 -8098 -8008 -7918 -7828 -7738 -7648 -7558 -7468 -7378 -7288 -7198 -7108 -7018 -6928 -6838 -6748 -6658 -6568 -6478 -6388 -6298 -6208 -6118 -6028 -5938 -5848 -5758 -5668 -5578 -5488 -5398 Y -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 NAME DUMMY<0> DUMMY<1> V0IN V0IN V0IN V0IN VSS PS VDD3 MPU1 VSS MPU0 VDD3 CDIR VSS CS1B CS2 TEST2 TEST1 TEST0 VDD3 CL FR PM RSTB RS VSS WRB RDB VDD3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 VSS VSS VSS VSS No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 X -5308 -5218 -5128 -5038 -4948 -4858 -4768 -4678 -4588 -4498 -4408 -4318 -4228 -4138 -4048 -3958 -3868 -3778 -3688 -3598 -3508 -3418 -3328 -3238 -3148 -3058 -2968 -2878 -2788 -2698 -2608 -2518 -2428 -2338 -2248 -2158 -2068 -1978 -1888 -1798 -1708 -1618 -1528 -1438 -1348 -1258 -1168 -1078 -988 -898 Y -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 NAME VSS VSS VSS VSS VSSA VSSA VSSA VSSA VSSO VSSO VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB REG_ENB VDD3 INTRS OSC5 VSS OSC4 OSC3 OSC2 OSC1 VDDO VDDO VDD VDD VDD VDD VDD VDD REG_OUT REG_OUT REG_OUT REG_OUT REG_OUT REG_OUT VDD3R VDD3R VDD3R VDD3R VDD3R VDD3R VDD3 No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 X -808 -718 -628 -538 -448 -358 -268 -178 -88 2 92 182 272 362 452 542 632 722 812 902 992 1082 1172 1262 1352 1442 1532 1622 1712 1802 1892 1982 2072 2162 2252 2342 2432 2522 2612 2702 2792 2882 2972 3062 3152 3242 3332 3422 3512 3602 Y -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 NAME VDD3 VDD3 VDD3 VDD3 VDD3 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1 VIN1A VIN1A VIN1A VIN1A VIN2 VIN2 VIN2 VIN2 VIN2 VIN45 VIN45 VIN45 VOUT45 VOUT45 VOUT45 C11P C11P C11P C11M C11M C11M C12P C12P C12P C12M C12M C12M V1IN V1IN V1IN V1OUT V1OUT V1OUT 6 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: m] No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 X 3692 3782 3872 3962 4052 4142 4232 4322 4412 4502 4592 4682 4772 4862 4952 5042 5132 5222 5312 5402 5492 5582 5672 5762 5852 5942 6032 6122 6212 6302 6392 6482 6572 6662 6752 6842 6932 7022 7112 7202 7292 7382 7472 7562 7652 7742 7832 7922 8012 8102 Y -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 NAME V1T V1T VMOUT VMOUT VMOUT VMOUT VMIN VMIN VMIN VMIN DC2OUT DC2OUT DC2OUT DC2IN DC2IN DC2IN C21P C21P C21P C21M C21M C21M C22P C22P C22P C22M C22M C22M C23P C23P C23P C23M C23M C23M C24P C24P C24P C24M C24M C24M VRN VRN VRN VEE VEE VEE VEES VEES DUMMY<2> DUMMY<3> No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 X 8192 8282 8372 8462 8552 8642 8732 8822 8912 9002 9092 9182 9272 9362 9452 9542 9632 9722 9812 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 Y -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1320 -1240 -1200 -1160 -1120 -1080 -1040 -1000 -960 -920 -880 -840 -800 -760 -720 -680 -640 -600 -560 -520 -480 -440 -400 -360 -320 -280 -240 -200 -160 -120 -80 -40 NAME VCC VCC VCC VRP VRP VRP C31P C31P C31P C31M C31M C31M DUMMY<4> VSS V0IN V0IN V0IN DUMMY<5> DUMMY<6> DUMMY<7> COM<0> COM<1> COM<2> COM<3> COM<4> COM<5> COM<6> COM<7> COM<8> COM<9> COM<10> COM<11> COM<12> COM<13> COM<14> COM<15> COM<16> COM<17> COM<18> COM<19> COM<20> COM<21> COM<22> COM<23> COM<24> COM<25> COM<26> COM<27> COM<28> COM<29> No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 X 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 10120 9960 9920 9880 9840 9800 9760 9720 9680 9640 9600 9560 9520 9480 9440 9400 9360 9320 9280 9240 9200 9160 9120 Y 0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640 680 720 760 800 840 880 920 960 1000 1040 1080 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME COM<30> COM<31> COM<32> COM<33> COM<34> COM<35> COM<36> COM<37> COM<38> COM<39> COM<40> COM<41> COM<42> COM<43> COM<44> COM<45> COM<46> COM<47> COM<48> COM<49> COM<50> COM<51> COM<52> COM<53> COM<54> COM<55> COM<56> DUMMY<8> DUMMY<9> COM<57> COM<58> COM<59> COM<60> COM<61> COM<62> COM<63> COM<64> COM<65> COM<66> COM<67> COM<68> COM<69> COM<70> COM<71> COM<72> COM<73> COM<74> COM<75> COM<76> COM<77> 7 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Table 2. Pad Center Coordinates (Continued) [Unit: m] No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 X 9080 9040 9000 8960 8920 8880 8840 8800 8760 8720 8680 8640 8600 8560 8520 8480 8440 8400 8360 8320 8280 8240 8200 8160 8120 8080 8040 8000 7960 7920 7880 7840 7800 7760 7720 7680 7640 7600 7560 7520 7480 7440 7400 7360 7320 7280 7240 7200 7160 7120 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME COM<78> COM<79> COM<80> COM<81> COM<82> COM<83> COM<84> COM<85> COM<86> DUMMY<10> SEGC<0> SEGB<0> SEGA<0> SEGC<1> SEGB<1> SEGA<1> SEGC<2> SEGB<2> SEGA<2> SEGC<3> SEGB<3> SEGA<3> SEGC<4> SEGB<4> SEGA<4> SEGC<5> SEGB<5> SEGA<5> SEGC<6> SEGB<6> SEGA<6> SEGC<7> SEGB<7> SEGA<7> SEGC<8> SEGB<8> SEGA<8> SEGC<9> SEGB<9> SEGA<9> SEGC<10> SEGB<10> SEGA<10> SEGC<11> SEGB<11> SEGA<11> SEGC<12> SEGB<12> SEGA<12> SEGC<13> No 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 X 7080 7040 7000 6960 6920 6880 6840 6800 6760 6720 6680 6640 6600 6560 6520 6480 6440 6400 6360 6320 6280 6240 6200 6160 6120 6080 6040 6000 5960 5920 5880 5840 5800 5760 5720 5680 5640 5600 5560 5520 5480 5440 5400 5360 5320 5280 5240 5200 5160 5120 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGB<13> SEGA<13> SEGC<14> SEGB<14> SEGA<14> SEGC<15> SEGB<15> SEGA<15> SEGC<16> SEGB<16> SEGA<16> SEGC<17> SEGB<17> SEGA<17> SEGC<18> SEGB<18> SEGA<18> SEGC<19> SEGB<19> SEGA<19> SEGC<20> SEGB<20> SEGA<20> SEGC<21> SEGB<21> SEGA<21> SEGC<22> SEGB<22> SEGA<22> SEGC<23> SEGB<23> SEGA<23> SEGC<24> SEGB<24> SEGA<24> SEGC<25> SEGB<25> SEGA<25> SEGC<26> SEGB<26> SEGA<26> SEGC<27> SEGB<27> SEGA<27> SEGC<28> SEGB<28> SEGA<28> SEGC<29> SEGB<29> SEGA<29> No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 X 5080 5040 5000 4960 4920 4880 4840 4800 4760 4720 4680 4640 4600 4560 4520 4480 4440 4400 4360 4320 4280 4240 4200 4160 4120 4080 4040 4000 3960 3920 3880 3840 3800 3760 3720 3680 3640 3600 3560 3520 3480 3440 3400 3360 3320 3280 3240 3200 3160 3120 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGC<30> SEGB<30> SEGA<30> SEGC<31> SEGB<31> SEGA<31> SEGC<32> SEGB<32> SEGA<32> SEGC<33> SEGB<33> SEGA<33> SEGC<34> SEGB<34> SEGA<34> SEGC<35> SEGB<35> SEGA<35> SEGC<36> SEGB<36> SEGA<36> SEGC<37> SEGB<37> SEGA<37> SEGC<38> SEGB<38> SEGA<38> SEGC<39> SEGB<39> SEGA<39> SEGC<40> SEGB<40> SEGA<40> SEGC<41> SEGB<41> SEGA<41> SEGC<42> SEGB<42> SEGA<42> SEGC<43> SEGB<43> SEGA<43> SEGC<44> SEGB<44> SEGA<44> SEGC<45> SEGB<45> SEGA<45> SEGC<46> SEGB<46> 8 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: m] No 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 X 3080 3040 3000 2960 2920 2880 2840 2800 2760 2720 2680 2640 2600 2560 2520 2480 2440 2400 2360 2320 2280 2240 2200 2160 2120 2080 2040 2000 1960 1920 1880 1840 1800 1760 1720 1680 1640 1600 1560 1520 1480 1440 1400 1360 1320 1280 1240 1200 1160 1120 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGA<46> SEGC<47> SEGB<47> SEGA<47> SEGC<48> SEGB<48> SEGA<48> SEGC<49> SEGB<49> SEGA<49> SEGC<50> SEGB<50> SEGA<50> SEGC<51> SEGB<51> SEGA<51> SEGC<52> SEGB<52> SEGA<52> SEGC<53> SEGB<53> SEGA<53> SEGC<54> SEGB<54> SEGA<54> SEGC<55> SEGB<55> SEGA<55> SEGC<56> SEGB<56> SEGA<56> SEGC<57> SEGB<57> SEGA<57> SEGC<58> SEGB<58> SEGA<58> SEGC<59> SEGB<59> SEGA<59> SEGC<60> SEGB<60> SEGA<60> SEGC<61> SEGB<61> SEGA<61> SEGC<62> SEGB<62> SEGA<62> SEGC<63> No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 X 1080 1040 1000 960 920 880 840 800 760 720 680 640 600 560 520 480 440 400 360 320 280 240 200 160 120 80 40 0 -40 -80 -120 -160 -200 -240 -280 -320 -360 -400 -440 -480 -520 -560 -600 -640 -680 -720 -760 -800 -840 -880 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGB<63> SEGA<63> SEGC<64> SEGB<64> SEGA<64> SEGC<65> SEGB<65> SEGA<65> SEGC<66> SEGB<66> SEGA<66> SEGC<67> SEGB<67> SEGA<67> SEGC<68> SEGB<68> SEGA<68> SEGC<69> SEGB<69> SEGA<69> SEGC<70> SEGB<70> SEGA<70> SEGC<71> SEGB<71> SEGA<71> SEGC<72> SEGB<72> SEGA<72> SEGC<73> SEGB<73> SEGA<73> SEGC<74> SEGB<74> SEGA<74> SEGC<75> SEGB<75> SEGA<75> SEGC<76> SEGB<76> SEGA<76> SEGC<77> SEGB<77> SEGA<77> SEGC<78> SEGB<78> SEGA<78> SEGC<79> SEGB<79> SEGA<79> No 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 X -920 -960 -1000 -1040 -1080 -1120 -1160 -1200 -1240 -1280 -1320 -1360 -1400 -1440 -1480 -1520 -1560 -1600 -1640 -1680 -1720 -1760 -1800 -1840 -1880 -1920 -1960 -2000 -2040 -2080 -2120 -2160 -2200 -2240 -2280 -2320 -2360 -2400 -2440 -2480 -2520 -2560 -2600 -2640 -2680 -2720 -2760 -2800 -2840 -2880 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGC<80> SEGB<80> SEGA<80> SEGC<81> SEGB<81> SEGA<81> SEGC<82> SEGB<82> SEGA<82> SEGC<83> SEGB<83> SEGA<83> SEGC<84> SEGB<84> SEGA<84> SEGC<85> SEGB<85> SEGA<85> SEGC<86> SEGB<86> SEGA<86> SEGC<87> SEGB<87> SEGA<87> SEGC<88> SEGB<88> SEGA<88> SEGC<89> SEGB<89> SEGA<89> SEGC<90> SEGB<90> SEGA<90> SEGC<91> SEGB<91> SEGA<91> SEGC<92> SEGB<92> SEGA<92> SEGC<93> SEGB<93> SEGA<93> SEGC<94> SEGB<94> SEGA<94> SEGC<95> SEGB<95> SEGA<95> SEGC<96> SEGB<96> 9 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Table 2. Pad Center Coordinates (Continued) [Unit: m] No 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 X -2920 -2960 -3000 -3040 -3080 -3120 -3160 -3200 -3240 -3280 -3320 -3360 -3400 -3440 -3480 -3520 -3560 -3600 -3640 -3680 -3720 -3760 -3800 -3840 -3880 -3920 -3960 -4000 -4040 -4080 -4120 -4160 -4200 -4240 -4280 -4320 -4360 -4400 -4440 -4480 -4520 -4560 -4600 -4640 -4680 -4720 -4760 -4800 -4840 -4880 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGA<96> SEGC<97> SEGB<97> SEGA<97> SEGC<98> SEGB<98> SEGA<98> SEGC<99> SEGB<99> SEGA<99> SEGC<100> SEGB<100> SEGA<100> SEGC<101> SEGB<101> SEGA<101> SEGC<102> SEGB<102> SEGA<102> SEGC<103> SEGB<103> SEGA<103> SEGC<104> SEGB<104> SEGA<104> SEGC<105> SEGB<105> SEGA<105> SEGC<106> SEGB<106> SEGA<106> SEGC<107> SEGB<107> SEGA<107> SEGC<108> SEGB<108> SEGA<108> SEGC<109> SEGB<109> SEGA<109> SEGC<110> SEGB<110> SEGA<110> SEGC<111> SEGB<111> SEGA<111> SEGC<112> SEGB<112> SEGA<112> SEGC<113> No 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 X -4920 -4960 -5000 -5040 -5080 -5120 -5160 -5200 -5240 -5280 -5320 -5360 -5400 -5440 -5480 -5520 -5560 -5600 -5640 -5680 -5720 -5760 -5800 -5840 -5880 -5920 -5960 -6000 -6040 -6080 -6120 -6160 -6200 -6240 -6280 -6320 -6360 -6400 -6440 -6480 -6520 -6560 -6600 -6640 -6680 -6720 -6760 -6800 -6840 -6880 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGB<113> SEGA<113> SEGC<114> SEGB<114> SEGA<114> SEGC<115> SEGB<115> SEGA<115> SEGC<116> SEGB<116> SEGA<116> SEGC<117> SEGB<117> SEGA<117> SEGC<118> SEGB<118> SEGA<118> SEGC<119> SEGB<119> SEGA<119> SEGC<120> SEGB<120> SEGA<120> SEGC<121> SEGB<121> SEGA<121> SEGC<122> SEGB<122> SEGA<122> SEGC<123> SEGB<123> SEGA<123> SEGC<124> SEGB<124> SEGA<124> SEGC<125> SEGB<125> SEGA<125> SEGC<126> SEGB<126> SEGA<126> SEGC<127> SEGB<127> SEGA<127> SEGC<128> SEGB<128> SEGA<128> SEGC<129> SEGB<129> SEGA<129> No 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 X -6920 -6960 -7000 -7040 -7080 -7120 -7160 -7200 -7240 -7280 -7320 -7360 -7400 -7440 -7480 -7520 -7560 -7600 -7640 -7680 -7720 -7760 -7800 -7840 -7880 -7920 -7960 -8000 -8040 -8080 -8120 -8160 -8200 -8240 -8280 -8320 -8360 -8400 -8440 -8480 -8520 -8560 -8600 -8640 -8680 -8720 -8760 -8800 -8840 -8880 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 NAME SEGC<130> SEGB<130> SEGA<130> SEGC<131> SEGB<131> SEGA<131> SEGC<132> SEGB<132> SEGA<132> SEGC<133> SEGB<133> SEGA<133> SEGC<134> SEGB<134> SEGA<134> SEGC<135> SEGB<135> SEGA<135> SEGC<136> SEGB<136> SEGA<136> SEGC<137> SEGB<137> SEGA<137> SEGC<138> SEGB<138> SEGA<138> SEGC<139> SEGB<139> SEGA<139> SEGC<140> SEGB<140> SEGA<140> SEGC<141> SEGB<141> SEGA<141> SEGC<142> SEGB<142> SEGA<142> SEGC<143> SEGB<143> SEGA<143> DUMMY<11> COM<176> COM<175> COM<174> COM<173> COM<172> COM<171> COM<170> 10 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: m] No 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 X -8920 -8960 -9000 -9040 -9080 -9120 -9160 -9200 -9240 -9280 -9320 -9360 -9400 -9440 -9480 -9520 -9560 -9600 -9640 -9680 -9720 -9760 -9800 -9840 -9880 -9920 -9960 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 Y 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1233 1080 1040 1000 960 920 880 840 800 760 720 680 640 600 560 520 480 440 400 360 320 280 240 200 NAME COM<169> COM<168> COM<167> COM<166> COM<165> COM<164> COM<163> COM<162> COM<161> COM<160> COM<159> COM<158> COM<157> COM<156> COM<155> COM<154> COM<153> COM<152> COM<151> COM<150> COM<149> COM<148> COM<147> COM<146> COM<145> COM<144> DUMMY<12> DUMMY<13> COM<143> COM<142> COM<141> COM<140> COM<139> COM<138> COM<137> COM<136> COM<135> COM<134> COM<133> COM<132> COM<131> COM<130> COM<129> COM<128> COM<127> COM<126> COM<125> COM<124> COM<123> COM<122> No 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 X -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 -10120 Y 160 120 80 40 0 -40 -80 -120 -160 -200 -240 -280 -320 -360 -400 -440 -480 -520 -560 -600 -640 -680 -720 -760 -800 -840 -880 -920 -960 -1000 -1040 -1080 -1120 -1160 -1200 -1240 NAME COM<121> COM<120> COM<119> COM<118> COM<117> COM<116> COM<115> COM<114> COM<113> COM<112> COM<111> COM<110> COM<109> COM<108> COM<107> COM<106> COM<105> COM<104> COM<103> COM<102> COM<101> COM<100> COM<99> COM<98> COM<97> COM<96> COM<95> COM<94> COM<93> COM<92> COM<91> COM<90> COM<89> COM<88> COM<87> DUMMY<14> 11 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 PIN DESCRIPTION Table 3. Power Supply Pins Name VDD3 VDD3R VDD VDDO VSS VSSO VSSA VSSB V1IN V1OUT VMIN VMOUT V0IN VCC VRP VEE VEES VRN VIN1 VIN1A VIN2 VOUT45 VIN45 C11P C11M C12P C12M V1T INTRS DC2IN DC2OUT C21P C21M C22P C22M C23P C23M C24P C24M C31P C31M I/O Supply Supply Supply Supply GND I O I O I I O I O I I O I O I I I O Main power supply Internal regulator power supply This pin is connected to VDD3. Regulated power supply input pin for internal digital and DDRAM block. This pin is connected to REG_OUT outside the chip with stabilization capacitor. When the internal regulator is not used, VDD1 should be tied to VDD directly. Internal oscillator power supply This pin is connected to VDD. Ground LCD segment high selected driving voltage input pin LCD segment high driving voltage output pin LCD common/segment non-selected driving voltage input pin LCD common/segment non-selected driving voltage output pin LCD segment low selected driving voltage input pin LCD common high selected driving voltage input pin LCD common high selected driving voltage output pin LCD common low selected driving voltage input pin The relationship between VCC, V1, VM, V0 and VEE: VCC > V1 > VM > V0(=VSS) > VEE (V1 - VM = VM - V0, VCC -VM = VM - VEE) LCD common low selected driving voltage output pin Power supply for 1'st booster circuit and VM amp Power supply for 2'nd booster circuit 1'st booster output pin Power supply for V1. Connect to VOUT45 or VIN1 External capacitor connection pins used for 1'st booster circuit Thermistor resistor connection pin External resister select pin for temperature compensation circuit - INTRS = L : External resistor mode, INTRS = H : Internal resistor mode Power supply for 2'nd booster. Connect to DC2OUT pin Power output pin for 2'nd booster input Description O External capacitor connection pins used for 2'nd booster circuit O External capacitor connection pins used for 3'rd booster circuit 12 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Table 4. MPU Interface Pins Name RSTB I/O I Description Reset input pin. When RSTB is "L", initialization is executed. MPU interface select pin PS H PS MPU[1:0] I H H H L L CS1B CS2 D/I (RS) I MPU[1] L L H H L H MPU[0] L H L H X X Description 8080-series 8bit interface 8080-series 16bit interface 6800-series 8bit interface 6800-series 16bit interface 3 pin SPI(Write only) 4 pin SPI(Write only) Chip select input pins Data / instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB15 may be high impedance. Data / Instruction select input pin - D/I = "H": DB0 to DB15 are display data - D/I = "L": DB0 to DB7 are instruction data Read / Write execution control pin PS MPU H MPU Type 6800-series WRB R/W Description ReadWRBite control input pin - R/W = "H": read - R/W = "L": write Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the WRB signal. I WRB (R/W) I H H L 8080-series WRB Read / Write execution control pin MPU[1] RDB (E) MPU type RDB Description Read / Write control input pin - R/W = "H": When E is "H", DB0 to DB15 are in an output status. - R/W = "L": The data on DB0 to DB15 are latched at the falling edge of the E signal. Read enable clock input pin When RDB is "L", DB0 to DB15 are in an output status. I H 6800series E L DB[15:8] DB[7]/SDI DB[6]/SCL DB[5:0] CDIR 8080series RDB I/O I -DB[15:0]: 16-bit bi-directional data bus. -SDI: Serial data input pin. The data is latched at the rising edge of SCL. -SCL: Serial clock input pin. Common direction select pin. 13 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Table 5. Oscillator and Power Regulator Pins Name OSC1 OSC2 OSC3 OSC4 I/O Description CR oscillator output pin When the internal CR oscillator is used, connect to OSC1, OSC3 through a resistor. OSC1 - OSC2: Using in normal display mode, partial display mode 0 OSC3 - OSC4: Using in partial display mode 1 When an external oscillator is used, OSC1 pin is connected to VDD or VSS. External clock input pin When an external input is used, it is input to this pin. But the internal oscillator is used, this pin is connected to VDD or VSS. Internal regulator enable/disable input pin - REG_ENB = "L" (tied to VSS) : enable internal regulator - REG_ENB = "H" (tied to VDD) : disable internal regulator Internal voltage regulator output pin The regulator output port from this pin is used as a power supplier for an internal digital block via VDD pins. O OSC5 I REG_ENB I REG_OUT O Table 6. Timing signal Pins for monitoring Name CL PM FR I/O O O O Shift clock output pin Field delimiter output pin Liquid crystal alternating current output pin Description Table 7. LCD driver output pins Name SEGA0 to 143 SEGB0 to 143 SEGC0 to143 COM0 to 176 I/O O O O O Description LCD driving segment output (Red or Blue) LCD driving segment output (Green) LCD driving segment output (Blue or Red) LCD common outputs Table 8. Test pins Name TEST[2:0] I/O I Description Don't use these pins. IC maker's test pins These pins must be tied to VDD. 14 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD FUNCTIONAL DESCRIPTION MPU INTERFACE Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B33B0A can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, D/I, RDB, and WRB inputs are disabled and DB0 to DB15 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel/Serial Interface The S6B33B0A has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table9. Table 9. Parallel / Serial Interface Mode. PS MPU[1] L H H L H CS1B CS2 6800-Series MPU 3-Pin SPI 4-Pin SPI CS1B CS2 MPU bus type 8080-Series MPU L CS1B CS2 Parallel Interface (PS="H") The 8-bit/16-bit bi-directional data bus is used in parallel interface. The type of MPU is selected by MPU[1] and the mode of data-bus is controlled by MPU[0] as shown in below. In accessing internal registers (D/I = "L"), only DB[7:0] are valid. Table 10. Microprocessor Selection for Parallel Interface MPU[1] L MPU[0] L H L H CS1B CS1B CS2 CS2 RDB RDB WRB WRB Data Bus DB[7:0] DB[15:0] DB[7:0] DB[15:0] MPU bus type 8080-series MPU H CS1B CS2 E R/W 6800-series MPU Table 11. Parallel Data Transfer 6800-series D/I RDB H H L L H H H H WRB H L H L RDB L H L H WRB H L H L Read display data Write display data Read out internal status register Write instruction data 8080-series Description 15 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 /CS1 CS2 D/I R/W E DB Command Write Data Write Status Read Data Read Figure 6. 6800-Series MPU Interface protocol (MPU[1]="H") /CS1 CS2 D/I /WR /RD DB Command Write Data Write Status Read Data Read Figure 7. 8080-Series MPU Interface Protocol (MPU[1]="L") 16 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Serial Interface(PS="L") Communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when PS is low. When using the serial interface, read operations are not allowed. When the chip select inputs are valid (CS1B = "L" & CS2 = "H"), the serial data is sent most significant bit first on the rising edge of a serial clock going into DB6 and processed as 8 bit parallel data on the eighth clock. Since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. And Invalid, the internal shift register and the counter are reset. The serial interface type is selected by setting PS as shown in Table12. Table 12. Microprocessor Selection for Serial Interface PS L MPU[1] L H CS1B CS1B CS1B CS2 CS2 CS2 D/I By S/W D/I Serial Data DB[7] Serial Clock DB[6] SPI Mode 3-Pin 4-Pin 3-Pin SPI Interface (PS = "L" & MPU[1] = "L") In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length is used to indicate whether serial data input is display or instruction data instead of D/I pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists of three bytes instruction. The first byte instruction enables the next instruction to be valid, and data of the second two bytes indicate that a specifi ed number of display data bytes(1 to 65536) are to be transmitted. Next two bytes after the display data string is handled as instruction data. For details, refer the Figure 8. Chip Select 1 2 /CS1 = L, CS2 = H 23 24 1 2 159 160 SCL(DB6) 3 bytes (1) 20 bytes(2) DDL_L DDL_L = 09H 10 pixel display data User's display data (Max. 50688(176x144) bytes) SDI(DB7) DDC DDL_H DDL_H = 00H DDL = 0009H(9D) Internal D/I (1) Set DDC(Display Data Command) and DDL(Display Data Length) Set DDC(3 Pin SPI mode only) : 1 1 1 1 1 1 0 0 (FCH) Set DDL(2 Bytes) : (1'st byte) D7 D6 D5 D4 D3 D2 D1 D0 (DDL_L) (2'nd byte) D7 D6 D5 D4 D3 D2 D1 D0 (DDL_H) (2) DDL Register Value Number of Display data : (DDL + 1) Pixel Data ((DDL+1) x 2 byte) Necessary clock pulse number : 8 x [(DDL+1) x 2] Figure 8. 3-Pin SPI Timing (D/I is not used) 17 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 4-Pin Serial Interface (PS="L" & MPU[1]="H") In 4-pin SPI interface mode, D/I pin is used for indicating whether serial data input is display or instruction data. Data is display data when D/I is high and instruction data when D/I is low. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Chip Select l /CS1=L, CS2=H DB2 SID (DB7) SCL(DB6) D/I DB7 DB6 DB5 DB4 DB3 DB1 DB0 DB7 DB6 Figure 9. 4-Pin Serial Interface Timing 18 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD DISPLAY DATA RAM The on-chip display data RAM of S6B33B0A is a static RAM that is stored the data for the display. It is a 2,304 x 176 structure. It is controlled by 2 addresses, X and Y. And, RAM area selection and automatic address count up functions are accomplished by the internal instructions. DDRAM Address Area Selection A part of DDRAM address area of S6B33B0A can be accessed by X and Y address area settings. After setting RAM area, the addresses become the start address. Y-address area X-address area Figure 10. DDRAM Address Area Table 13. X address Control DB7 Code P1 P2 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 X start address set(Initial Status = 00H) X end address set(Initial Status = AFH) Table 14. Y address Control DB7 Code P1 P2 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 0 DB0 1 Y start address set (Initial status = 00H) Y end address set (Initial status =8FH) 19 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 RAM Addressing Count up By selecting the X address and Y address area by the internal instructions, the address counts up from its start address to end address after data access operation. When one address is equal to the end address, it returns to the start address. At this time, the other address is increased by 1. Y address count mode (Y address = 00h to 8Fh, X address = 00h to AFh) Y-address 00h 01h 02h 03h 00h 1 145 289 433 01h 02h 03h 04h 05h 06h 07h 08h 2 3 4 5 6 7 8 9 8Fh 144 288 432 576 X-address AFh 25201 25344 Figure 11. Y address count mode X address count mode (Y address =00h to 8Fh, X address = 00h to AFh) Y-address 00h 01h 02h 03h 04h 05h 06h 07h 08h 00h 1 177 324 486 648 810 972 1134 1296 01h 2 02h 3 X-address 03h 4 8Fh 21222 AFh 176 352 528 704 880 1056 1232 1408 1584 25344 Figure 12. X address count mode 20 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD YA Address XA Address 00H 01H 02H 03H 04H 05H 06H 07H 08H - - - - - - - 89H 8AH 8BH 8CH 8DH 8EH 8FH 00H ------01H ------02H ------03H ------04H ------05H ------06H ------07H ------08H ------09H ------0AH ------0BH ------0CH ------0DH ------0EH ------0FH ----------A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH ----------------------------------------------------------------------------------------------------D15D14 D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Red Green Blue Figure 13. Display Data RAM Map 21 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Partial Display Mode The S6B33B0A realizes the partial display function with low duty driving for saving power consumption and showing the various display duties. It is set as display start/end line number. Area Scroll Function The S6B33B0A realizes the specific area scroll function. (1/176 duty case). E xample of Scrolling up 0 Fixed 15 lines 14 15 146 Lines 161 Fixed 15 lines 175 Example of Scrolling down 0 14 15 LCD Panel Fixed area Scroll area Display area 160 161 175 Figure 14. Area scroll examples (duty = 1/176, center scroll mode) 22 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Display Direction SDIR The SDIR flag of Driver Output Mode Set instruction selects the direction of segment display. SEGA0 SEGB0 SEGC0 Y=0 (D7~D0) (D7~D0) 1st 2nd SEGA1 SEGB1 SEGC1 Y=1 (D7~D0) (D7~D0) SEGA143 SEGB143 SEGC1 43 Y = 143 (D7~D0) (D7~D0) x=0 Figure 15. 8-bit data bus mode when SDIR = L SEGA0 SEGB0 SEGC0 Y=0 (D15~D0) SEGA1 SEGB1 SEGC1 Y=1 (D15~D0) SEGA143 SEGB143 SEGC143 Y = 143 (D15~D0) X=0 Figure 16. 16-bit data bus mode when SDIR = L SEGA0 SEGB0 SEGC0 Y = 143 (D7~D0) (D7~D0) 1st 2nd SEGA1 SEGB1 SEGC1 Y = 142 (D7~D0) (D7~D0) SEGA143 SEGB143 1 EGC143 S Y=0 (D7~D0) (D7~D0) x=0 Figure 17. 8-bit data bus mode when SDIR = H SEGA0 SEGB0 SEGC0 Y = 143 (D15~D0) SEGA1 SEGB1 SEGC1 Y = 142 (D15~D0) SEGA143 SEGB143 SEGC1 43 Y=0 (D15~D0) x=0 Figure 18. 16-bit data bus mode when SDIR = H 23 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 CDIR The direction of common scanning is selected by CDIR pin. COM 86 SEG144 COM176 COM 0 Driver COM87 128 Display Lines (DLN=00) COM 0 Line number 0 COM 1 Line number 127 Display Area COM 62 Line number 62 Display Area COM 62 Line number 66 COM 87 Line number 63 COM 87 Display Area COM 151 Line number 127 COM 152 Line number 65 Display Area Line number 0 144 Display Lines (DLN=01) COM 0 Line number 0 COM 0 Line number 143 Display Area COM 71 Line number 71 COM 71 Line number 72 COM 87 Display Area Line number 72 COM 87 Line number 71 Display Area COM 158 Line number 143 COM 158 Display Area Line number 0 160 Display Lines (DLN=10) COM 0 Line number 0 COM 2 Line number 159 Display Area COM 80 COM 87 Line number 80 COM 80 Line number 81 COM 87 Display Area Line number 81 Line number 80 Display Area COM 165 Line number 159 COM 167 Display Area Line number 0 176 Display Lines (DLN=11) COM 0 Line number 0 COM 1 Line number 175 Display Area Display Area COM 175 Line number 175 COM 176 Line number 0 24 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD SWP The SWP flag of Driver Output Mode Set instruction selects the swapping of segment display. SWP=1 SEGAi SEGBi * i = 0 to 143 SEGCi R control RAM DATA G control D0 D10 D9 D8 D7 D6 D5 B control D15 D14 D13 D12 D11 D4 D3 D2 D1 MPU I/F DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SWP=0 SEGAi SEGBi * i = 0 to 143 SEGCi R control RAM DATA G control D8 D7 D6 D5 D4 B control D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 MPU I/F DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SEGAi SWP = 0 SWP = 1 RED D15 ~ D11 BLUE D4~ D0 SEGBi GREEN D10~ D5 GREEN D10 ~ D5 SEGCi BLUE D4 ~ D0 RED D15 ~ D11 Color Assigned Bit Color Assigned Bit Figure 19. The relationship between SEG outputs and RGB color 25 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 On-Chip Regulator Configuration The output voltage of regulator circuit(REG_OUT) is ranging from 1.8V to 2.2V and nominal value is 1.8V. Value of external Capacitance VDD3 Item REG_ENB REG_ENB C1 Floating Value 1.0 to 4.7 Unit F REG_OUT C1 VDD /VDDO VDD3 VDD3 /VDD3R REG_OUT VDD /VDDO VDD3 VDD3 /VDD3R VDD3: 2.4 to 3.3V REG_OUT : 1.8V VDD3: 1.8 to 3.3V Figure 20. Regulator Application Oscillator Circuit When internal oscillator is used(EXT=0), the selection of oscillator resistor is determined by display mode. Normal display mode/ Partial display mode 0 : resistor1 between OSC1 and OSC2 Partial display mode 1 : resistor2 between OSC3 and OSC4 When external clock is used (EXT=1), clock frequency should be adjusted to display mode which is selected. Example of external oscillator application External clock VSS OSC5 OSC4 OSC3 OSC2 OSC1 Figure 21. External oscillator application 26 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Example of internal oscillator application VSS/VDD3 VSS/VDD3 R1 OSC5 OSC4 OSC3 OSC2 OSC1 OSC5 OSC4 R2 OSC3 OSC2 R1 OSC1 When partial display mode 1 is not used. When partial display mode 1 is used. Figure 22. Internal oscillator application Discharge Circuit Driving voltage level discharge time at standby ON. T[ms] Internal STB signal +VR V1 VM V+[mV] VSS V-[mV] -VR The relation between voltage level and discharge time from when "Standby ON" command is inputted. LEVEL +VR,V1,VM,-VR CONDITION +VR=12.0V, V1=3.0V, VM=1.5V, -VR=-9.0V at T=0 T[ms] 100 300 V+,V-[mV] < 50 < 20 27 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 INSTRUCTION DESCRIPTION Table 15. Instruction Table Instruction Name Non Operation Oscillation Mode Set Driver Output Mode Set DC-DC Select Bias Set DCDC Clock Division Set DCDC and AMP ON/OFF set Temperature Compensation Set Contrast Control(1) Contrast Control(2) Standby Mode OFF Standby Mode ON DDRAM Burst Mode OFF DDRAM Burst Mode ON Addressing Mode Set ROW Vector Mode Set N-line Inversion Set Entry Mode Set X-address Area Set Y-address Area Set RAM Skip Area Set Display OFF Display ON Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set Area Scroll Mode Set Scroll Start Line Set Set Display Data Length Display Data Write Display Data Read Status Read Test Mode1 Test Mode2 Test Mode3 Test Mode4 Test Mode5 Test Mode6 D/I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 0 0 0 0 0 0 0 W B RDB R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 0 0 1 1 1 1 1 1 DB15 DB7 ~D 8 B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DB6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 DB5 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 DB4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 DB3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 DB2 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1 DB1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 DB0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 Hex. Parameter 00 02 10 20 22 24 26 28 2A 2B 2C 2D 2E 2F 30 32 34 40 42 43 45 50 51 53 55 56 57 59 5A FC 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 1Byte 2Byte 2Byte 1Byte 1Byte 1Byte 1Byte 1Byte 4Byte 1Byte 1Byte - Display Data Write Display Data Read 0 * * * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Data Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 FF FE FD FB FA F9 *: Don't care Parameter: The number of parameter bytes that follows instruction data. 28 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Non Operation (00H) This instruction is Non operation. D/I WRB RDB DB7 0 0 1 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 Oscillation Mode Set (02H) Setting internal function mode. D/I WRB RDB 0 0 1 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 0 0 DB1 1 EXT DB0 0 OSC EXT: External clock selecting EXT = 0: Internal clock mode (Initial status) EXT = 1: External clock mode OSC: Internal oscillator ON/OFF OSC = 0: Internal oscillator OFF(Initial status) OSC = 1: Internal oscillator ON Driver Output Mode Set(10H) This instruction sets the display direction. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 0 DB5 0 DLN DB4 1 DB3 0 0 DB2 0 SDIR DB1 0 SWP DB0 0 0 DLN: Display Line number selecting DB5 DB4 Display Duty 0 0 1 1 0 1 0 1 1/128 1/144 1/160 1/176 SDIR: Segment direction This bit is for controlling the direction of segment driver. SDIR = 0 (Initial status) SWP: Swap segment output SEGAi and SEGCi This bit is for swapping the output of segment driver. SWP = 0 (Initial status) 29 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 DC-DC Select (20H) Selects DC-DC step-up of the common driver in normal and partial mode D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 0 DB5 1 0 DB4 0 0 DB3 0 DC(2) DB2 0 DB1 0 DC(1) DB0 0 DC(1) : 1'st DC-DC booster boosting step select for V1 generation in normal mode and partial mode 0. DC(2) : 1'st DC-DC booster boosting step select for V1 generation in partial mode 1. DC(2) : In partial mode 1 DB3 0 0 1 1 DB2 0 1 0 1 DC-DC step up X1.0 X1.5 X2.0 X2.0 DC(1) : In normal mode, partial mode 0 DB1 0 0 1 1 DB0 0 1 0 1 DC-DC step up X1.0 X1.5 X2.0 X2.0 30 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD DC-DC Select and power supply for V1 Op-Amp. Even if VIN45 is connected to VOUT45 or VIN1, a setup by software must be able to be performed. Power supply for V1 Op.Amp. is decided by Hardware setting and Software setting. The example of usage is shown below. Figure28. Example : Hardware Setting Software Setting : VIN45 connected to VOUT45 : Power supply for V1 Op.Amp. uses VIN1 ( not VOUT45). Hardware Setting VIN45 Software Setting VOUT45 + VSS C11+ C11C12+ C12EV_256 R1 Reference voltage generator & Temperature Compensation Control Circuit 1st Booster Circuit R1 V1 VIN1 V1 generation circuit Hardware setting : VIN45 connected to (1) VIN1 (when 1'st boosting is not used) (2) VOUT45 (when 1'st boosting is used) Software setting : DC-DC Select(20H) - DC(1), DC(2) Set value "00" Power supply for V1 Op.Amp. uses VIN1 directly. Set value "01" or "10" Power supply for V1 Op.Amp. uses VOUT45. 31 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Bias Set (22H) This instruction set up the value of bias in normal mode and in partial mode. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 0 0 1 0 0 0 0 1 Bias(2) 0 0 0 DB2 0 0 DB1 1 Bias(1) DB0 0 Bias(1): Bias value selecting in normal mode and partial mode0. Bias(2): Bias value selecting in partial mode1. Bias (2) : In partial mode 1 DB5 0 0 1 1 DB4 0 1 0 1 Bias(2) 1/4 1/5 1/6 1/7 2'nd boosting step x(-3) x(-4) x(-4) x(-5) Bias (1) : In normal mode, partial mode 0 DB1 0 0 1 1 DB0 0 1 0 1 Bias(1) 1/4 1/5 1/6 1/7 2'nd boosting step x(-3) x(-4) x(-4) x(-5) DCDC Clock Division Set(24H) This instruction sets the internal booster clock frequency. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 0 DB5 1 DIV(2) DB4 0 DB3 0 0 DB2 1 0 DB1 0 DIV(1) DB0 0 DIV(1) : DC-DC Charge Pump Division Ratio in Normal Mode Display and Partial Display Mode0 - DIV(1) = 10 (Initial status) DIV(2) : Division Ratio in Partial Display Mode1 - DIV(2) = 10 (Initial status) DB5 0 0 1 1 DB4 0 1 0 1 DIV(2) fPCK = fOSC/4 fPCK = fOSC/8 fPCK = fOSC/16 fPCK = fOSC/32 DB1 0 0 1 1 DB0 0 1 0 1 DIV(1) fPCK = fOSC/4 fPCK = fOSC/8 fPCK = fOSC/16 fPCK = fOSC/32 Note: fOSC = ( ROUNDUP (Duty/3) + dummy) x 4 x 8 x frame frequency 32 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD DC/DC and AMP ON/OFF Set (26H) This instruction set up the DC/DC and Op-amp in common start up setting. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 0 0 1 0 0 0 0 1 0 0 0 0 AMP DB2 1 DCDC3 DB1 1 DCDC2 DB0 0 DCDC1 AMP: Built-in OP-AMP ON/OFF. - AMP=0: OP-AMP OFF (Initial status) - AMP=1: OP-AMP ON DCDC1: Built-in 1'st Booster ON/OFF - DCDC1= 0: 1'st Booster OFF (Initial status) - DCDC1= 1: 1'st Booster ON DCDC2: Built-in 2'nd Booster ON/OFF - DCDC2= 0: 2'nd Booster OFF (Initial status) - DCDC2= 1: 2'nd Booster ON DCDC3: Built-in 3'rd Booster ON/OFF - DCDC3= 0: 3'rd Booster OFF (Initial status) - DCDC3= 1: 3'rd Booster ON Temperature Compensation Set (28H) This Instruction sets up the driving voltage slope for temperature compensation. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 0 0 1 0 0 0 0 1 0 0 0 1 0 DB2 0 0 DB1 0 TCS DB0 0 TCS: Temperature compensation slope set TCS = 00 : 0.00%/degC (Initial status) TCS = 01 : -0.05%/degC TCS = 10 : -0.10%/degC TCS = 11 : -0.15%degC Driving voltage 00: 0.00 %/degC 01: -0.05 %/degC 10: -0.10 %/degC 11: -0.15 %/degC 25degC Temperature 33 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Temperature Compensation If external temperature compensation is needed, circuit diagram is described as below. To use temperature compensation, two resistors and one thermistor are needed. Internal Chip External V1IN + - V1OUT V1T INTRS 34 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Contrast Control (1) (2AH) This instruction updates the contrast control value in normal display mode and partial display mode 0. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 1 0 0 1 0 1 0 1 Contrast control value (0 to 255) DB0 0 The relation between V1 voltage (typ.) and Contrast(1) set value ( 3bit step case) Contrast(1) V1 (HEX) [V] 00h 2.000 08h 10h 18h 20h 28h 2.063 2.125 2.188 2.251 2.314 Contrast(1) V1 Contrast(1) V1 Contrast(1) V1 Contrast(1) V1 Contrast(1) V1 (HEX) [V] (HEX) [V] (HEX) [V] (HEX) [V] (HEX) [V] 30h 2.376 60h 2.753 90h 3.129 C0h 3.506 F0h 3.882 38h 40h 48h 50h 58h 2.439 2.502 2.565 2.627 2.690 68h 70h 78h 80h 88h 2.816 2.878 2.941 3.004 3.067 98h A0h A8h B0h B8h 3.192 3.255 3.318 3.380 3.443 C8h D0h D8h E0h E8h 3.569 3.631 3.694 3.757 3.820 F8h FFh 3.945 4.000 Contrast Control (2) (2BH) This instruction updates the contrast control value in partial display mode 1. D/I 0 WRB 0 RDB 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(2) set value ( 3 bit step case) Contrast(2) V1 (HEX) [V] 00h 2.000 08h 10h 18h 20h 28h 2.063 2.125 2.188 2.251 2.314 Contrast(2) V1 Contrast(2) V1 (HEX) [V] (HEX) [V] 30h 2.376 60h 2.753 38h 40h 48h 50h 58h 2.439 2.502 2.565 2.627 2.690 68h 70h 78h 80h 88h 2.816 2.878 2.941 3.004 3.067 Contrast(2) V1 Contrast(2) V1 Contrast(2) V1 (HEX) [V] (HEX) [V] (HEX) [V] F0h 3.882 90h 3.129 C0h 3.506 F8h 3.945 98h 3.192 C8h 3.569 FFh 4.000 A0h 3.255 D0h 3.631 A8h B0h B8h 3.318 3.380 3.443 D8h E0h E8h 3.694 3.757 3.820 Note : S6B33B0A has a hardware protection for "2VR < 20V". It means the limitation of contrast value in each bias. If 1/6 bias is set, max contrast value is limited to A9h, and if 1/7 bias is set, max contrast value is limited to 6Dh. 35 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Standby Mode OFF (2CH) This instruction releases the standby mode. D/I 0 WRB 0 RDB 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 0 The internal statuses during standby off are as following: All common and segment output: VSS or V1 Oscillator circuit: On (EXT = 0, OSC=1),OFF (others) Displaying clocks (FR, PM, CL): In operation Function and Pin condition at standby OFF Function/Pin DC/DC booster(1'st,2'nd,3'rd) COM outputs SEG outputs Condition ON(Operate) +VR or VM or VSS or -VR V1 or VSS Standby Mode ON (2DH) This instruction enters the standby mode to reduce the power consumption to the static power consumption value (Initial status). The following instructions, standby off and display on, cause returning to the normal operation status. D/I 0 WRB 0 RDB 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 1 The internal statuses during standby on are as following: All common and segment output: VSS Oscillator circuit: OFF Displaying clocks (FR, PM, CL) are held. Function and Pin condition at standby ON Function/Pin DC/DC booster(1'st,2'nd,3'rd) SEG and COM outputs Condition OFF VSS LCD driving power output condition at Standby ON. level +VR V1 VM -VR Condition VSS VSS VSS VSS 36 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD DDRAM Burst Mode OFF(2EH) /ON(2FH) D/I 0 WRB 0 RDB 1 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 BM BM: Internal DDRAM Burst Mode Interface Off/On Control - 0 : Burst Mode Interface Off(Initial Status) - 1 : Burst Mode Interface On When BM=0, If MPU[0] is 0 then internal DDRAM I/F bpw(bits per word) is 8 bits. Else MPU[0] is 1 then internal DDRAM I/F bpw(bits per word) is 16bits. When BM=1, Regardless of MPU[0] bit, Internal DDRAM I/F bpw(bits per word) is 32 bits. MPU 16 8 S6B33B0 Register1 X Address Counter 00H 01H 02H 03H 8 Register2 32 --------8 8EH 8FH Y Address Counter DDRAM Figure 23. Burst mode writing to DDRAM 37 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 /CS --------E --------Burst X Y RAM RAM RAM RAM RAM RAM Mode Address Address DATA DATA DATA DATA DATA DATA ON Setting Setting 1(16bits) 2(16bits) 3(16bits) 4(16bits) 5(16bits) 6(16bits) --------- DB15 ~DB0 ----- RAM Write time RAM Write time RAM data 3 to 4 RAM Write time RAM data 5 to 6 RAM write data (32 bits) RAM X address RAM Y address RAM data 1 to 2 --------- 00H 00H 02H 04H ----- Figure 24. Example of the Burst mode writing to DDRAM (68-mode 16-bit parallel interface) When DDRAM burst mode is used, note the following. Notes: 1.Data is written to DDRAM each two words. If only one word data is written to DDRAM, the data will not be written. So, the number of word data must be even. It means that Y start address must be even and Y end address must be odd. 2.X address count mode can't be used. 3.Burst mode and normal mode write operation cannot be executed at the same time. 4.In the read data mode and serial interface mode, the burst mode can't be used. 5.In the 256 color mode with 16-bit data bus mode and 4,096 color mode with 8-bit data bus mode, The address is counted as burst mode enable. So these modes are influenced by above notes. 38 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Addressing Mode Set (30H) D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 GSM DB5 1 DB4 1 DSG DB3 0 SGF DB2 0 SGP DB1 0 DB0 0 SGM GSM: Gray Scale Mode - 00 : 65,536 color mode(Initial status) - 01 : 4,096 color mode* (refer to "Data Format Select(60H/61H)") - 10 : 256 color mode* - 11 : 256 color mode* * In the 256 color mode with 16-bit data bus mode and 4,096 color mode with 8-bit data format B, the address is counted as burst mode enable. So, In this case, refer to notes of burst mode at page 39. DSG : Duty Adjust Setting - 0 : Dummy subgroup is one subgroup (Initial status) - 1 : Dummy subgroup is none SGF : Sub Group Frame Inversion mode setting - 0: SG Frame inversion OFF (Initial status) - 1: SG Frame inversion ON SGM : Sub Group inversion mode setting - 0: SG inversion OFF (Initial status) - 1: SG inversion ON SGP : Sub Group Phase mode setting - 00 : Same phase in all pixels - 01 : Different phase by 1pixel-unit - 10 : Different phase by 2pixel-unit - 11 : Different phase by 4pixel-unit Row Vector Mode Set (32H) Setting ROW function. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 0 0 DB5 1 0 DB4 1 0 DB3 0 DB2 0 INC DB1 1 DB0 0 VEC INC: Row Vector Increment Mode. This Parameter set up Row vector increment period DB3 0 0 0 0 1 1 1 1 DB2 0 0 1 1 0 0 1 1 DB1 0 1 0 1 0 1 0 1 Row Vector Increment Period Every subgroup Every 2subgroup Every 4subgroup Every 8subgroup Every 16subgroup Every 16subgroup Every 16subgroup Every subframe VEC: ROW Vector Sequence Mode - 0: R1->R2->R3->R4 -> R1..... (initial status) - 1: R1->R3->R2->R4 -> R1..... 39 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 256 Color Mode Palettes At 256-color mode, the instruction and parameter below set each Gray Scale level of the Red/Green/Blue. Gray scale level is determined by GS data. Red Palette (38H) D/I WRB RDB DB7 0 0 0 0 0 0 1 0 0 0 0 0 DB6 0 0 0 0 0 0 0 0 0 DB5 1 0 0 0 0 0 0 0 0 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0 GS data "000" to RAM data GS data "001" to RAM data GS data "010" to RAM data GS data "011" to RAM data GS data "100" to RAM data GS data "101" to RAM data GS data "110" to RAM data GS data "111" to RAM data Green Palette (3AH) D/I WRB RDB DB7 0 0 0 0 0 0 1 0 0 0 0 0 DB6 0 0 0 0 0 0 0 0 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0 GS data "000" to RAM data GS data "001" to RAM data GS data "010" to RAM data GS data "011" to RAM data GS data "100" to RAM data GS data "101" to RAM data GS data "110" to RAM data GS data "111" to RAM data Blue Palette (3CH) D/I WRB RDB DB7 0 0 0 0 1 0 0 0 DB6 0 0 0 0 0 DB5 1 0 0 0 0 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0 GS data "00" to RAM data GS data "01" to RAM data GS data "10" to RAM data GS data "11" to RAM data 40 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Initial value for each Palette Gray Scale Data 000 001 010 011 100 101 110 111 Red 0 8 12 16 20 24 28 31 Initial Gray Scale Level Green 0 16 24 32 40 48 56 63 Blue 0 12 20 31 - The relationship between Gray Scale level and RAM data for Red/Blue RAM Data DB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GS Level DB4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RAM Data DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GS Level 41 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 The relationship between Gray Scale level and Gray Scale data for Green GS Data DB5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GS Level DB5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GS Data DB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 GS Level 42 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD N-block inversion Set (34H) This instruction set up N block inversion for AC driving. D/I WRB RDB DB7 DB6 DB5 0 0 1 0 FIM 0 FIP 1 0 DB4 1 DB3 0 DB2 1 N-block inversion DB1 0 DB0 0 FIM: Forcing Inversion Mode FIM = 0: Forcing Inversion OFF (Initial status) FIM = 1: Forcing Inversion ON FIP: Forcing Inversion Period FIP = 0: Forcing Inversion Period is one frame FIP = 1: Forcing Inversion Period is two frames N-block Inversion : This parameter indicates the basic period of polarity inversion. The whole period of polarity inversion is decided by FIM, FIP and this parameter. DB7 x 0 : 0 1 : 1 1 : 1 DB6 X X : X 0 : 0 1 : 1 DB5 x x : x x : x x : x DB4 - DB0 0 1 : 31 1 : 31 1 : 31 every frame every 1 block : every 31 blocks every 1 block and every frame : every 31 blocks and every frame every 1 block and every 2 frames : every 31 blocks and every 2 frames Polarity Inversion Period 43 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Entry Mode Set (40H) Setting internal function mode. D/I WRB RDB 0 0 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 0 0 DB3 0 HL DB2 0 MDI DB1 0 X/Y DB0 0 RMW HL: When GSM is 10 or 11 (256 color mode), Exchange higher and lower byte in 16-bit data bus mode only for "Display Data Write/Read" HL = 0: Not exchanged status (Initial status) HL = 1: Exchanged status MDI: Memory data inversion setting for low power consumption. MDI = 0: Memory data inversion OFF (Initial status) MDI = 1: Memory data inversion ON Memory 00h 00h FFh 00h X/Y: Memory address counter mode setting X/Y = 0: Y address counter mode (Initial status) X/Y = 1: X address counter mode RMW: Read modify write mode ON/OFF select RMW = 0: Read modify write OFF (Initial status) RMW = 1: Read modify write ON. When this mode is on, X(Y) address of on-chip display RAM is not increment in reading display data but in writing display data. X Address Area Set (42H) This instruction and parameter set up the X address areas of the on-chip display data RAM. D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 X start address set (Initial Status = 00H) X end address set (Initial Status = AFH) The current X address of the on-chip display data RAM is the X start address by setting this instruction. In X address count mode (X/Y = "H"), the X address is increased from X start address to X end address. When X address is equal to the X end address, the Y address is increased by 1 and the X address returns to X start address. The X start and X end addresses must be set as a pair and X start address must be less than X end address. 44 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Y Address Area Set (43H) This instruction and parameter set up the Y address areas of the on-chip display data RAM. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 1 1 0 0 0 0 Y start address set (Initial Status = 00H) Y end address set (Initial Status = 8FH) The current Y address of the on-chip display data RAM is the Y start address by setting this instruction. In Y address count mode (X/Y = "L"), the Y address is increased from Y start address to Y end address. When Y address is equal to the Y end address, the X address is increased by 1 and the Y address returns to Y start address. The Y start and Y end address must be set as a pair and Y start address must be less than Y end address. DB1 1 DB0 1 RAM Skip Area Set (45H) This instruction and parameter set up the X address areas of the on-chip display data RAM. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 1 0 DB1 0 RSK DB0 1 RSK : RAM Skip function ON/OFF set RSK = 00 : No Skip RSK = 01 : Y address 44h-4Bh skip RSK = 10 : Y address 40h-4Fh skip RSK = 11 : Y address 3Ch-53h skip RAM Skip Area Set RAM Skip Area Set can skip a part of RAM Y-address area. After setting RAM skip area, Y-address count skip this area and count. In other words, Y address after skip area is changed into Y address which added a part for skip area. Memory data Y-address Area Input Display Area Skip Area X-address Area 45 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Display OFF (50H) Turn the display OFF(Initial status). When display is off, all segment and common output are VSS level. D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 0 DB0 0 Function and Pin condition at Display OFF Function/Pin Condition DC/DC booster(1'st,2'nd,3'rd) SEG and COM outputs ON(Operate) VSS Display ON (51H) Turns the display ON. In case of being standby mode, this instruction does not work. This instruction is executed after standby mode off. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 0 0 1 Function and Pin condition at Display ON Function/Pin Condition DC/DC booster(1'st,2'nd,3'rd) COM outputs SEG outputs ON(Operate) +VR or VM or -VR V1 or VSS Specified Display Pattern Set (53H) This instruction sets the specified display pattern. D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 1 0 DB3 0 0 DB2 0 0 DB1 1 SDP DB0 1 SDP : Specified Display Pattern set - SDP = 00 : Normal display - SDP = 01 : Reverse display : Display data reversing mode setting without the contents of the display RAM SDP = 10 : Whole display pattern becomes OFF regardless of the RAM data. SDP = 11 : Whole display pattern becomes ON regardless of the RAM data. 46 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Partial Display Mode Set (55H) D/I 0 WRB 0 RDB 1 DB7 0 0 DB6 1 0 DB5 0 0 DB4 1 0 DB3 0 0 DB2 1 0 DB1 0 PDM DB0 1 PT PT: Partial Display ON/OFF PT = 0: Partial display OFF = Normal mode (Initial status) PT = 1: Partial display ON PDM: Partial Display mode set PDM = 0: Partial mode 0 : Duty ratio is same as Normal display mode(initial status) PDM = 1: Partial mode 1 : Duty ratio is changed from Normal display mode (DSG = 0 : 69 line fixed(including 1 dummy subgroup), DSG = 1 : 66 line fixed(no dummy subgroup)) Applied parameter in PDM0 and PDM1 are summarized as below PDM 0 1 Contrast Contrast control(1) Contrast control(2) Duty Normal 1/69 Bias Bias(1) Bias(2) DC-DC Select DC(1) DC(2) OSC OSC1-OSC2 OSC3-OSC4 PCK DIV(1) DIV(2) Partial Start Line Display Area N line Partial Start Line M line Partial End Line 69 line Fix Partial End Line PDM 0 No display Area PDM 1 : No COM Scanning field (COM = Vm fixed) Except Partial Display Area : COM Timing is existing, but COM = Vm fixed Partial Display Area : Real display field Operation in Partial Display Mode 0 (PDM=0) On scanning except partial display area - SEG output select V0 or V1 level depend on "FR" value. Refer to Page51. - All of COM output is fixed VM level. On scanning partial display area - It is equal to be in normal mode Operation in Partial Display Mode 1 (PDM=1) Display area is from partial start line to partial end line. (COM driver output is fixed VM except display area, only max69 line output COM signal. On scanning except partial display area - SEG output select V0 or V1 level depend on "FR" value. Refer to Page51. - All of COM output is fixed VM level. On scanning partial display area - It is equal to be in normal mode 47 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Partial Display Mode0 Item Duty Bias Contrast Oscillator SEG Output level COM Output level Partial Display Area Out of Partial Display Area Same as normal display mode Same as normal display mode ( Bias(1) setting ) Same as normal display mode ( Contrast(1) setting ) Same as normal display mode ( OSC1 - OSC2 ) Same as normal mode (V1,V0) Same as normal mode (+VR,VM,-VR) Depends on Internal "FR" signal See page 51 VM fixed In case of COM 6 to COM11 Partial display +VR VM -VR Normal Display Mode Partial Display Mode 1 Partial display mode1 Item Duty Bias Contrast Oscillator SEG Output level COM Output level Same as normal mode (V1,V0) Same as normal mode (+VR, VM, -VR) Partial Display Area Out of Partial Display Area 1/69duty Bias(2) setting Contrast(2) setting ( OSC3 - OSC4 ) setting value Depends on "FR" signal See page 51 VM fixed VM fixed Out of Display Area 48 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Partial Display Start Line Set (56H), Partial Display End Line Set(57H) These 2 instructions set the partial display area and it is possible to display a part. Partial Display Start Line Set (56H) D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 1 DB1 1 DB0 0 Partial start line Partial Display End Line Set (57H) D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 1 DB1 1 DB0 1 Partial end line COM 0 COM 1 COM 2 COM 3 line line line line : : : 0 1 2 3 COM COM COM COM 172 173 174 175 line line line line 172 173 174 175 Parameter set appoints display line number. At PDM 0, Parameter Size is able to be in a number of Display lines. But that is not able to be over max 69 line at PDM 1. Partial end line must set bigger number than Partial start line. 49 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Example of Segment Voltage in non-display area Frame Subframe N 0 VM Display Off Partial Display Addressing Duty N+1 2 3 VM VM 1 VM 0 +VR COM VM -VR internal polarity counter (FR) V1 V1 V0 V0 V1 V1 V0 V1 V0 SEG V0 V1 VM V0 Area scroll Set (59H) This instruction sets up area scroll field (start line, end line, Lower fixed line number), and it is possible to make screen to display as partial scroll field. D/I WRB RDB DB7 0 0 0 0 1 DB6 1 0 DB5 0 0 DB4 1 0 DB3 1 0 DB2 0 0 DB1 0 SCM DB0 1 Scroll area start line Scroll area end line Lower fixed number SCM: Scroll mode setting DB1 0 0 1 1 DB0 0 1 0 1 Mode Entire display(Initial status) Upper scroll display Lower scroll display Center scroll display 50 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Entire Display Scroll Start Line Set (5AH) Upper Display Lower Display Center Display This instruction and parameter set up scroll start line. On this instruction, scroll start line becomes the first of area scroll field. Scroll operation is occurred every issue of this instruction. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 1 0 Scroll start line Addr0 Addr5 Addr40 Xadr=40 Scroll display Scroll area Addr166 Addr6 COM167 COM175 Lower fix Xadr=167 Xadr=175 Lower fix COM167 COM175 Addr39 Addr167 Addr175 RAM Address. 51 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Normal Mode Set partial start line Set partial end line Set partial mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line Set scroll start line Set partial start line Check busy flag Set partial end line Set partial mode 0 Scroll/Partial Mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Release partial mode Partial Mode 0 Scroll Mode Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Release partial mode Normal Mode Data Format Select (60H/61H) D/I 0 WRB 0 RDB 1 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 DFS DFS: 4,096 Color Mode Data Format Select - 0 : 4,096 Color Data Format A (Initial Status) 8 bit mode : DB[7:0] : XXXXRRRR (1'st write) DB[7:0] : GGGGBBBB(2'nd write) 16 bit mode : DB[15:0] :XXXXRRRRGGGGBBBB (12 bit) - 1 : 4,096 Color Data Format B 8 bit mode : DB[7:0] : RRRRGGGG(1'st write) DB[7:0] : BBBBRRRR (2'nd write) DB[7:0] : GGGGBBBB(3'rd write) 16 bit mode : DB[15:0] :RRRRGGGGBBBBXXXX (12 bit) 52 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Display Data Write/Read D/I 1 1 WRB 0 1 RDB 1 0 DB15 ~ DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display RAM write in data Display RAM read out data GSM = 00(65,536 Color Mode) (1) 16bit access mode 15 14 13 1'st cycle R4 R3 R3 6 R3 G1 R3 G1 R2 R2 5 R2 G0 R2 G0 2'nd cycle R4 (2) 8bit access mode 7 1'st cycle 2'nd cycle 3'rd cycle 4'th cycle R4 G2 R4 G2 12 R1 R1 4 R1 B4 R1 B4 11 R0 R0 3 R0 B3 R0 B3 10 G5 G5 2 G5 B2 G5 B2 9 G4 G4 1 G4 B1 G4 B1 8 G3 G3 0 G3 B0 G3 B0 7 G2 G2 6 G1 G1 5 G0 G0 4 B4 B4 3 B3 B3 2 B2 B2 1 B1 B1 0 B0 B0 GSM = 01(4,096 Color Mode) (1) 16bit access mode 15 14 1'st cycle X X X 6 X G2 X G2 2'nd cycle X (2) 8bit access mode 7 1'st cycle 2'nd cycle 3'rd cycle 4'th cycle X G3 X G3 13 X X 5 X G1 X G1 12 X X 4 X G0 X G0 11 R3 R3 3 R3 B3 R3 B3 10 R2 R2 2 R2 B2 R2 B2 9 R1 R1 1 R1 B1 R1 B1 8 R0 R0 0 R0 B0 R0 B0 7 G3 G3 6 G2 G2 5 G1 G1 4 G0 G0 3 B3 B3 2 B2 B2 1 B1 B1 0 B0 B0 GSM = 10 or 11 (256 Color Mode) (1) 16bit access mode 15 14 13 1'st cycle R2 R1 R1 6 R1 R1 R1 R1 R0 R0 5 R0 R0 R0 R0 2'nd cycle R2 (2) 8bit access mode 7 1'st cycle 2'nd cycle 3'rd cycle 4'th cycle R2 R2 R2 R2 12 G2 G2 4 G2 G2 G2 G2 11 G1 G1 3 G1 G1 G1 G1 10 G0 G0 2 G0 G0 G0 G0 9 B1 B1 1 B1 B1 B1 B1 8 B0 B0 0 B0 B0 B0 B0 7 R2 R2 6 R1 R1 5 R0 R0 4 G2 G2 3 G1 G1 2 G0 G0 1 B1 B1 0 B0 B0 53 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Status Read D/I 0 WRB 1 RDB 0 DB7 BSY DB6 X/Y DB5 0 DB4 PDM DB3 PT DB2 STB DB1 REV DB0 DP This instruction indicates the internal status of the S6B33B0A. DP: ( 0 : Display OFF Status, 1 : Display ON Status ) REV: ( 0 : Display Image Non-Reversing, 1 : Display Image Reversing ) STB: ( 0 : Standby Mode OFF Status, 1 : Standby Mode ON Status ) PT: ( 0 : Partial Display Mode OFF Status, 1 : Partial Display Mode ON Status ) PDM: ( 0 : Partial Display Mode 0, 1 : Partial Display Mode 1 ) X/Y: ( 0 : Y-address Count Mode, 1 : X-address Count Mode ) BSY: ( 0 : No Busy, 1 : Busy ) Set Display Data Length (FCH) This Instruction is only used in 3-pin SPI MPU interface mode(PS="L", MPU[1]="L"). It consists of two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second and third bytes will be number of data bytes will be write. When DI is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. D/I 0 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0 Number of display data upper 8bits (DDL_H) Number of display data lower 8bits (DDL_L) 54 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Test Mode1 (FFH) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 Test Mode2 (FEH) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 Test Mode3 (FDH) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 Test Mode4 (FBH) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 Test Mode5 (FAH) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 Test Mode6 (F9H) This Instruction is for testing IC. User is not permitted to access. if access, have to reset. D/I 0 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 1 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 1 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 1 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 0 WRB 0 RDB 1 DB7 1 DB6 1 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 1 55 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 INSTRUCTION PARAMETER Table 16. Instruction Parameter Instruction Oscillation Mode Set Driver Output Mode Set DC-DC Set Bias Set DCDC Clock Division Set DCDC and AMP ON/OFF Set Temperature Compensation Set Contrast Control (1) Contrast Control(2) Addressing Mode Set ROW Vector Mode Set N-line Inversion Set Entry Mode Set Hex 02H 10H 20H 22H 24H 26H 28H 2AH 2BH 30H 32H 34H 40H Para. 1 1 1 1 1 1 1 1 1 1 1 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 EXT OSC * * * * * * 0 0 0 0 DLN 0 SDIR SWP 0 * * 0 0 * 0 0 0 0 0 0 0 DC(2) DC(1) 0 0 0 0 0 0 0 0 0 0 Bias(2) 0 0 Bias(1) 0 * 0 0 * * 0 0 0 0 DIV(2) 0 0 DIV(1) * * 1 0 * * 1 0 0 0 0 0 AMP DCDC3 DCDC2 DCDC1 * * * * 0 0 0 0 0 0 0 0 0 0 TCS * * * * * * 0 0 Contrast control value in normal and partial display mode0(0 to 255) 0 0 0 0 0 0 0 0 Contrast control value in partial display mode 1(0 to 255) 0 0 0 0 0 0 0 0 GSM DSG SGF SGP SGM 0 * * 0 0 0 0 0 0 0 0 0 0 INC VEC * * * * 0 0 0 0 FIM FIP 0 N-block Inversion 0 0 * 0 0 0 0 0 0 0 0 0 HL MDI X/Y RMW * * * * * 0 0 0 X Start address set 0 0 0 0 0 0 0 0 X end address set 1 0 1 0 1 1 1 1 Y start address set 0 0 0 0 0 0 0 0 Y end address set 1 0 0 0 1 1 1 1 0 0 0 0 0 0 RSK * * * * * * 0 0 Number of display data DDL_H Number of display data DDL_L 0 0 0 0 0 0 SDP * * * * * * 0 0 0 0 0 0 0 0 PDM PT * * * * * * 0 0 Partial start line 0 0 0 0 0 0 0 0 Partial end line 0 0 0 0 0 0 0 0 X-address Area Set 42H 2 Y-address Area Set 43H 2 RAM Skip Area Set Set Display Data Length Specified Display Pattern Set Partial Display Mode Set Partial Display Start Line Set Partial Display End Line Set 42H FCH 53H 55H 56H 57H 1 2 1 1 1 1 56 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Table 16. Instruction Parameter (Continued) Instruction Hex Para. DB7 0 * 0 1 0 Scroll Start Line Set 5AH 1 0 DB6 0 * 0 0 0 0 DB5 0 * 0 1 0 0 DB4 DB3 DB2 0 0 0 * * * Scroll area start line 0 0 0 Scroll area end line 0 1 1 Lower Fixed number 0 0 0 Scroll start line 0 0 0 DB1 DB0 SCM 0 0 0 1 0 0 0 1 0 0 Area Scroll Mode Set 59H 4 57 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Reset Operation When RSTB becomes "L", following procedure is occurred. - X start address: 0, X end address: 176 - Y start address: 0, Y end address: 143 - Display OFF - Read Modify Write Mode OFF - Function Mode Set MDI = 0: Memory Data Inversion OFF OSC = 0: Oscillator OFF EXT = 0: Internal Oscillator Mode REV = 0: Reversing mode OFF X/Y = 0: Y-address Count Mode Standby Mode ON - DCDC Clock Division Set DIV(1) = 10: fPCK = fOSC/16x DIV(2) = 10: fPCK = fOSC/16x - Duty Set Display Duty = 00H: 1/128 duty - DC-DC Select DC(1) = 0: X1 step-up DC(2) = 0: X1 step-up - Bias Set Bias(1) = 0H: 1/4 bias Bias(2) = 0H: 1/4 bias - DC/DC and AMP ON/OFF Set AMP =0: Built-in OP-AMP OFF DCDC1 =0: Built-in 1'st booster OFF DCDC2 =0: Built-in 2'nd booster OFF DCDC3 =0: Built-in 3'rd booster OFF - N-block inversion FIM =0: Forcing Inversion OFF FIP =0: Forcing Inversion Period in one frame N-block inversion = 00H: frame inversion - Partial Display Mode PT = 0: Partial Display Mode OFF PDM = 0: Partial Mode 0 - Partial Display Area Set Partial start line = 00H Partial end line = 00H -Area Scroll Set Mode = 00H : Entire Display Scroll Mode Area Start Line: 00H Area End Line: AFH Lower Fixed Line Number: 00H - Scroll Start Line Set Scroll Start Line: 00H - Addressing Mode Set GSM=00: 65,536 Color Mode DSG = 0: Mode 0 SGF = 0: SG Frame Inversion OFF SGM = 0: SG Reverse Mode OFF SGP=00:Same phase in all pixel - Row Vector Mode Set INC =000: Increment every subgroup VEC=0: R1->R2->R3->R4->R1->... 58 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD POWER ON/OFF SEQENCE Power ON Sequence Power On Set various registers and RAM data if needed (XS,XE,YS,YE,MDI,EXT,REV,XY,DIV,DLN,BIAS,DC, FIM,FIP,N-block,PT,PDM,SMOD,DSG,GSM,SGF, SGM,SGP,INC,VEC, Display Data) Reset Waiting for releasingReset Display ON Standby mode OFF Busy Busy Flag check or waiting for No busy OSC ON DCDC1 ON AMP ON DCDC2 ON DCDC3 ON 59 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Power OFF Sequence Display Off Standby On ( DCDC3 OFF DCDC2 OFF AMP OFF DCDC1 OFF OSC OFF ) Waiting for Discharge Power Off 60 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Item Supply Voltage range LCD Supply Voltage range Input Voltage range Operating Temperature range Storage Temperature range Symbol VDD3 |VCC - VEE| Vin TOPR TSTR - 0.3 to -0.3 Rating to 22 VDD +0.3 +4.0 Unit V V V C C -30 to +70 -55 to +150 OPERATING VOLTAGE Item Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Symbol VDD3 2Vr VIN Min. 1.8 4.0 2.4 Typ. 3.0 Max. 3.3 20 3.6 Unit V V V 61 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 DC CHARACTERISTICS (1) (Vss = 0V, VDD3 = 1.8 to 3.3V, Ta = -30 to 70 C) Uni Min Typ Max Remarks t 1.8 2.4 2.4 2.4 1/4 Bias Operating voltage DC2IN 1/5 Bias 1/6 Bias 1/7 Bias Operating voltage Driving voltage input range Input voltage Output voltage High Low High Low 2Vr VM VCC VEE VIH VIL VOH VOL IIL IOZ FOSC1 IOH = 0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS R1=80kOhm Oscillator Frequency Tolerance Partial 1 Normal or Partial 0 Partial 1 FOSC2 Normal or Partial 0 (fFR=100Hz target), DSG=0, 176 display lines R1=300kOhm (fFR=70Hz target), 69 display lines Oscillator Frequency Range FOSC1 FOSC2 V1 VM REG_OUT REG_ENB = "L" (*1) (*2) 84.48 29.44 2.0 1.0 1.8 288 88.32 4.0 2.0 2.2 kHz kHz V V OSC1 OSC2 OSC3 OSC4 46.36 51.52 56.68 kHz OSC3 OSC4 172.8 192.0 211.2 kHz OSC1 OSC2 External power supply mode 2Vr = |(+VR)- (-VR)| 1.5 1.33 1.67 1.5 4.0 1.0 5.0 -3.0 0.8VDD VSS 0.8VDD VSS -1.0 -3.0 3.3 3.6 7.2 7.2 3.0 2.67 3.33 3.0 20 2.0 12.0 -8.0 VDD 0.2VDD VDD 0.2VDD +1.0 +3.0 A A V V V V V V +VR, -VR VMOUT VRP VRN V DC2OUT V V V V VOUT45 VDD3 VIN1,VIN1A Item Operating voltage Operating voltage Operating voltage Operating voltage Symbol VDD3 VIN1 VIN2 VIN45 Condition Input leakage current Output leakage current Driving voltage input range Regulator output range (*1) Minimum oscillator frequency range is defined at fFR=60Hz and display line number=128 Maximum oscillator frequency range is defined at fFR=150Hz and display line number=176 (*2) Minimum oscillator frequency range is defined at fFR=40Hz and display line number=69 62 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Maximum oscillator frequency range is defined at fFR=120Hz and display line number=69 DC CHARACTERISTICS (2) Item SEG Driver output resistance COM Symbol RON-Seg Condition V1=3.0 V, V0=0V, Ta = 25C, Iload=50uA VCC=10.5 V, VM=1.5V, VEE=-7.5V, Ta = 25C, Iload=100uA VDD3=VIN1=3.0V, V1=3.0V, Bias(1)=1/6, DC(1)=x1.5, Ta=25C, Display line=176 DSG=0 (1dummy) fOSC1=192.0kHz (fFR=100Hz) Low current mode, No load, No access, All white pattern VDD3=VIN1=3.0V, V1=3.0V, Bias(2)=1/5, DC(2)=x1.5, Ta=25C, 1/69 duty fOSC2=51.52kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern Min - Typ 1.5 Max 3.0 Unit k Remarks SEGn RON-Com - 1.0 1.5 k COMn Normal Mode Current consumption Partial1 Mode IDD - 650 750 VDD3 + VIN1 - 200 250 * : "IDD" is determined from lowest power consumption for dc-dc converter. 63 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 DC CHARACTERISTICS (3) Item Symbol (+VR) (V1) Voltage shift range(*1) (VM) (-VR) Isource,sink = 250uA Isink = 80uA 20 150 mV mV VM -VR (Vss = 0V, VDD3 = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Condition Min Typ Max Unit Remarks Isource = 80uA Isource = 250uA 150 20 mV mV +VR V1 (*1) Voltage shift means output voltage deference between output current = Iload and no-load. Refer to the following figure. (in case of source current mode) No-load Vx Vx Current = I Load Vy I=0 Vshift = |Vx-Vy| Vy I=ILoad Item Tolerance of Bias ratio Symbol (+VR)_0 (-VR)_0(*1) Condition No load Min -100 Typ - Max +100 Unit mV Remarks +VR -VR (*1) Tolerance of bias ratio definition (+VR)_0 = ((+VR) - VM ) - VM / Bias (-VR)_0 = ( VM - (-VR)) - VM / Bias 64 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD DC CHARACTERISTICS (4) (Vss = 0V, VDD3 = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Item Temperature compensation Tolerance of Contrast step of V1 Symbol Vt Vstep Contrast set = FFh Contrast set = 00h V1 VM V1 VM Condition VDD3=VIN1=V1=3.0V, -20 to 70 C Min -0.02 3.13 3.95 1.95 1.95 0.95 Typ 6.27 4.00 2.00 2.00 1.00 Max +0.02 9.41 4.05 2.05 2.05 1.05 Unit %/C mV V V V V Remarks V1 V1 V1 VM V1 VM Voltage range V1 VM Item ||+VR-VM| -|VM -(-VR)|| Offset Voltage A ||V1-VM| -|VM-V0|| B Condition Load current Voltage range Max 100 Unit mV Ref Fig.1 I Load = +100uA (+VR) I Load = -100uA (-VR) I Load = +100uA ( V1, VM ) I Load = +100uA (+VR) I Load = -100uA (-VR) +VR=5.0~12.0 V V1=2.0~4.0V VM=1.0~2.0V -VR=-3.0~-8.0 V 50 mV Fig.2 +VR Vx VM Vy -VR +100uA V1 Va +100uA (both Case A and B) -100uA (Case B) +100uA (Case A) Vb |Vx-Vy| < 100mV VM -100uA V0 |Va-Vb| < 50mV Fig. 1: Offset voltage definition (+VR,VM,-VR) Fig. 2: Offset voltage definition (V1,VM,V0) 65 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 DC CHARACTERISTICS (5) (Vss = 0V, VDD3 = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 C) Range Min V1OUT Voltage Level VMOUT DC2OUT (*1) This definition is shown as below VIN45 Item Max 4.0 V (DC(1) and DC(2) = X2) (*1) 2.0 V (DC(1) and DC(2) = X2) (*2) 3.33V (DC(1) and DC(2) = X2) (*3) (1/6 Bias, V1OUT = 4V) 2.0 V 1.0 V 1.33V (1/5 Bias, V1OUT = 2V) V1OUT Output VIN45 Delta V V1OUT Delta V > 0.3 V (External VIN45) Delta V > 0.5 V (VIN45 = VOUT45) If V1OUT input voltage is set over VIN45, V1OUT output voltage must be clipped near VIN45. In this case, V1OUT output level must not be unstable. Refer to Fig.1 VIN45 VIN45 - Delta V Fig. 1 V1OUT Input (*2) This definition is shown as below VIN1 VMOUT Output VIN1 Delta V VMOUT Delta V > 0.3 V If VMOUT input voltage is set over VIN1, VMOUT output voltage must be clipped near VIN1. In this case, VMOUT output level must not be unstable. Refer to Fig.2 (*3) This definition is shown as below VIN2 VIN1 VIN1 - Delta V Fig. 2 VMOUT Input DC2OUT Output VIN2 Delta V DC2OUT Delta V > 0.3 V (External VIN2) Delta V > 0.5 V (VIN2 = VOUT45) If DC2OUT input voltage is set over VIN2, DC2OUT output voltage must be clipped near VIN2. In this case, VMOUT output level must not be unstable. Refer to Fig.3 VIN2 VIN2 - Delta V Fig. 3 DC2OUT Input 66 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) D/I tAS80 /CS1 (CS2) tPW L80(R), /RD, /WR 0.9V DD 0.1V DD tDS80 DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and /WR(/RD) is low. Figure 25. Parallel Interface (8080-series MPU) Timing Diagram tOD80 tDH80 tPWL80(W) tCY80 tPWH80(R), tPW H80(W) tAH80 Table 17. AC Characteristics (8080-series Parallel Mode) (VDD3 = 1.8 to 3.3V, Ta = -30 to +70C) Min. Max. Unit (3.3V/1.8V) 3.3V 1.8V 0 0 150 50 30 50 30 5 8 CL = 100 pF tEWHR 0 0 360 100 75 100 75 10 14 60 / 120 ns ns ns ns ns ns Item Address setup time Address hold time System cycle time Pulse width low for write Pulse width High for write Pulse width low for read Pulse width high for read Data setup time Data hold time Read access time Output disable time Signal D/I Symbol tAS80 tAH80 tCY80 tPWLW tPWHW tPWLR tPWHR tDS80 tDH80 tACC80 tOD80 Condition WRB (WRB) RDB (RDB) DB0 to DB15 NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read 67 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Read / Write Characteristics (6800-series Microprocessor) D/I,R/W tAS68 tAH68 /CS1 (CS2) tEW H68(R), tEWH68(W) tCY68 t EWL68(R), tEWL68(W) E 0.1VDD 0.9VDD tDS68 tDH68 DB0 to DB7 (Write) tACC68 tOD68 DB0 to DB7 (Read) ** tEWH68(W) and t EWH68(R) is specified in the overlapped period when /CS1 is low (CS2 is high) and E is high. Figure 26. Parallel Interface (6800-series MPU) Timing Diagram Table 18. AC Characteristics (6800-series Parallel Mode) (VDD3 = 1.8 to 3.3V, Ta = -30 to +70C) Item Address setup time Address hold time System cycle time Enable width high for write Enable width low for write Enable width high for read Enable width low for read Data setup time Data hold time Read access time Output disable time RDB (E) RDB (E) DB0 to DB15 Signal D/I R/W Symbol tAS68 tAH68 tCY68 tEWHW tEWLW tEWHR tEWLR tDS68 tDH68 TACC68 tOD68 CL = 100 pF Condition Min. 3.3V 0 0 150 50 30 50 30 5 8 tEWLR 1.8V 0 0 360 100 75 100 75 10 14 Max. (3.3V/1.8V) 60 / 120 Unit ns ns ns ns ns ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read 68 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD Serial Data Interface Timing /CS1 (CS2) 0.1VDD t CSS t SCYC t CSH 0.1VDD tr tSHW tSLW SCL tf t SAS tSAH D/I t SDS tSDH 0.9VDD 0.1VDD 0.9VDD 0.1VDD SDI Table 19. Serial Data Interface Timing (VDD3 = 1.8 to 3.3V, Ta = -30 to +70C) Item SCL Cycle Time SCL High Pulse Width SCL Low Pulse Width SDI Setup time SDI Hold time D/I Setup time D/I Hold time Chip Select Setup time Chip Select Hold time Signal SCL SCL SCL SDI SDI D/I D/I CS1B(CS2) CS1B(CS2) Symbol tCSC tSHW tSLW tSDS tSDH tSAS tSAH tCSS tCHS Condition Min. 50 20 20 20 20 20 20 20 20 Max. Unit ns ns ns ns ns ns ns ns ns 69 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 Reset Input Timing tRW /RST tR Internal status During reset Reset complete Figure 27. Reset Input Timing Diagram Table 20. AC Characteristics (Reset mode) (VDD3 = 1.8 to 3.3V, Ta = -30 to +70C) Item Reset low pulse width Reset time Signal RSTB Symbol tRW tR Condition Min. 1000 Max. 1000 Unit ns ns 70 S6B33B0A PRELIMINARY VER 1.1 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD External Components SYSTEM APPLICATION DIAGRAM Internal Power Mode VDD3, VDD3R VDD3 or REG_OUT C1 VDD, VDDO REG_OUT Name R1,R2 C1,C2,C3 D1 Device Resistors Capacitors Schottky barrier diode Values of external Capacitors and D1 Item Capacitance 1.0 to 4.7F 1.0 to 2.2F 1.0 to 2.2F Vforward = Max. 0.3V at 1mA Vreverse = Min. 15V VSS, VSSA, VSSB, VSSO C1 C2 C3 D1 DB15DB0 /RD DB15 to DB0 /RD /WR /CS1 CS2 D/I /RST R1 OSC1 R2 OSC2 OSC3 OSC4 OSC5 MPU /WR /CS1 CS2 D/I /RST Maximum rating voltage of capacitors Maximum Item rating voltage REG_OUT to VSS VOUT45 to VSS C11P to C11M C12P to C12M VMOUT to VSS DC2OUT to VSS V1OUT to VSS C21P to C21M C22P to C22M C23P to C23M C24P to C24M VSS to VRN C31P to C31M VRP to VSS VIN2 S6B33B0A VIN1 VIN1, VIN1A C2 C2 C11P C11M C12P C12M VOUT45 C3 VIN45 C21P C21M C22P C22M C23P C23M C24P V1OUT C3 V1IN C24M VRN VEES, VEE VMOUT C3 VMIN VIN2 DC2OUT DC2IN 3V 11V 6V 6V 3V 5V 6V 5V 10V 13V 13V 13V 17V 18V C3 C2 C2 C2 C2 C3 D1 V0IN C31P C31M VRP VCC C3 C2 71 144 RGB SEGMENT & 177 COMMON DRIVER FOR 65,536 COLOR STN LCD S6B33B0A PRELIMINARY VER 1.1 External Power Mode VDD3, VDD3R VDD, VDDO REG_OUT C VDD3 or REG_OUT VSS, VSSA, VSSB, VSSO DB15 to DB0 /RD DB15 to DB0 /RD /WR /CS1 CS2 D/I MPU /WR /CS1 CS2 D/I /RST R1 /RST OSC1 OSC2 OSC3 OSC4 OSC5 R2 S6B33B0A VIN1 VIN1, VIN1A C11P C11M C12P C12M VOUT45 VIN45 C21P C21M C22P C22M C23P C23M V1OUT V1IN C24P C24M VRN VMOUT VMIN VEES, VEE VEE VIN2 DC2OUT DC2IN VIN2 V1IN VMIN V0IN C31P C31M VRP VCC VCC 72 |
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