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9 Jul ,1997 9 Jul ,1997
M5M51016BTP,RT-12VL-I, M5M51016BTP,RT-12VL-I, -12VLL-I -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM 1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low stand-by current and low operation current and ideal for the battery back-up application. The M5M51016BTP,RT are packaged in a 44-pin thin small outline package which is a high reliability and high density surface mount device (SMD). Two types of devices are available. M5M51016BTP(normal lead bend type package), M5M51016BRT (reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
MITSUBISHI LSIs MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
NC A12 A7 A6 A5 A4 A3 A2 A1 A0
CHIP SELECT INPUT CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC BC1 BC2 A14 A15
BYTE CONTROL INPUTS ADDRESS INPUTS
ADDRESS INPUTS
FEATURES
Power supply current Type name
Access time (max)
Active (max)
stand-by (max) 120A (VCC = 3.6V)
M5M51016BTP,RT-12VL
120ns 12mA (1MHz)
M5M51016BTP,RT-12VLL
120ns
24A (VCC = 3.6V) 0.3A (VCC = 3.0V, typ)
Single +3.0V power supply Low stand-by current 0.3E A (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by CS, BC1 & BC2 Data hold on +2V power supply Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51016BTP,RT .............................. 44pin 400mil TSOP(II)
(0V)GND OUTPUT ENABLE INPUT OE NC DQ1 DQ2 DQ3 DATA DQ4 INPUTS/ OUTPUTS DQ5 DQ6 DQ7 DQ8
A13 WRITE CONTROL W INPUTS A8 A9 ADDRESS INPUTS A11 A10 GND(0V) NC DQ16 DQ15 DQ14 DQ13 DATA INPUTS/ DQ12 OUTPUTS DQ11 DQ10 DQ9 VCC(5V)
Outline 44P3W - H (400mil TSOP Normal Bend)
M5M51016BTP
APPLICATION
Small capacity memory units
NC BC1 BC2 A14 ADDRESS INPUTS A15 A13 WRITE CONTROL W INPUTS A8 ADDRESS A9 INPUTS A11 A10 (0V)GND NC DQ16 DQ15 DQ14
BYTE CONTROL INPUTS DATA INPUTS/ OUTPUTS
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
DQ13 DQ12 DQ11 DQ10 DQ9
(5V)VCC
NC A12 A7 A6 A5 ADDRESS A4 INPUTS A3 A2 A1 A0 CS CHIP SELECT INPUT GND(0V) OUTPUT ENABLE OE INPUT NC DQ1 DQ2 DQ3 DQ4 DATA INPUTS/ DQ5 OUTPUTS DQ6 DQ7 DQ8
Outline 44P3W - J (400mil TSOP Reverse Bend)
NC : NO CONNECTION
M5M51016BRT
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51016B series are determined by a combination of the device control inputs BC1, BC 2, CS, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the high level CS. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, BC1, BC2 or CS, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the databus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and CS are in an active state. (BC1 and/or BC2=L,CS=H) When setting BC1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower-Byte are in a non-selectable mode.And when setting BC2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode and upper -Byte are in a non-selectable mode.
MITSUBISHI LSIs
When setting BC1 and BC2 at a high level or CS at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and CS. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during powerfailure or power-down operation in the non-selected mode. DQ1~8 DQ9~16 ICC CS BC1 BC2 W OE Mode L X X X X Non selection High-Z High-Z Stand-by X H H X X Non selection High-Z High-Z Stand-by Din Active H HL L X Upper-Byte Write High-Z H HL H L Upper-Byte Read High-Z Dout Active H HL HH High-Z High-Z Active H L HL X Lower-Byte Write Din High-Z Active H L H H L Lower-Byte Read Dout High-Z Active L HHH High-Z High-Z Active H Din Din H L L L X Word Write Active H L L H L Word Read Dout Dout Active L L HH High-Z High-Z Active H
(High-Z=High-impedance)
BLOCK DIAGRAM
OUTPUT BUFFER A1 9 A3 7 ADDRESS INPUT BUFFER A6 4 A7 3 A12 2 A14 41 A1540 A13 39 A8 37 ADDRESS INPUTS A9 36 SENSE AMP. 15 DQ1 16 DQ2 17 DQ3 18 DQ4 19 DQ5 20 DQ6 21 DQ7 22 DQ8 SENSE AMP. 24 DQ9 25 DQ10 26 DQ11 27 DQ12 28 DQ13 29 DQ14 30 DQ15 31 DQ16 ADDRESS INPUT BUFFER BLOCK DECODER INPUT DATA CONTROL DATA INPUTS/ OUTPUTS
ROW DECODER
65536 WORDS x16 BITS ( 1024 ROWS x 256 COLUMNS x 4 BLOCKS )
ADDRESS INPUT BUFFER
A4 6 A2 8 A5 5
A10 34 A11 35 CHIP SELECT INPUT BYTE CONTROL INPUTS CS 11 BC1 43 BC2 42
COLUMN DECODER
A0 10
CLOCK GENERATOR
INPUT DATA CONTROL
OUTPUT BUFFER
23 Vcc 33 GND(0V) 12 GND (0V)
WRITE CONTROL W 38 INPUT OUTPUT ENABLE OE 13 INPUT
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25 C
o
MITSUBISHI LSIs
Ratings - 0.3 ~ 4.6 - 0.3* ~ Vcc + 0.3 0 ~ Vcc 1 - 40 ~ 85 - 65 ~ 150
Unit V V V W C o C
o
* -3.0V in case of AC ( Pulse width < 50ns )
o DC ELECTRICAL CHARACTERISTICS (Ta=- 40 ~ 85 C , Vcc=2.7V ~ 3.6V, unless otherwise noted)
Symbol VIH VIL VOH1 VOH2 VOL II IO ICC1W ICC2W ICC1B ICC2B
Parameter High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current Output current in off-state Word operation (16bit) Active supply current (AC,TTL level) Byte operation (8bit) Active supply current (AC,TTL level)
Test conditions
Min 2.0 - 0.3*
Limits Typ
Max
Vcc+0.3V
Unit V V V V V A A mA mA mA mA A A mA
0.6
IOH = -1mA IOH = - 0.1mA IOL = 2mA VI =0 ~ Vcc BC1 and BC2 = VIH or CS = VIL or OE = VIH, VI/O = 0 ~ Vcc
BC1 and BC2 = VIL, CS = VIH other inputs = VIH or VIL Output-open(duty 100%) (BC1 = VIH and BC2 = VIL) or (BC1 = VIL and BC2 = VIH), CS = VIH other inputs = VIH or VIL Output-open(duty 100%) 1) CS < 0.2V, other inputs = 0~Vcc 2) BC1,BC2 > Vcc - 0.2V, CS > Vcc - 0.2V other inputs = 0~Vcc BC1 and BC2 = VIH or CS = VIL, other inputs = 0~Vcc
Min cycle 1MHz Min cycle 1MHz
2.4
Vcc-0.5V
0.4 + _1 + _1 27 5 20 3 50 12 30 10 120 24 1
-VL -VLL
ICC3
Stand-by current
ICC4
Stand-by current
* -3.0V in case of AC ( Pulse width < 30ns )
CAPACITANCE (Ta=- 40 ~ 85 o C , Vcc=2.7V ~ 3.6V, unless otherwise noted)
Symbol CI CIBC CO Parameter Input capacitance ( except BC1,BC2) Input capacitance ( BC1,BC2 ) Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 6 9 8 Unit pF pF pF
Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 3.3V, Ta = 25 o C
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = - 40 ~ 85o C , VCC = 2.7V~ 3.6V, unless otherwise noted ) (1) MEASUREMENT CONDITIONS
Input pulse level ...................... VIH = 2.2V, VIL = 0.4V Input rise and fall time .............. 5ns Reference level ........................ VOH = 1.5V, VOL = 1.5V Output loads ............................ Fig.1,CL = 30pF CL = 5pF ( for ten, tdis ) + Transition is measured _ 500mV from steady state voltage. ( for ten, tdis )
1TTL DQ
MITSUBISHI LSIs
CL ( Including scope and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits Symbol Parameter M5M51016B -12VL,-12VLL Min Typ Max 120 120 120 120 120 60 40 40 40 40 10 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCR ta(A) ta(BC1) ta(BC2) ta(CS) ta(OE) tdis(BC1) tdis(BC2) tdis(CS) tdis(OE) ten(BC1) ten(BC2) ten(CS) ten(OE) tv(A)
Read cycle time Address access time Byte control 1 access time Byte control 2 access time Chip select access time Output enable access time Output disable time after BC1 high Output disable time after BC2 high Output disable time after CS low Output disable time after OE high Output enable time after BC1 low Output enable time after BC2 low Output enable time after CS high Output enable time after OE low Data valid time after address
(3) WRITE CYCLE
Limits M5M51016B -12VL,-12VLL Max Min Typ 120 85 0 100 100 100 100 45 0 0 40 40 5 5
Symbol
Parameter
Unit
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2 ) tsu(CS) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Write cycle time Write pulse width Address set up time Address set up time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select set up time Data set up time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
tCR A0~15 ta(A) ta (BC1) or ta (BC2)
(Note 3) (Note 3)
MITSUBISHI LSIs
tv (A)
BC1 and/or BC2
tdis (BC1) or tdis (BC2) CS
(Note 3)
ta (CS) ta (OE) ten (OE) tdis (CS)
(Note 3)
OE
(Note 3)
ten (BC1) ten (BC2) ten (CS)
tdis (OE)
(Note 3)
DQ1~16
W = "H" level
DATA VALID
Write cycle (W control mode)
tCW A0~15
tsu (BC1) or tsu (BC2) BC1 and/or BC2
(Note 3) (Note 3)
CS
(Note 3)
tsu (CS)
(Note 3)
tsu (A-WH) OE
tsu (A) W
tw (W)
trec (W)
tdis (W) tdis (OE) DQ1~16 ten (W) DATA IN STABLE tsu (D) th (D)
ten(OE)
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
Write cycle ( BC control mode)
tCW A0~15 tsu (BC1) or tsu (BC2)
MITSUBISHI LSIs
tsu (A) BC1 and/or BC2
trec (W)
CS
(Note 3) (Note 5) (Note 3)
W
(Note 4) (Note 3) (Note 3)
tsu (D) DATA IN STABLE
th (D)
DQ1~16
Write cycle (CS control mode)
tCW A0~15
BC1 and/or BC2
(Note 3) (Note 3)
tsu (A) CS
tsu (CS)
trec (W)
(Note 5)
W
(Note 3)
(Note 4) (Note 3)
tsu (D) DATA IN STABLE
th (D)
DQ1~16
Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while CS high overlaps BC1 and/or BC2 low and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or rising edge of CS, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI ELECTRIC
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9 Jul ,1997
M5M51016BTP,RT-12VL-I, -12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta = - 40 ~ 85 o C, unless otherwise noted)
Symbol VCC (PD) VI (BC) VI (CS) Parameter Power down supply voltage Byte control input BC1 & BC2 Chip select input CS 2.7V < VCC(PD) VCC(PD) < 2.7V
VCC = 3V -VL 1) CS < 0.2V other inputs = 0 ~ 3V 2) BC1 & BC2 > Vcc 0.2V, -VLL CS > VCC 0.2V,other inputs=0~3V
MITSUBISHI LSIs
Test conditions
Min 2 2.0
Limits Typ
Max
Unit V V
0.6 0.2 100
V
ICC (PD)
Power down supply current
A 0.3
(Note 7)
20
Note7. ICC (PD) = 1A in case of Ta = 25 C
o
(2) TIMING REQUIREMENTS (Ta = - 40 ~ 85o C , unless otherwise noted )
Symbol tsu (PD) trec (PD) Parameter Power down set up time Power down recovery time Test conditions Min 0 5 Limits Typ Max Unit ns ms
(3) POWER DOWN CHARACTERISTICS BC control mode
VCC t su (PD) 2.7V 2.7V t rec (PD)
2.2V BC1 & BC2 BC1 & BC2 > VCC 0.2V
2.2V
CS control mode
VCC 2.7V 2.7V
CS
t su (PD)
t rec (PD)
0.2V CS < 0.2V
0.2V
MITSUBISHI ELECTRIC
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