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CXP829P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP829P60 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, fluorescent display panel controller/driver, I2C bus interface, remote control transmission circuit, remote control reception circuit, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. This LSI also provides sleep/stop functions which enable to lower power consumption. The CXP829P60 is the PROM-incorporated version of the CXP82960 with built-in mask ROM, and it is able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 80 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (122s at 32kHz operation) * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 2048 bytes (including fluorescent display area) * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 20s/16MHz) -- Serial interface Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel -- Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer 32kHz timer/counter -- Fluorescent display panel controller/driver High voltage drive output port of 28 pins (40V) Maximum of 196 segments display possible 1 to 16-digit dynamic display Dimmer function On-chip incorporated pull-down resistor Hardware key scan function Maximum of 12 x 8 key matrix supportable 2C bus interface --I -- Remote control transmission circuit Auto transmission for 1 to 32 bytes, restart function, carrier output function -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO * Interruption 16 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 80-pin plastic QFP
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95326-PP
Block Diagram
AVSS
AVREF
AVDD
INT0 INT1 INT2 INT3/NMI
2
T0 to T7 RAM
8
SPC 700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL 8 8
T8/S19 to T15/S12
8
PORT A
AN0 to AN7
8
A/D CONVERTER
TEX TX EXTAL XTAL RST VDD VSS Vpp
PA0 to PA7
S0 to S11 VFDP KR0 to KR7 RAM PROM 60K BYTES RAM 2048 BYTES
8
KEY SCAN
PORT B
12
FDP CONTROLLER/ DRIVER
PB0 to PB7
RMCO
BUFFER REMOCON OUT RAM FIFO
PORT C
8
PC0 to PC7
PORT D
CS0 SI0 SO0 SCK0 BUFFER RAM FIFO PRESCALER/ TIME BASE TIMER 2
SERIAL INTERFACE UNIT (CH0)
PORT E
SI1 SO1 SCK1
SERIAL INTERFACE UNIT (CH1)
EC
8 BIT TIMER/COUNTER 0
PORT F
SCL0 SCL1 SDA0 SDA1 2
I2C INTERFACE UNIT
ADJ
PORT G
-2-
RMC
REMOCON IN
INTERRUPT CONTROLLER
8
PD0 to PD7
6 2
PE0 to PE5 PE6 to PE7
32KHz TIMER/COUNTER
4
PF0 to PF3
TO
8 BIT TIMER 1
4
PG0 to PG3
CXP829P60
CXP829P60
Pin Assignment (Top View)
PE0/EC/INT0
PG3
PG2
PG1
PG0
TEX
Vpp
VDD
TX
T0
T1
T2
T3
T4
T5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5 PE6/RMCO PE7/TO/ADJ PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 T7 T8/S19 T9/S18 T10/S17 T11/S16 T12/S15 T13/S14 T14/S13 T15/S12 S11 S10 S9 S8 PD7/S7 PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 PD0/S0 VFDP PC7/KR7 PC6/KR6
AVREF
PF3/SDA1
EXTAL
TXAL
VSS
RST
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PF0/SCL0
PF1/SCL1
PF2/SDA2
Note) Vpp (Pin 75) must be connected to VDD.
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PC5/KR5
AVSS
T6
CXP829P60
Pin Description Pin code I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/ Analog input
Analog inputs to A/D converter. (8 pins)
PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving Serves as key return inputs when operating 12mA sync current. key scan with fluorescent display panel (FDP) Incorporation of pull-up segment signal (8 pins). resistor can be set through the software in a unit of 4 bits. (8 pins) Inputs for external interruption request. (4 pins) External event inputs for timer/counter.
PC0/KR0 to PC7/KR7
I/O/Input
PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5 PE6/RMCO PE7/TO/ADJ
Input/Input/Input Input/Input Input/Input Input/Input/Input Input/Input Input Output/Output Output/Output/ Output (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins)
Non-maskable interruption request input.
Remote control reception circuit input.
Carrier output of remote control transmission circuit. Output for the timer/counter rectangular waves, and 32kHz oscillation dividing frequency.
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CXP829P60
Pin code PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1
I/O Output/I/O (Port F) 4-bit output port, operating as N-ch open drain output for large current (12mA). (4 pins)
Functions Transfer clock I/Os for I2C bus interface. (2 pins) Transfer data I/Os for I2C bus interface. (2 pins)
Output/I/O
PG0 to PG3
I/O
(Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (4 pins) (Port D) 8-bit output ports. (8 pins) FDP segment signal outputs. (8 pins)
PD0/S0 to PD7/S7 S8 to S11 T8/S12 to T15/S19 T0 to T7 VFDP EXTAL XTAL TEX TX RST NC AVDD AVREF AVSS Vpp VSS
Output/Output Output Output/Output Output
FDP segment signal outputs. (4 pins) Outputs for FDP timing signals/segment signals. (8 pins) FDP timing signal outputs. FDP voltage supply.
Input Output Input Output Input
Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event counter, attach clock source to TEX, and open TX. Low-level active, system reset. NC. Under normal operation, connect to VDD. Positive power supply for A/D converter.
Input
Reference voltage input for A/D converter. A/D converter GND. Positive power supply for built-in PROM writing. Connect to VDD for normal operation. GND.
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CXP829P60
I/O Circuit Format for Pins Pin Port A
Pull-up resistor "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Port A direction "0" when reset Data bus RD (Port A) Port A input selection "0" when reset A/D converter
IP
Input protection circuit
Hi-Z
Input multiplexer Pull-up transistor approx. 100k
8 pins Port B
Pull-up resistor "0" when reset Port B data
PB1/CS0 PB3/SI0 PB6/SI1
Port B direction "0" when reset Data bus RD (Port B) CS0 SI0 SI1 Schmitt input
IP
Hi-Z
Pull-up transistor approx. 100k
3 pins Port B
Pull-up resistor "0" when reset SCK OUT Serial clock output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus
Not Schmitt input for SI0 and SI1.
PB2/SCK0 PB5/SCK1
IP
Hi-Z
Schmitt input
2 pins
RD (Port B) SCK in Pull-up transistor approx. 100k
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CXP829P60
Pin Port B
Pull-up resistor "0" when reset SO Serial data output enable
Circuit format
When reset
PB4/SO0 PB7/SO1
Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus IP
Hi-Z
2 pins Port C
RD (Port B)
Pull-up transistor approx. 100k
Pull-up resistor "0" when reset Port C data
2
PC0/KR0 to PC7/KR7
Port C direction "0" when reset Data bus RD (Port C)
1 IP
Hi-Z
8 pins PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC 5 pins PE5 1 pin Port E Port E
Key input signal
1 Large current 12mA
2 Pull-up transistor approx. 100k EC/INT0 INT1 INT2 INT3/NMI RMC Data bus RD (Port E)
Schmitt input IP
Hi-Z
Port E
IP RD (Port E)
Remote control transmission circuit
Data bus
Hi-Z
Port E output selection
PE6/RMCO
"0" when reset Port E data "1" when reset Data bus Output enable
High level
1 pin
RD (Port E)
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CXP829P60
Pin Port E
Circuit format
Internal reset signal Port E data "1" when reset TO ADJ16K1 00 01 10 11 MPX 2
When reset
PE7/TO/ADJ
ADJ2K1
Port E output selection (upper) Port E output selection (lower)
High level (with approx. 150k resistor when reset)
"00" when reset TO output enable
1 pin Port F
1 ADJ signal is a frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2 can be used for buzzer output. 2 Pull-up transistor approx. 150k.
SCL, SDA
PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1
I2C output enable ("0" when reset) Port F data "1" when reset Schmitt input SCL, SDA (I2C circuit) IP
Large current 12mA
Hi-Z
BUS SW To internal I2C pin (to SCL1 for SCL0)
4 pins Port B Port G
Pull-up resistor "0" when reset Port B, G data
PB0 PG0 to PG3
Port B, G direction "0" when reset Data bus RD (Port B or Port G) Pull-up transistor approx. 100k IP
Hi-Z
5 pins
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CXP829P60
Pin Port D
Circuit format
High voltage drive transistor Segment output data
When reset
PD0/S0 to PD7/S7
Output selection control signal ("0" when reset)
Hi-Z
Port D data
Data bus
8 pins
RD (Port D)
High voltage drive transistor
S8 to S11 T15/S12 to T8/S19 T0 to T7
Segment output data Timing output data Output selection control signal ("0" when reset)
Low level
Pull-down resistor
20 pins
VFDP
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop, and XTAL becomes High.
Oscillation
2 pins
XTAL
TEX TX
TEX
IP
IP
* Diagram shows circuit composition during oscillation.
2 pins
TX
* When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX becomes Low level and TX becomes High level.
Oscillation
Pull-up resistor
RST Low level 1 pins
IP Schmitt input
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CXP829P60
Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVDD AVSS Input voltage Output voltage Display output voltage VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL IOLC Low level total output current IOL Operating temperature Storage temperature Allowabl power dissipation 1 2 3 4 Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +13.0 AVSS to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 VDD - 40 to VDD + 0.3 -5 -15 -35 -40 -100 15 20 100 -10 to +75 -55 to +150 600 Unit V V V V V V V mA mA mA mA mA mA mA mA C C mW Incorporated PROM
(Vss = 0V reference) Remarks
As P channel transistor is open drain, VDD is reference. All pins excluding outputs3 (value per pin) Display outputs S0 to S11 (value per pin) Display outputs T0 to T7, and T8/S19 to T15/S12 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port (value per pin) Large current Port (value per pin)4 Total for all output pins
AVDD and VDD should be set to the same voltage. VIN and VOUT must not exceed VDD + 0.3V. Specifies output current of general-purpose I/O ports. The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
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CXP829P60
Recommended Operating Conditions Item Symbol Min. 4.5 Max. 5.5 Unit V
(Vss = 0V reference) Remarks Guaranteed operation range for high-speed mode (1/2, 1/4 frequency dividing clock) Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) or SLEEP mode Guaranteed operation range with TEX clock Guaranteed data hold range during STOP 4 5 1 Hysteresis input2 EXTAL3 1 Hysteresis input2 EXTAL3
3.5 Supply voltage VDD 2.7 2.5 Vpp Analog power supply High level input voltage AVDD VIH VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr
5.5
V
5.5 5.5
V V V V V V V V V C
Vpp = VDD 4.5 0.7VDD 0.8VDD 5.5 VDD VDD
VDD - 0.4 VDD + 0.3 0 0 -0.3 -10 0.3VDD 0.2VDD 0.4 +75
1 Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG). 2 Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1, SDA0, SDA1. 3 Specifies only during external clock input. 4 Vpp and VDD should be set to the same voltage. 5 AVDD and VDD should be set to the same voltage.
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CXP829P60
Electrical Characteristics DC Characteristics Item High level output current Symbol VOH Pins PA, PB, PC, PE6, PE7, PG PC, PF Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA Low level output current VOL VDD = 4.5V, IOL = 12.0mA (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 -0.5 0.1 -0.1 -1.5 40 -40 10 -10 -400 -50 VDD = 4.5V, VIL = 4.0V VDD = 4.5V VOH = VDD - 2.5V -3.3 -8 -20 Typ. Max. Unit V V V V V V V A A A A A A A mA mA
PF VDD = 4.5V, IOL = 3.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA IIHE IILE IIHT VDD = 5.5V, VIH = 5.5V EXTAL VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V TEX RST PA to PC1, PG1 S0 to S11 VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V
Input current
IILT IILR IIL
Display output current
IOH
S12/T15 to S19/T8, T0 to T7 S0 to S11, S12/T15 to S19/T8, T0 to T7 S8 to S11, S12/T15 to S19/T8, T0 to T7
Open drain output ILOL leakage current (P-CH Tr off state)
VDD = 5.5V VOL = VDD - 35V VFDP = VDD - 35V
-20
A
Pull-down resistance
RL
VDD = 5V VOD - VFDP = 30V
60
100
270
k
I/O IIZ leakage current Open drain output leakage current (N-ch Tr off state) I2C bus switch connection impedance (Output Tr off state)
PA to PC1, VDD = 5.5V VI = 0, 5.5V PG1
10
A
ILOH
PF
VDD = 5.5V, VOH = 5.5V
10
A
RBS
SCL0: SCL1 SDA0: SDA1
VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V
120
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CXP829P60
Item
Symbol
Pins
Conditions High speed mode operation (1/2 frequency dividing clock)
Min.
Typ.
Max.
Unit
IDD1
VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD SLEEP mode VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation PA to PC, PE0 to PE5, PG, PF, Clock 1MHz EXTAL, 0V for all pins excluding XTAL, measured pins TX, TEX, RST
36
55
mA
IDD2 Power supply current2
46
120
A
IDDS1
2.6
10
mA
IDDS2
9
30
A
IDDS3
30
A
Input capacity
CIN
10
20
pF
1 PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current when no resistance has been selected. 2 When all pins are open.
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CXP829P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input pulse width Event count input rise time, fall time 1 Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20
4tsys1
Min. 1 28
Typ.
Max. 16
Unit MHz ns
tXL tXH tCR tCF tEH tEL tER tEF
fC
200
ns ns
20
ms
32.768
kHz
tTL tTH tTR tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
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CXP829P60
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Min. Max. 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
tsys + 200
2tsys + 200 8000/fc
SCK0
Input mode Output mode
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
SI0
SCK input mode SCK output mode
SI0
SCK input mode SCK output mode
SO0
SCK input mode SCK output mode
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (CLC: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
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CXP829P60
Fig. 4. Serial transfer CH0 timing (CH0)
tWHCS
0.8VDD CS0 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP829P60
Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Ouput mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK1
Input mode Ouput mode
tsys + 100
8000/fc - 50 100 200
SI1
SCK1 input mode SCK1 ouput mode
SI1
SCK1 input mode SCK1 ouput mode
tsys + 200
100
SO1
SCK1 input mode SCK1 ouput mode
tsys + 200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (CLC: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP829P60
Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time 1 Symbol
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin SO1 SI1 SI1 SI1 1 2 2 Condition Min. Typ. 104 Max. Unit s s s
tLCY tLSU tLHD
tLCY is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1)
(SIOM1: 01E2H) is set to 104s. Note) The load condition for SO1 is 50pF + 1TTL.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
tLCY
SO1
Start bit
Output data bit
0.5VDD
tLCY/2 tLSU tLHD
0.8VDD SI1 Input data bit 0.2VDD
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CXP829P60
(3) A/D converter characteristics (Ta = -10 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage VZT1 VFT2 Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V -10 4910 160/fADC3 12/fADC3 AVREF AN0 to AN7 Operation mode AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VDD = AVDD = 4.5 to 5.5V AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 10 4970 Symbol Pin Condition Min. Typ. Max. 8 3 70 5030 Unit Bits LSB mV mV s s V V mA A
tCONV tSAMP
VREF VIAN IREF
AVREF current
Fig. 7. Definition of A/D converter terms
FFH FEH
Linearity error 01H 00H VZT Analog input VFT
1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEH).
CKS PCK1, PCK0
Digital conversion value
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
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CXP829P60
(4) Interruption, reset input Item
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit
External interruption High, Low level width
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig. 8. Interruption input timing
tIH tIL
0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only the falling edge.) 0.2VDD tIL tIH
Fig. 9. RST input timing
tRSL
RST 0.2VDD
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CXP829P60
(5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.
Fig.10. I2C bus transfer timing
SDA tBUF tR SCL tHD ; STA tSU ; STA P S tLOW tHD ; DAT tHIGH tSU ; DAT St tSU ; STO P tF tHD ; STA
Fig.11. Recommended circuit example for I2C device
I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C device RS RP RP
* Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * Serial resistance (Rs = 300 or less) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flash-over.
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CXP829P60
Appendix Fig. 12. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10 5
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00
0 0 0 470k (ii) (i)
P3
32.768kHz
Product List Option item Package ROM capacitance Reset pull-up resistance High voltage drive pin pull-down resistance Mask product CXP82940 CXP82948 CXP82952 CXP82960 80-pin plasitc QFP 40 Kbytes 48 Kbytes 52 Kbytes 60 Kbytes Existent/Non-existent PROM version CXP829P60Q-180-pin plasitc QFP PROM 60 Kbytes Existent Non-existent (PD0/S0 to PD7/S7) Existent (T0 to T15, S8 to S11)
Existent/Non-existent
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CXP829P60
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical)
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 frequency dividing mode 1/4 frequency dividing mode 10 1/16 frequency dividing mode SLEEP mode
30 1/2 frequency dividing mode 25
IDD - Supply current [mA]
IDD - Supply current [mA]
20
1
15
1/4 frequency dividing mode
32kHz mode (instruction) 0.1
10
32kHz SLEEP mode
5
1/16 frequency dividing mode SLEEP mode
3
4
5
6 0 2 4 6 8 10 12 14
VDD - Supply voltage [ V ]
16
Frequency [MHz]
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CXP829P60
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
- 24 -
0.8 0.2
1
24
16.3

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