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| CXD2598Q CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD2598Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, 1-bit DAC and analog low-pass filter on a single chip. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a builtin RAM Digital Signal Processor (DSP) Block * Playback mode supporting CAV (Constant Angular Velocity) * Frame jitter free * 0.5x to 4x continuous playback possible * Allows relative rotational velocity readout * Wide capture range playback mode * Spindle rotational velocity following method * Supports normal-speed to 4x speed playback * Supports variable pitch playback * The bit clock, which strobes the EFM signal, is generated by the digital PLL. * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4x speed playback * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and Sub-Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry correction circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high accuracy * Digital audio interface outputs * Digital level meter, peak meter * Bilingual compatible * VCO control mode * CD TEXT data demodulation Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment functions * Surf jump function supporting micro two-axis * Tracking filter: 6 stages Focus filter: 5 stages Digital Filter, DAC and Analog Low-Pass Filter Blocks * DBB (digital bass boost) function * Digital de-emphasis * Digital attenuation * 8fs oversampling digital filter * Adoption of tertiary noise shaper 100 pin QFP (Plastic) * S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB * THD + N: 0.007% or less (master clock: 384Fs, typ.) * Rejection band attenuation: -60dB or less * Double-speed playback supported Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD -0.3 to +7.0 V * Input voltage VI -0.3 to +7.0 V (Vss - 0.3V to VDD + 0.3V) * Output voltage VO -0.3 to +7.0 V (Vss - 0.3V to VDD + 0.3V) * Storage temperature Tstg -40 to +125 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V Note) AVDD includes XVDD and AVSS includes XVSS. Recommended Operating Conditions * Supply voltage VDD 2.7 to 5.5 V * Operating temperature Topr -20 to +75 C Note) The VDD for the CXD2598Q varies according to the playback speed selection. Playback speed 4x 2x 1x VDD[V] CD-DSP block 4.75 to 5.25 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 11 (Max.) 11 (Max.) 11 (Max.) VDD = VI = 0V fM = 1MHz pF pF pF DAC block I/O Pin Capacitance * Input capacitance CI * Output capacitance CO * I/O capacitance CI/O Note) Measurement conditions Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97Y14-PS CXD2598Q EMPHI PCMD LRCKI PCMDI EMPH VPCO WFCK WDCK Block Diagram XUGF V16M XTSL VCTL GFS C2PO BCKI BCK SYSM LRCK DAC Block TES1 TEST FSTIO C4M RFAC ASYI ASYO BIAS ASYE XPCK FILO FILI PCO CLTV MDP PWMI LOCK SENS DATA XLAT CLOK SCOR SBSO EXCK Clock Generator EFM demodulator Asymmetry Corrector Error Corrector D/A Interface Serial-In Interface Over Sampling Digital Filter 32K RAM Sub Code Processor Digital OUT PWM Timing Logic XRST RMUT LMUT XTAI XTAO 3rd-Order Noise Shaper PWM Digital PLL Digital CLV AOUT1 AIN1 CPU Interface Servo Auto Sequencer LOUT1 AOUT2 AIN2 LOUT2 Signal Processor Block MD2 DOUT SOUT SOCK XOLT SERVO Interface SCLK COUT SSTP Servo Block MIRR DFCT FOK SERVO DSP OPAmp Analog SW A/D Converter FOCUS SERVO TRACKING SERVO SLED SERVO PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR FFDR FRDR TFDR TRDR SFDR SRDR ATSK MIRR DFCT FOK SCSY SQSO SQCK RFDC CE TE SE FE VC IGEN ADIO -2- CXD2598Q Pin Configuration PCMDI PCMD LRCKI AVDD3 AVDD0 DOUT VPCO AVSS3 ASYO AVSS0 LRCK ASYE V16M VCTL CLTV RFAC BIAS VDD MD2 PCO VSS FILI FILO ASYI IGEN ADIO RFDC CE 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 BCK 81 BCKI 82 EMPH 83 EMPHI 84 XVDD 85 XTAI 86 XTAO 87 XVSS 88 AVDD1 89 AOUT1 90 AIN1 91 LOUT1 92 AVSS1 93 AVSS2 94 LOUT2 95 AIN2 96 AOUT2 97 AVDD2 98 RMUT 99 LMUT 100 TE SE 50 49 48 47 46 45 44 FE VC XTSL TES1 TEST VSS VDD 43 FRDR 42 FFDR 41 TRDR 40 TFDR 39 SRDR 38 SFDR 37 FSTIO 36 SSTP 35 MDP 34 LOCK 33 PWMI 32 FOK 31 DFCT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 WDCK SCOR COUT C2PO MIRR C4M -3- WFCK SQSO SOCK SQCK SYSM SOUT SBSO XUGF SCSY EXCK CLOK SENS XPCK XRST DATA XOLT SCLK ATSK XLAT GFS VDD VDD VSS VSS CXD2598Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol VDD VSS SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR C4M WDCK COUT MIRR VSS VDD DFCT FOK PWMI LOCK -- -- O O O O I I O I I I I I I O I I/O O O O O O O O O I/O I/O -- -- I/O I/O I I/O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- -- 1, 0 1, 0 1, 0 1, 0 I/O -- -- 1, 0 1, 0 1, 0 1, 0 Digital power supply. Digital GND. Servo block internal serial data output. Servo block internal serial data readout clock output. Servo block internal serial data latch output. Sub-Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. Sub P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. MNT0 or RFCK is output by switching with the command. XPCK output. MNT1 is output by switching with the command. GFS output. MNT2 or XROF is output by switching with the command. C2PO output. MNT3 or GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. 4.2336MHz output. In CAV-W mode and variable pitch mode, the 1/4 frequency division of V16M is output. Word clock output f = 2Fs. GRSCOR is output by switching with the command. Track count signal input/output. Mirror signal input/output. Digital GND. Digital power supply. Defect signal input/output. Focus OK signal input/output. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. -4- Description CXD2598Q Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Symbol MDP SSTP FSTIO SFDR SRDR TFDR TRDR FFDR FRDR VDD VSS TEST TES1 XTSL VC FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI RFAC AVSS3 CLTV FILO FILI PCO AVDD3 BIAS VCTL O I I/O O O O O O O -- -- I I I I I I I I I O -- I -- O I I -- I O I O -- I I I/O 1, Z, 0 Description Spindle motor servo control output. Disc innermost track detection signal input. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- -- Input/output of 2/3 frequency division for the XTAI pin. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital power supply. Digital GND. Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Analog -- Test pin. Do not connect anything. Analog GND. Operational amplifier constant current input. -- 1, 0 Analog power supply. EFM full-swing output (low = VSS, high = VDD). Asymmetry comparator voltage input. EFM signal input. -- Analog GND. Multiplier VCO1 control voltage input. Analog Master PLL filter output (slave = digital PLL). Master PLL filter input. 1, Z, 0 -- Master PLL charge pump output. Analog power supply. Asymmetry circuit constant current input. Wide-band EFM PLL VCO2 control voltage input. -5- CXD2598Q Pin No. 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol V16M VPCO VSS MD2 DOUT ASYE VDD LRCK LRCKI PCMD PCMDI BCK BCKI EMPH EMPHI XVDD XTAI XTAO XVSS AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT -- O I O -- -- O I O -- O O I O I/O O -- I O I -- O I O I O I O I I/O 1, 0 1, Z, 0 -- Description Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL clock input by switching with the command. Wide-band EFM PLL charge pump output. Digital GND. Digital Out on/off control (low = off, high = on). 1, 0 Digital Out output. Asymmetry circuit on/off (low = off, high = on). -- 1, 0 Digital power supply. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. 1, 0 D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) 1, 0 D/A interface. Bit clock output. D/A interface. Bit clock input. 1, 0 Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Inputs a high signal when emphasis is on, and a low signal when emphasis is off. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. -- Analog power supply. Left channel analog output. Left channel operational amplifier input. Left channel LINE output. -- -- Analog GND. Analog GND. Right channel LINE output. Right channel operational amplifier input. Right channel analog output. -- 1, 0 1, 0 Analog power supply. Right channel zero detection flag. Left channel zero detection flag. -6- CXD2598Q Notes) * PCMD is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window opens.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XRAOF is generated when the 32K RAM exceeds the 28F jitter margin. Monitor Pin Output Combinations Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT0 RFCK Output data XPCK MNT1 XPCK GFS MNT2 XROF C2PO MNT3 GTOP -7- CXD2598Q Electrical Characteristics 1. DC Characteristics Item Input voltage (1) High level input voltage Low level input voltage Input voltage (2) High level input voltage Low level input voltage Input voltage (3) High level input voltage Low level input voltage Input voltage (4) Input voltage Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) VIH (1) VIL (1) VIH (2) VIL (2) VIH (3) VIL (3) VIN (4) Analog input Vss VDD - 0.8 Vss VDD - 0.8 Vss VDD - 0.8 Vss 0.8VDD 0.2VDD VDD VDD 0.4 VDD 0.4 VDD 0.4 VDD 0.4 10 40 20 600 Schmitt input 0.8VDD 0.2VDD (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Conditions Min. 0.7VDD 0.3VDD Typ. Max. Unit Applicable pins V V V V V V V V V V V V V V V A A A A 1, 2 3, 11, 12 9 10 8 7 6 4, 9, 10 5 3 2, 12 1, 11 High level output voltage VOH (1) IOH = -2mA Low level output voltage VOL (1) IOL = 4mA High level output voltage VOH (2) IOH = -4mA Low level output voltage VOL (2) IOL = 8mA High level output voltage VOH (3) IOH = -6mA Low level output voltage VOL (3) IOL = 4mA High level output voltage VOH (4) IOH = -0.28mA VDD - 0.5 Low level output voltage VOL (4) IOL = 0.36mA ILI (1) ILI (2) ILI (3) ILI (4) VIN = VSS or VDD VIN = VSS or VDD VI = 1.5 to 3.5V VI = 0 to 5.0V Vss -10 -40 -20 -40 Input leak current (1) Input leak current (2) Input leak current (3) Input leak current (4) Applicable pins 1 SYSM, DATA, XLAT, PWMI, SSTP, XTSL, TEST, TES1, MD2, SCSY 2 SQCK, XRST, CLOK, ASYE 3 LRCKI, PCMDI, BCKI, EMPHI 4 ASYI, RFAC, CLTV, FILI, VCTL 5 SQSO, SBSO, SENS, ATSK, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTIO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SOUT, SOCK, XOLT 6 V16M 7 MDP, PCO, VPCO 8 FILO 9 VC, FE, SE, TE, CE 10 RFDC 11 EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK, PWMI, V16M, FSTIO 12 SCLK -8- CXD2598Q 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTAI pin (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTAI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTAI pin via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p -9- CXD2598Q (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (during input) COUT pulse width (during input) Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750 65 7.5 Unit MHz ns ns ns ns ns MHz ns kHz s tWCK tSU tH tD tWL fT tWT fT tWT Only when $44 and $45 are executed. 1/fCK tWCK tWCK CLOK DATA XLAT EXCK SQCK COUT tSU tH tD tWL tWT 1/fT SBSO SQSO tSU tH tWT - 10 - CXD2598Q (3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item BCK pulse width PCMDI setup time PCMDI hold time LRCK setup time Symbol Conditions Min. 94 18 18 18 tW(BCKI) tW(BCKI) Typ. Max. Unit ns ns ns ns tW tSU tH tSU BCKI VDD/2 tSU tH (PCMDI) (PCMDI) VDD/2 PCMDI tSU (LRCKI) LRCKI (4) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 Unit MHz ns s tSPW tDLS 31.3 15 - 11 - CXD2598Q (5) COUT, MIRR and DFCT pins Operating frequency Item (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Max. kHz kHz kHz Conditions 1 2 3 COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.12VDD to 0.26VDD * B 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 12 - CXD2598Q 1-bit DAC and LPF Block Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD Conditions 1kHz, 0dB data 1kHz, 0dB data (Using A-weighting filter) Crystal 384Fs 768Fs 384Fs 768Fs 96 96 Min. Typ. 0.0050 0.0045 100 100 Max. 0.0070 0.0065 dB Unit % S/N Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 12k AOUT1 (2) 680p 12k AIN1 (2) 150p LOUT1 (2) 22 100k Audio Analyzer 12k SHIBASOKU (AM51A) LPF external circuit diagram 768Fs/384Fs Rch DATA TEST DISC RF CXD2598Q Lch A Audio Analyzer B Block diagram of analog characteristics measurement (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage Load resistance Symbol VOUT RL 8 Min. Typ. 1.12 Max. Unit Vrms k Applicable pins 1 1 Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB. Applicable pins 1 LOUT1, LOUT2 - 13 - CXD2598Q Contents 1. CPU Interface 1-1. CPU Interface Timing ..........................................................................................................................15 1-2. CPU Interface Command Table ..........................................................................................................15 1-3. CPU Command Presets ......................................................................................................................26 1-4. Description of SENS Signals ...............................................................................................................32 1-5. Description of Commands ...................................................................................................................34 2. Subcode Interface 2-1. P to W Subcode Readout ....................................................................................................................62 2-2. 80-bit Sub-Q Readout..........................................................................................................................62 3. Description of Modes 3-1. CLV-N Mode ........................................................................................................................................69 3-2. CLV-W Mode .......................................................................................................................................69 3-3. CAV-W Mode.......................................................................................................................................69 3-4. VCO-C mode .......................................................................................................................................70 4. Description of Other Functions 4-1. Channel Clock Recovery by Digital PLL Circuit...................................................................................73 4-2. Frame Sync Protection ........................................................................................................................75 4-3. Error Correction ...................................................................................................................................75 4-4. DA Interface.........................................................................................................................................76 4-5. Digital Out ............................................................................................................................................78 4-6. Servo Auto Sequence..........................................................................................................................82 4-7. Digital CLV...........................................................................................................................................90 4-8. CD-DSP Block Playback Speed ..........................................................................................................91 4-9. DAC Block Playback Speed ................................................................................................................91 4-10. DAC Block Input Timing ....................................................................................................................92 4-11. Description of DAC Block Functions..................................................................................................92 4-12. LPF Block ..........................................................................................................................................97 4-13. Asymmetry Correction .......................................................................................................................98 4-14. CD TEXT Data Demodulation ...........................................................................................................99 5. Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System..................................................................101 5-2. Digital Servo Block Master Clock (MCK) ...........................................................................................102 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...........................................................103 5-4. E:F Balance Adjustment Function .....................................................................................................104 5-5. FCS Bias Adjustment Function..........................................................................................................104 5-6. AGCNTL Function .............................................................................................................................106 5-7. FCS Servo and FCS Search .............................................................................................................108 5-8. TRK and SLD Servo Control .............................................................................................................109 5-9. MIRR and DFCT Signal Generation ..................................................................................................110 5-10. DFCT Countermeasure Circuit ........................................................................................................111 5-11. Anti-Shock Circuit ............................................................................................................................111 5-12. Brake Circuit ....................................................................................................................................112 5-13. COUT Signal ...................................................................................................................................113 5-14. Serial Readout Circuit......................................................................................................................113 5-15. Writing to Coefficient RAM ..............................................................................................................114 5-16. PWM Output ....................................................................................................................................114 5-17. Servo Status Changes Produced by LOCK Signal ........................................................................115 5-18. Description of Commands and Data Sets .......................................................................................115 5-19. List of Servo Filter Coefficients ........................................................................................................137 5-20. Filter Composition............................................................................................................................139 5-21. TRACKING and FOCUS Frequency Response ..............................................................................145 6. Application Circuit ...................................................................................................................................146 Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus - 14 - TRK: SLD: DFCT: Tracking Sled Defect CXD2598Q 1. CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 16 bits 20 bits 32 bits 32 bits 28 bits 24 bits 28 bits 20 bits 20 bits - 15 - Command Table ($0X to 1X) Data 1 Data 2 Data 3 Data 4 D8 D7 -- -- -- -- -- -- -- -- D6 D5 D4 -- D3 D2 D1 D0 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT -- -- FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- FOCUS SEACH VOLTAGE UP -- ANTI SHOCK ON -- ANTI SHOCK OFF -- BRAKE ON -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- -- -- TRACKING GAIN UP FILTER SELECT 2 -- --: Don't care CXD2598Q D12 D11 -- -- -- D10 D9 -- Data 5 D16 D15 -- -- -- D14 D13 -- D18 0 -- D17 Address Register Command D23 to D20 D19 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- FOCUS CONTROL 0000 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 1 0 -- -- -- -- -- 0 -- 1 1 -- 0 -- -- -- -- -- -- -- -- -- 1 1 1 0 0 - 16 - 1 0 -- -- 1 TRACKING CONTROL 0001 -- -- -- -- Command Table ($2X to 3X) Data 1 D18 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 Data 4 D8 -- -- -- -- -- -- -- D7 -- -- -- -- D6 -- -- -- -- D5 -- -- -- -- D4 -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) SLED KICK LEVEL (2 x basic value) -- SLED KICK LEVEL (3 x basic value) -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- -- -- -- -- -- -- -- -- -- -- -- D14 D13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 1 -- -- -- -- Data 1 D18 0 0 0 0 1 1 1 0 0 1 0 0 D17 D16 1 1 1 0 0 1 0 0 -- -- -- -- -- -- -- -- D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE Data 2 Data 3 Data 4 Data 5 Address Register Command D23 to D20 D19 0 0 1 1 2 TRACKING MODE 0010 -- -- -- - 17 - -- Address Register Command D23 to D20 D19 0 0 3 SELECT 0011 0 0 CXD2598Q Command Table ($340X) Address 3 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN CXD2598Q 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K00) SLED INPUT GAIN D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0000 1 1 1 1 1 1 1 1 - 18 - 3 SELECT 0011 0100 Command Table ($341X) Address 3 D10 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L 1 0 KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H 1 1 KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L 1 CXD2598Q KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K11) FOCUS OUTPUT GAIN 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0001 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 Command Table ($342X) Address 3 Data 1 Data 2 D4 D3 D2 D1 D0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K2E) NOT USED 1 1 KRAM DATA (K2F) NOT USED 1 CXD2598Q D8 D7 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D6 D5 0 1 0 1 0 1 0 1 0 1 0 1 0 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0010 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 Command Table ($343X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED 1 CXD2598Q 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 KRAM DATA (K30) SLED INPUT GAIN (when SFSK = 1 TGup2) Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0011 1 1 1 1 1 1 1 1 - 21 - 3 SELECT 0011 0100 Command Table ($344X) Address 3 Data 2 D4 D3 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when THSK = 1 TGup2) KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4E) NOT USED 1 1 KRAM DATA (K4F) NOT USED 1 CXD2598Q D2 D1 D0 D10 D7 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D6 D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 D9 D8 Address 4 Data 1 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0100 1 1 1 1 1 1 1 1 - 22 - 3 SELECT 0011 0100 Command Table ($348X to 34FX) Address 2 Data 1 Data 2 D8 D7 0 0 0 0 0 0 0 0 DOUT Booster Surf Brake Booster 0 0 0 0 Data 3 D4 D3 D2 D1 D0 -- FB5 FB4 FB6 TV6 TV5 TV4 TV7 FB3 TV3 FB2 FB1 TV2 TV1 -- TV0 FCS Bias Limit FCS Bias Data Traverse Center Data --: Don't care 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 PGFS, PFOK, RFAC Data 3 D12 D11 PGFS1 PGFS0 RFOK1 RFOK0 A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT D SEL EN b8 EN1 DMUT WOD EN EN2 SFBK1 SFBK2 0 0 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 0 0 0 0 0 0 0 0 0 0 Data 2 D7 D6 D5 0 THBON FHBON TLB1ON FLB1ON TLB2ON 0 0 0 Data 1 D11 1 0 1 FB9 TV9 TV8 0 FB8 FB7 1 0 0 1 1 1 D10 D9 D8 0 0 0 0 0 0 0 0 0 0 D10 D9 0 0 1 0 1 0 D17 D15 1 0 0 0 1 1 1 Address 2 D15 D14 D13 D12 1 0 0 1 1 0 1 1 1 1 1 1 0 0 D14 D13 D16 Address 1 D18 Register Command D23 to D20 D19 3 SELECT 0011 0 - 23 - FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 CXD2598Q Command Table ($35X to 3FX) Data 1 Data 4 D4 D3 D2 D1 D0 FCS search, AGF TRK jump, AGT D17 0 FT1 TDZC DTZC TJ5 TJ4 TJ3 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 TJ2 TJ1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 1 SFID SFSK THID THSK 0 0 TLD2 TLD1 TLD0 0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 1 0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 0 1 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 0 0 0 0 1 0 1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D16 D15 D14 D13 D12 D11 D7 D6 D5 D10 D9 D8 Data 2 Data 3 Address D18 1 1 1 0 0 0 0 1 1 1 1 Register Command D23 to D20 D19 0 0 0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel 0 Serial data read out FCS Bias, Gain, Surf jump/brake SJHD INBK MTI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter LKIN COIN MDFI MIRI XT1D Filter ASFG FTQ LPAS 0 0 AGHF ASOT Clock, others 1 1 3 SELECT 0011 1 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT BTS1 BTS0 MRC1 MRC0 - 24 - F1NM F1DM F3NM F3DM TINM TIUM T3NM T3UM DF1S TLCD 1 1 1 1 CXD2598Q Command Table ($4X to EX) Data 1 D0 0 AS2 0 0 MT0 LSSL AS3 AS1 MT3 -- MT2 MT1 -- -- AS0 0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 -- Data 2 Data 3 Data 4 Address D1 0 Register Command D3 D2 4 Auto sequence 0 1 5 0 TR2 0 0 0 0 1 TR3 TR1 0 -- 0 0 -- TR0 0 Blind (A, E), Brake (B), Overflow (C, G) 0 1 -- -- 6 1 SD2 0 0 KF0 0 0 SD3 SD1 KF3 KF2 KF1 SD0 0 Sled KICK, BRAKE (D), KICK (F) 0 1 -- -- -- -- 7 1 256 64 32 128 1 32768 16384 8192 2048 1024 512 4096 Auto sequence (N) track jump count setting 0 1 16 8 4 2 1 8 0 KSL3 KSL2 0 1 0 VARI ON Mute ATT 32768 16384 2048 1024 512 8192 4096 256 VARI USE 1 1 DSPB ASEQ ON/OFF ON/OFF 1 BiliGL BiliGL DAC FLFC XWOC MAIN SUB EMO 0 MODE specification 1 0 VCO CD- DOUT DOUT VCO WSEL ASHS SOCT0 SEL1 ROM Mute Mute-F SEL2 KSL1 KSL0 0 0 0 XVCO2 THRU 0 PLM3 PLM2 PLM1 PLM0 ATTCH ATD10 ATD9 ATD8 SEL 9 Function specification 1 0 DAC SYCOF ATT - 25 - 1 1 128 0 0 1 0 CM3 CM2 CM1 1 0 TB VP7 TP CLVS Gain VP6 0 VP5 VP4 VP3 CM0 EPWM SPDC ICAP A Audio CTRL 1 0 PCT1 PCT2 MCSL SOC2 DCOF FMUT BSBST BBST B Traverse monitor counter setting 1 0 64 32 16 8 4 2 1 C Spindle servo coefficient setting 1 1 Gain Gain Gain Gain Gain Gain PCC1 PCC0 SFP3 MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 SFP2 VP2 SFSL VC2C SFP1 VP1 SFP0 SRP3 SRP2 SRP1 SRP0 VP0 HIFC LPWR VPON VP CTL1 VP CTL0 Gain Gain CAV1 CAV0 0 0 0 INV VPCO --: Don't care D CLV CTRL 1 1 E SPD mode 1 1 CXD2598Q Command Table ($4X to EX) cont. Data 5 Data 1 Data 2 D3 ERC4 0 0 DAC DAC ZMUT ZDPL SMUTL SMUTR 0 ATD2 ATD1 ATD0 -- -- -- 0 0 0 DIV4 ATD7 ATD6 ATD5 ATD4 ATD3 0 -- LRMIX MTSL1 MTSL0 SCOR SCSY SOCT1 TXON TXOUT OUTLI OUTL0 FSTIN SEL 0 OUTL2 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 Data 3 Data 4 D0 0 0 Data 6 Data 7 Register Command Address 8 MODE specification 1000 9 Function specification 1001 A Audio CTRL 1010 B Traverse monitor counter setting 1011 C Spindle servo coefficient setting EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 --: Don't care 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 1 Data 2 D16 D15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- Address 2 D17 D15 0 0 0 D16 D14 D13 D12 D11 -- -- -- D14 D13 D12 D11 -- -- -- -- -- -- -- -- -- -- D14 D13 D12 0 1 0 D11 D10 D9 D8 D7 D6 -- -- -- D18 0 0 0 Data 1 D18 0 0 0 D17 D16 0 0 0 D17 Data 3 Data 4 D5 -- -- -- Data 4 Data 3 D10 -- D9 -- Address 3 D10 D9 D8 D7 D8 -- D7 -- D6 -- D5 -- Data 1 D6 D5 D4 See "Coefficient ROM Preset Values Table". D3 D4 -- D3 -- D4 -- -- -- D3 -- -- -- Data 5 D2 -- -- -- D1 -- -- -- Data 5 D2 -- D0 -- Data 2 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care CXD2598Q D0 -- SLED KICK LEVEL (1 x basic value) (Default) D0 -- -- -- FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF - 26 - D18 1 Address Register Command D23 to D20 D19 0 FOCUS CONTROL 0000 0 1 TRACKING CONTROL 0001 0 2 TRACKING MODE 0010 0 Address Register Command D23 to D20 D19 0011 0 Address 1 3 SELECT D23 to D20 D19 0011 0 Command Preset Table ($348X to 34FX) Address 2 D17 D14 0 0 1 1 0 0 1 Address 2 D15 D14 D13 D12 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 Data 1 Data 2 D4 0 0 0 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Data 3 D2 0 0 0 D1 0 0 0 D0 0 0 0 FCS Bias Limit FCS Bias Data Traverse Center Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 DOUT Booster Surf Brake Booster 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 D12 1 1 1 1 1 1 1 0 0 D16 D15 D11 D10 D9 D8 D7 D3 D2 D1 D0 PGFS, PFOK, RFAC D6 D5 D4 Data 1 Data 2 Data 3 Address 1 D18 Register Command D23 to D20 D19 3 SELECT 0011 0 - 27 - CXD2598Q Command Preset Table ($35X to 3FX) Data 1 Data 2 D12 D11 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter Filter Clock, others D10 D9 D8 1 0 1 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Data 3 D17 D15 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 D14 D13 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 D16 Data 4 Address D18 1 1 1 0 0 0 0 1 1 1 1 Register Command D23 to D20 D19 0 0 0 1 1 3 SELECT 0011 1 1 - 28 - 1 1 1 1 CXD2598Q Command Preset Table ($4X to EX) --: Don't care Data 1 D0 0 0 0 0 0 0 -- -- -- 0 0 0 0 0 0 0 -- D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 2 Data 3 Data 4 Address D1 0 Register Command D3 D2 4 Auto sequence 0 1 5 Blind (A, E), Brake (B), Overflow (C, G) 0 0 0 1 0 0 0 -- -- 0 0 0 0 0 1 0 1 1 -- -- 6 Sled KICK, BRAKE (D), KICK (F) 0 1 0 1 0 0 0 -- 0 0 0 0 0 1 1 0 1 -- -- -- 7 Auto sequence (N) track jump count setting 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 8 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 MODE specification 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 9 Function specification 1 0 - 29 - 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Data 5 Data 1 Data 2 Data 3 Data 4 D3 0 0 0 0 0 A Audio CTRL 1 0 B Traverse monitor counter setting 1 0 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Spindle servo coefficient setting 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 Data 6 0 0 0 0 0 0 0 0 0 1 0 0 Data 7 1 0 0 D CLV CTRL 1 1 E SPD mode 1 1 Register Command Address D2 0 0 0 0 0 D1 0 0 0 0 0 D0 0 0 0 0 0 D3 0 0 0 -- 0 D2 0 0 0 -- 0 D1 0 0 0 -- 0 D0 0 0 0 -- 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 8 MODE specification 1000 9 Function specification 1001 A Audio CTRL 1010 B Traverse monitor counter setting 1011 CXD2598Q C Spindle servo coefficient setting 1100 CXD2598Q Fix indicates that normal preset values should be used. - 30 - CXD2598Q - 31 - CXD2598Q 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX ASEQ = 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 FZC AS TZC SSTP AGOK XAVEBSY TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS Count STOP SSTP XBUSY FOK 0 GFS COMP COUT OV64 0 Output data length -- -- -- -- -- -- 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits -- -- -- -- -- -- -- -- -- -- $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. - 32 - CXD2598Q Description of SENS Signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set by Reg.B. High when Reg.B is latched, low when COUT is counted for the initial Reg.B number. Counts the number of tracks set by Reg.B. High when Reg.B is latched, toggles each time COUT is counted for the Reg.B number. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. COUT OV64 - 33 - CXD2598Q 1-5. Description of Commands The meaning of the data for each address is explained below. $4X commands Register name 4 AS3 Data 1 Command AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move AS3 0 0 0 1 1 1 1 AS2 0 1 1 0 0 1 1 AS1 0 0 1 0 1 0 1 AS0 0 RXF 1 RXF RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the Focus-On command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track Jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To disable the MAX timer, set the MAX timer value to 0. $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms - 34 - CXD2598Q $6X commands Register name 6 SD3 Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) Data 1 KICK (D) SD2 SD1 SD0 SD3 23.2ms 11.6ms KF3 Data 2 KICK (F) KF2 KF1 KF0 SD1 5.8ms 2.9ms SD0 2.9ms 1.45ms SD2 11.6ms 5.8ms KF3 0.72ms KF2 0.36ms KF1 0.18ms KF0 0.09ms $7X commands Auto sequence track jump count setting Command Auto sequence track jump count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N-track jump is executed, M when an M-track move is executed and the jump count when fine search is executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. - 35 - CXD2598Q $8X commands Command MODE specification Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 D0 CD- DOUT DOUT VCO VCO WSEL ASHS SOCT0 ROM Mute Mute-F SEL1 SEL2 Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Command bit DOUT Mute F = 1 DOUT Mute F = 0 Processing When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DOUT Mute DOUT Mute F DOUT output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - dB 0dB OFF DA output for 48-bit slot 0dB - dB 0dB - dB 0dB - dB See mute conditions (1) and (3) to (5) under $AX commands for other mute conditions. - 36 - CXD2598Q Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit ASHS = 0 ASHS = 1 Function The command transfer rate from the auto sequencer to the DSSP block is set to normal speed. The command transfer rate from the auto sequencer to the DSSP block is set to half speed. See "4-8. CD-DSP Block Playback Speed" for settings. Command bit SOCT0 0 1 1 SOCT1 -- 0 1 Processing Sub-Q is output from the SQSO pin. Various signals are output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) --: Don't care Command MODE specification Data 2 D3 D2 D1 D0 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 VCO VCO ASHS SOCT0 SEL1 SEL2 See above. Command bit VCOSEL1 = 0 VCOSEL1 = 1 Processing Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed. Command bit KSL3 0 0 1 1 KSL2 0 1 0 1 Processing Output of multiplier PLL VCO1 is 1/1 frequency-divided. Output of multiplier PLL VCO1 is 1/2 frequency-divided. Output of multiplier PLL VCO1 is 1/4 frequency-divided. Output of multiplier PLL VCO1 is 1/8 frequency-divided. - 37 - CXD2598Q Command bit VCOSEL2 = 0 VCOSEL2 = 1 Processing Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed. Command bit KSL1 0 0 1 1 KSL0 0 1 0 1 Processing Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided. Command D3 MODE specification 0 0 Data 4 D2 D1 VCO2 THRU D0 0 D3 ERC4 Data 5 D2 D1 D0 D3 Data 6 D2 D1 D0 SCOR SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 SEL See the previous page. Command bit VCO2 THRU = 0 VCO2 THRU = 1 V16M is output. Processing Wide-band EFM PLL clock can be input from the V16M pin. This command sets internal or external connection for the VCO2 used during CAV-W mode and variable pitch mode. Command bit ERC4 = 0 ERC4 = 1 Processing C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1. Command bit SCOR SEL = 0 SCOR SEL = 1 WDCK signal is output. Processing GRSCOR (protected SCOR) is output. Used when outputting GRSCOR from the WDCK pin. - 38 - CXD2598Q Command bit SCSY = 0 SCSY = 1 No processing. Processing GRSCOR (protected SCOR) synchronization is applied again. Used to resynchronize GRSCOR. The rising edge signal of this command bit is used internally, so when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR is the crystal accuracy SCOR signal obtained by removing the motor wow component. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (Same as when SCSY = 1 is sent by the $8X command.) Command bit TXON = 0 TXON = 1 Processing When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1. See "4-14. CD TEXT Data Demodulation". Command bit TXOUT = 0 TXOUT = 1 Processing Various signals except for CD TEXT are output from the SQSO pin. CD TEXT data is output from the SQSO pin. See "4-14. CD TEXT Data Demodulation". Command bit OUTL1 = 0 OUTL1 = 1 Processing XPCK, C4M, WDCK and FSTO are output. V16M is output when VCO2 THRU = 0. XPCK, C4M, WDCK and FSTO outputs are set to low. V16M output is set to low when VCO2 THRU = 0. Command bit OUTL0 = 0 OUTL0 = 1 Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are set to low. - 39 - CXD2598Q Command Data 7 D3 D2 0 D1 OUTL2 D0 0 MODE FSTIN specification Command bit FSTIN = 0 Processing Servo block clock switching uses the internal connection. (Preset) The clock with 2/3 frequency division for the XTLO pin is input to the servo block. The FSTIO pin functions as an output pin for monitoring the servo block clock. Servo block clock switching uses external input. The FSTIO pin functions as an input pin. Input the servo block clock from the FSTIO pin. FSTIN = 1 Command bit OUTL2 = 0 OUTL2 = 1 WFCK is output. WFCK is set to low. Processing $9X commands Command Function specification Data 1 D3 1 D2 D1 D0 1 D3 BiliGL MAIN D2 BiliGL SUB Data 2 D1 FLFC D0 XWOC DSPB A.SEQ ON-OFF ON-OFF Command bit DSPB = 0 DSPB = 1 Processing Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) FLFC is normally 0. Set FLFC to 1 in CAV-W mode for any playback speed. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels, respectively, for STEREO. - 40 - CXD2598Q Command bit XWOC = 0 XWOC = 1 DAC sync window opens. DAC sync window does not open. Processing This is used to resynchronize the DAC. Command Function specification Data 3 D3 DAC EMPH D2 DAC ATT D1 SYCOF D0 0 Command bit DAC EMPH = 1 DAC EMPH = 0 Processing Applies digital de-emphasis. The emphasis constants are 1 = 50s and 2 = 15s when Fs = 44.1kHz. Turns digital de-emphasis off. Command bit DAC ATT = 1 DAC ATT = 0 Processing Identical digital attenuation control is used for both the left and right channels. When common attenuation data is specified, the attenuation values for the left channel are used. Independent digital attenuation control is used for the left and right channels. Command bit SYCOF = 1 SYCOF = 0 LRCK asynchronous mode. Normal operation. Processing Set SYCOF = 0 in advance when setting the XWOC command of $9 to 0. - 41 - CXD2598Q Command Function specification Data 4 D3 PLM3 D2 PLM2 D1 PLM1 D0 PLM0 * DAC play mode By controlling these command bits, the DAC output left channel and right channel can be output in 16 different combinations of left (L) channel, right (R) channel, left + right (L + R) channel, and mute. The relationship between the commands and the outputs is shown in the table below. PLM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PLM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PLM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PLM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Left channel output Right channel output Mute L R L+R Mute L R L+R Mute L R L+R Mute L R L+R Mute Mute Mute Mute L L L L R R R R L+R L+R L+R L+R Remarks Mute Reverse Stereo Mono Note) The output data of L + R is (L + R)/2 to prevent overflow. - 42 - CXD2598Q Command Function specification Data 5 D3 DAC SMUTL D2 DAC SMUTR D1 ZMUT D0 ZDPL Command bit DAC SMUTL = 1 DAC SMUTL = 0 Left channel soft mute is on. Left channel soft mute is off. Processing Command bit DAC SMUTR = 1 DAC SMUTR = 0 Right channel soft mute is on. Right channel soft mute is off. Processing Command bit ZMUT = 1 ZMUT = 0 Zero detection mute is on. Zero detection mute is off. Processing Command bit ZDPL = 1 ZDPL = 0 Processing LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted. See "Mute flag output" for the mute flag output conditions. Command Function specification Data 6 D3 0 D2 0 D1 0 D0 0 D3 DIV4 D2 0 Data 7 D1 0 D0 0 This switches the digital PLL master clock. Either the conventional mode or the 2/3 mode (2/3 of the conventional clock) can be selected. Command bit DIV4 = 0 DIV4 = 1 Processing Digital PLL master clock, conventional mode. (Preset) Digital PLL master clock, 2/3 mode. Note) Do not set DIV4 = 1 when DSPB = 0. - 43 - CXD2598Q $AX commands Command Audio CTRL Data 1 D3 VARI ON D2 VARI USE D1 Mute D0 ATT D3 PCT1 D2 PCT2 Data 2 D1 MCSL D0 SOC2 Command bit VARION = 0 VARION = 1 Command bit VARIUSE = 0 Processing Variable pitch mode is off. (The internal clock uses the crystal reference.) Variable pitch mode is on. (The internal clock uses the VCO2 reference.) Processing Set VARIUSE = 0 when not using variable pitch mode. VARIUSE = 1 Set VARIUSE = 1 when using variable pitch mode. See "$DX commands" for the variable pitch range and example of use. Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off. -12dB Mute conditions (1) When register A mute = 1. (2) When Digital Out is on (MD2 pin = 1) and register 8 DOUT Mute F = 1. (3) When GFS stays low for 35 ms or more (during normal-speed). (4) When register 9 BiliGL MAIN = Sub = 1. (5) When register A PCT1 = 1 and PCT2 = 0. (1) to (3) perform zero-cross muting with a 1ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain x 0dB x 0dB Mute x 0dB ECC error correction ability C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Description of level meter mode (see Timing Chart 1-4.) * When the LSI is set to this mode, it performs digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub-Q data (see "2. Subcode Interface"). The last 16 bits are LSB first, and consist of 15-bit PCM data (absolute values) and an L/R flag. The final bit (L/R flag) is high when the PCM data is from the left channel and low when the data is from the right channel. * The PCM data is reset and the L/R flag is reversed after one readout. Then the maximum value is measured until the next readout. - 44 - CXD2598Q Description of peak meter mode (see Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is reset in the LSI internal register. In other words, the PCM maximum value register is not reset by the readout. * To reset the PCM maximum value register, set PCT1 = PCT2 = 0 or set the Mute command of $AX to 1. * The Sub-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. * The final bit (L/R flag) of the 96-bit data is normally 0. * The pre-value hold and average value interpolation data are fixed to level (- ) for this mode. Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz) Note) See "4-9. DAC Block Playback Speed". Command bit SOC2 = 0 SOC2 = 1 Processing The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. SENS output switching * This command is used to output the SQSO pin signal from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. - 45 - CXD2598Q Command Audio CTRL Data 3 D3 DCOF D2 FMUT D1 BSBST D0 BBSL Command bit DCOF = 1 DCOF = 0 DC offset is off. DC offset is on. Processing Set DC offset to off when zero detection mute is on. Command bit FMUT = 1 FMUT = 0 Forced mute is on. Forced mute is off. Processing Command bit BSBST = 1 BSBST = 0 Bass boost is on. Bass boost is off. Processing Command bit BBSL = 1 BBSL = 0 Bass boost is Max. Bass boost is Mid. Processing - 46 - CXD2598Q Command Audio CTRL Data 4 D3 D2 D1 D0 D3 Data 5 D2 D1 D0 D3 Data 6 D2 D1 D0 ATTCH ATD10 ATD9 ATD8 ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0 SEL Command bit ATTCH SEL = 1 ATTCH SEL = 0 Processing Right channel attenuation data can be set. Left channel attenuation data can be set. Command bit ATD10 to 0 Attenuation data. Meaning The attenuation data consists of 11 bits each for the left and right channels, and the DAC ATT bit can be used to control the left and right channels with common attenuation data. When common attenuation data is specified, the left channel attenuation values are used. Attenuation data 400h 3FFh 3FEh : 001h 000h Audio output 0dB -0.0085dB -0.017dB : -60.206dB - The audio output from 001h to 400h is obtained using the following equation: Audio output = 20 log Attenuation data 1024 [dB] - 47 - CXD2598Q $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set to monitor the traverse status using the SENS outputs COMP and COUT. The monitor output is set as follows. Data 5 Command Traverse monitor count setting D3 0 D2 D1 D0 LRMIX MTSL1 MTSL0 Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MINT0 RFCK Output data XPCK MNT1 XPCK GFS MNT2 XROF C2PO MNT3 GTOP Command bit LRMIX = 0 Processing LMUT and RMUT both operate normally. The AND signal of the left channel and right channel zero detection flags is output from the LMUT pin. The OR signal of the left channel and right channel zero detection flags is output from the RMUT pin. LRMIX = 1 - 48 - CXD2598Q $CX commands Command D3 Data 1 D2 D1 D0 D3 Data 2 D2 D1 D0 Gain Gain Gain Gain Gain Gain Spindle servo PCC1 PCC0 coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 CLV CTRL ($DX) * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB Gain CLVS * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV1 0 0 1 Gain DCLV0 0 1 0 GDCLV 0dB +6dB +12dB Command bit PCC1 0 0 1 1 PCC0 0 1 0 1 The VPCO signal is output. Processing The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high. * This command controls the VPCO pin signal. The VPCO output can be controlled with this setting. - 49 - CXD2598Q Command Data 3 D3 D2 D1 D0 D3 Data 4 D2 D1 D0 Spindle servo SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0 coefficient setting Command bit SFP3 to 0 Processing Sets the frame sync forward protection times. The setting range is 1 to F (Hex). Command bit SRP3 to 0 Processing Sets the frame sync backward protection times. The setting range is 1 to F (Hex). See "4-2. Frame Sync Protection" regarding frame sync protection. * The CXD2598Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to EDC7 from the SQSO pin and monitor this data using a microcomputer. The C1 and C2 error rate settings are sent one at a time by the $C commands by setting the SOCT0 and SOCT1 commands of $8 to 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses. Data 5 D3 D2 D1 D0 D3 Data 6 D2 D1 D0 Command Spindle servo EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 coefficient setting - 50 - CXD2598Q Error monitor commands Command bit EDC7 = 0 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 EDC7 = 1 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 Processing The [No C1 errors, pointer reset] count is output when 0. The [One C1 error corrected, pointer reset] count is output when 0. The [No C1 errors, pointer set] count is output when 0. The [One C1 error corrected, pointer set] count is output when 0. The [Two C1 errors corrected, pointer set] count is output when 0. The [C1 correction impossible, pointer set] count is output when 0. 7350-frame count cycle mode1 when 1. 73500-frame count cycle mode2 when 0. The [No C2 errors, pointer reset] count is output when 0. The [One C2 error corrected, pointer reset] count is output when 0. The [Two C2 errors corrected, pointer reset] count is output when 0. The [Three C2 errors corrected, pointer reset] count is output when 0. The [Four C2 errors corrected, pointer reset] count is output when 0. The [C2 correction impossible, pointer copy] count is output when 0. The [C2 correction impossible, pointer set] count is output when 0. 1 The value selected by C1 (EDC1 to EDC6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350 frames. 2 The value selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) is added to C1 and C2 and output every 73500 frames. $DX commands Data 1 Command CLV CTRL D3 0 D2 TB D1 TP D0 Gain CLVS See "$CX commands". Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. - 51 - CXD2598Q Command CLV CTRL Data 2 D3 VP7 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 D3 VP CTL1 Data 4 D2 VP CTL0 D1 0 D0 0 The settings in CAV-W mode are as follows. Command bit VP0 to 7 Command bit VPCTL1 0 0 1 1 VPCTL0 0 1 0 1 Sets the spindle rotational velocity. Processing Processing The setting of VP0 to VP7 is multiplied by 1. The setting of VP0 to VP7 is multiplied by 2. The setting of VP0 to VP7 is multiplied by 3. The setting of VP0 to VP7 is multiplied by 4. The above setting should be 0, 0 when not operating in the CAV-W mode. The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n xl 32 R: Relative velocity at normal speed = 1 n: VP0 to VP7 setting value 1: Multiple set by VPCTL0, 1 Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at (quadruple) speed Command bit VP0 to 7 = F0(H) ... VP0 to 7 = E0(H) ... VP0 to 7 = C0(H) 4 3.5 3 2.5 2 1.5 1 0.5 Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Values in parentheses are for when DSPB is 1. R - Relative velocity [multiple] DS PB =1 DSPB =0 F0 E0 VP0 to VP7 setting value [HEX] D0 C0 - 52 - CXD2598Q The settings in variable pitch mode are as follows. Command bit VPCTL1 to 0, VP7 to 0 Processing Sets the pitch for the variable pitch mode. The pitch setting can be expressed with the following equation. P= -n 10 [%] P: Pitch setting value n: VPCTL1 and VPCTL0, VP7 to VP0 setting value (two's complement, VPCTL1 = sign bit) Command bit VPCTL1 VPCTL0 VP7 to 0 00(H) 1 0 : FF(H) 00(H) 1 1 : FF(H) 00(H) 0 0 : FF(H) 00(H) 0 1 : E7(H) Pitch setting value [%] +51.2 to +25.7 +25.6 to +0.1 0.0 to -25.5 -25.6 to -48.7 Command setting example $D60080 : $D6FF80 $D600C0 : $D6FFC0 $D60000 : $D6FF00 $D60040 : $D6E740 The pitch setting range is from -48.7 to +51.2%. The plus pitch setting should not exceed the playback speed given in the Recommended Operating Conditions. An example of variable pitch mode commands is shown below. $A4XXXXX (Setting to enable variable pitch mode.) $ACXXXXX (Turns on variable pitch mode. The internal clock uses the VCO2 reference.) $D60A00 (Sets the pitch to +1.0%.) $D60000 (Sets the pitch to 0.0%.) $A4XXXXX (Turns off variable pitch mode. The internal clock uses the crystal reference.) - 53 - CXD2598Q $EX commands Command SPD mode Data 1 D3 CM3 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.1 Description Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA 1 See Timing Charts 1-6 to 1-12. When using the digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. This means that the CLVS mode cut-off frequency fc is 70Hz when the TB command of $D = 0 or 140Hz when the TB command of $D = 1. Command bit EPWM SPDC 0 0 0 1 0 0 0 1 0 0 ICAP 0 0 1 1 0 SFSL 0 0 0 0 0 VC2C 0 1 0 0 0 HIFC 0 1 1 1 1 LPWR VPON 0 0 0 0 0 0 0 1 1 1 INV VPCO 0 0 0 0 1 Mode CLV-N CLV-W CAV-W CAV-W Description Crystal reference CLV servo. Used for normal-speed playback in CLV-W mode.2 Spindle control with VP0 to VP7. Spindle control with the external PWM. VCO-C VCO control3 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. 3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode. - 54 - CXD2598Q Mode LPWR Command KICK Timing chart 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) CLV-N 0 BRAKE STOP KICK 0 CLV-W 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N CLV-W LPWR 0 0 1 0 1 Timing chart 1-11 1-12 1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1) Data 4 CAV-W 0 1 Command SPD mode D3 Gain CAV1 D2 Gain CAV0 D1 0 D0 INV VPCO See the previous page. Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with VP0 to VP7 in CAV-W mode. Note) This setting is not valid when controlling the spindle with the external PWM. - 55 - Timing Chart 1-3 LRCK 48 bit slot WDCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG - 56 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD2598Q Timing Chart 1-4 750ns to 120s 80 81 96 1 2 3 SQCK SQSO CRCF 15-bit peak-data Absolute value display, LSB first D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R Sub Q Data See "Sub Code Interface" Peak data L/R flag 2 3 1 2 3 - 57 - 96 clock pulses CRCF 16 bit R/L Peak data of this section 1 WFCK 96 clock pulses SQCK SQSO L/R CRCF 96 bit data Hold section Level Meter Timing CXD2598Q Timing Chart 1-5 1 1 2 3 2 3 WFCK 96 clock pulses 96 clock pulses SQCK - 58 - CRCF Measurement CRCF CRCF Measurement Measurement Peak Meter Timing CXD2598Q CXD2598Q Timing Chart 1-6 CLV-N mode LPWR = 0 KICK H Z (a) KICK Z MDP L (b) BRAKE MDP Z BRAKE STOP MDP (c) STOP Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 KICK H Z (a) KICK Z MDP L (b) BRAKE MDP Z BRAKE STOP MDP (c) STOP Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 KICK H Z (a) KICK (b) BRAKE (c) STOP BRAKE STOP MDP MDP Z MDP Z Timing Chart 1-9 CAV-W mode LPWR = 0 KICK H BRAKE STOP MDP MDP L (b) BRAKE MDP Z (a) KICK (c) STOP Timing Chart 1-10 CAV-W mode LPWR = 1 KICK H BRAKE STOP MDP MDP Z (b) BRAKE MDP Z (c) STOP (a) KICK - 59 - CXD2598Q Timing Chart 1-11 CLV-N mode LPWR = 0 n * 236 (ns) n = 0 to 31 Acceleration MDP Z Deceleration 132kHz 7.6s Timing Chart 1-12 CLV-W mode LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-13 CLV-W mode LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 60 - CXD2598Q Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. - 61 - CXD2598Q 2. Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Sub-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register. * First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. * The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. * The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak meter mode" on page 45. See Timing Chart 2-3. * Clock input via the SQCK pin is necessary to perform these operations. The high and low intervals for SQCK input should be between 750ns and 120s. - 62 - CXD2598Q Timing Chart 2-1 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 63 - Block Diagram 2-2 (ASEC) 80 bit S/P Register (AMIN) ADDRS CTRL (AFRAM) SUBQ SIN ABCDE FGH 8 Order Inversion 8 8 8 8 8 8 8 8 HGFEDCBA 80 bit P/S Register SI SO LD LD LD LD LD LD SUBQ LD ABS time load control for peak value CRCC Monostable multivibrator SHIFT SHIFT LD - 64 - LOAD CONTROL SO 16 bit P/S register SI 16 Peak detection SQCK Ring control 1 Ring control 2 CRCF Mix SQSO CXD2598Q Timing Chart 2-3 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK SCOR Determined by mode CRCF1 80 or 96 Clock CRCF2 SQSO CRCF1 SQCK Register load forbidder - 65 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Monostable Multivibrator (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2598Q Timing Chart 2-4 Example: $802000 latch Set SQCK high during this interval. XLAT 750ns or more Internal signal latch SQCK SQSO PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH ALOCK VF0 VF1 VF2 VF3 PER0 PER1 PER2 PER3 VF4 VF5 VF6 VF7 VF8 VF9 Signal Description PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK. GFS High when the frame sync and the insertion protection timing match. - 66 - Description C1 pointer reset C1 pointer reset C2F2 0 0 0 0 C1 pointer set C1 pointer set 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 -- -- LOCK GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. EMPH High when the playback disc has emphasis. ALOCK GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. VF0 to 9 Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. Description No C2 errors; One C2 error corrected; C2 pointer reset C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset -- C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set C1F2 C1F1 C1F0 0 0 0 No C1 errors; 0 0 1 One C1 error corrected; 0 1 0 0 1 1 1 0 0 No C1 errors; 1 0 1 One C1 error corrected; 1 1 0 Two C1 errors corrected; C1 pointer set CXD2598Q 1 1 1 C1 correction impossible; C1 pointer set CXD2598Q Timing Chart 2-5 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load VF0 to 9 m The relative velocity R of the disc can be expressed with the following equation. R= m+1 (R: Relative velocity, m: Measurement results) 32 VF0 to VF9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 67 - Timing Chart 2-6 XLAT SQCK - 68 - 8 7 6 5 4 3 2 1 C1 error rate 7 3 5 0 0 7 SQSO C1 MSB 19 18 17 16 15 14 13 12 11 10 9 0 19 18 17 16 15 14 13 12 11 10 9 8 C2 error rate 7 6 5 4 3 2 1 0 0 3 5 0 CXD2598Q CXD2598Q 3. Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the conventional PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the V16M pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for this mode is theoretically up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to quadruple speed. (See "$DX commands".) When controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.3kHz obtained by 1/128-frequency dividing XTAL (XTAI, XTAO) (384Fs). The velocity is obtained by counting half of the V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VF0 to VP9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for CAV-W mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode. - 69 - CXD2598Q 3-4. VCO-C Mode This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 commands and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation. V16M = 1(256 - n) 32 n: VP0 to VP7 setting value 1: VPCTL0, 1 setting value The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. * When DSPB = 0 VCO1 = V16M x * When DSPB = 1 VCO1 = V16M x 49 16 49 24 - 70 - CXD2598Q CAV-W Rotational velocity CLVS Target speed CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E60CX (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart - 71 - CXD2598Q VCO-C Mode Access START R? (How many minutes of absolute time?) n? (Caluculate n) What is the playback speed when access ends? Caluculate VP0 to VP7. Transfer $E00510 Switch to VCO control mode EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer VP0 to VP7. ( corresponds to VP0 to VP7.) Transfer $DX XX Track Jump Subroutine Transfer $E66500 Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END Fig. 3-3. Access Flow Chart Using VCO Control - 72 - CXD2598Q 4. Description of other functions 4-1. Channel Clock Recovery by Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to recover the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2598Q has a built-in three-stage PLL. * The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that recovers the actual channel clock. * The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such a case, turning off the secondary loop yields better playability. However, in this case the capture range becomes 50kHz. * A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. - 73 - CXD2598Q Block Diagram 4-1 CLV-W CAV-W Spindle rotation information Clock input 1/2 XTAI XTSL 1/32 Selector VPCO Phase comparator CLV-N 1/2 1/l 1/n CLV-W CAV-W /CLV-N l = 1, 2, 3, 4 (VPCTL0, 1) Microcomputer control 1/K (KSL1, 0) VCO2 n = 1 to 256 (VP7 to 0) LPF VCOSEL2 VCTL V16M 2/1 MUX VPON 1/M Phase comparator PCO 1/N FILI FILO 1/K (KSL3, 2) VCO1 CLTV Digital PLL RFPLL VCOSEL1 - 74 - CXD2598Q 4-2. Frame sync protection * In normal speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2598Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13, and the backward protection counter to 3. Concretely, when the disc is being played back normally and then the frame sync cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. Default values. These values can be set as desired by the SFP3 to SFP0 and SRP3 to SRP0 commands of $C. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. * The CXD2598Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status during C1 error correction, the playback status of the EFM signal, and the operating status of the player. * The correction status can be monitored externally. See Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible; C2 correction impossible; Table 4-2. - 75 - No C1 errors; One C1 error corrected; Two C1 errors corrected; C1 correction impossible; No C2 errors; One C2 error corrected; Two C2 errors corrected; Three C2 errors corrected; Four C2 errors corrected; No C1 errors; One C1 error corrected; Description C1 pointer reset C1 pointer reset -- -- C1 pointer set C1 pointer set C1 pointer set C1 pointer set C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset -- C1 pointer copy C2 pointer set CXD2598Q Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 4-4. DA Interface * The DA interface supports the 48-bit slot interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. - 76 - Timing Chart 4-4 48-bit slot Normal-Speed Playback LRCK (44.1K) 4 5 6 7 8 9 10 11 12 24 1 2 3 BCK (2.12M) WDCK PCMD L14 L13 L12 L11 L10 L9 L8 L7 R0 Lch MSB (15) L6 L5 L4 L3 L2 L1 L0 Rch MSB - 77 - 24 L0 Rch MSB 48-bit slot Double-Speed Playback LRCK (88.2K) 12 BCK (4.23M) WDCK PCMD R0 Lch MSB (15) CXD2598Q CXD2598Q 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2598Q supports type 2 form 1. The CXD2598Q also supports two Digital Out generation methods: generation from the PCM data read out from the disc, and generation from the DA interface input (PCMDI, LRCKI, BCKI). 4-5-1. Digital Out from PCM Data Digital Out is generated from the PCM data read out from the disc. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode. In addition, Sub-Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz, XTSL is high and DSPB is set to 1 in CLV-N or CLV-W mode. Therefore, set the MD2 pin to 0 and turn DOUT off. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0 /1 0 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q 32 48 0 176 bits 0 to 3 Sub Q control bits that matched twice in succession with CRCOK bit 29 VPON or VARION: 1 Crystal: 0 Table 4-5-1. - 78 - CXD2598Q 4-5-2. Digital Out from DA Interface Input Digital Out is generated from the DA interface input. Validity Flag, User Data The Validity Flag and User Data are fixed to 0. Channel Status Data Bits 0, 6 and 7 of the Channel Status Data are fixed to 0. In addition, the following items can be set by bits 1, 2, 3 and 8. a) Digital data/audio data b) Digital copy allowed/prohibited c) Pre-emphasis on/off d) Category code (2 types) Digital Out C bit 0 0 0 1 2 3 4 0 5 0 6 0 7 0 8 CAT b8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 A/D COPY EMPH D SEL En 0 0 0 16 0 0 0 0 0 0 0 0 0 0 0 0 32 48 0 176 Table 4-5-2. Note) When using this generation method, turn DOUT off by first setting the MD pin to 0 and then setting the DOUT EN command of $34A to 0. - 79 - CXD2598Q Digital audio data input The digital audio data input signal is input from the DAC input pins PCMDI, LRCKI and BCKI. The input format supports the 48-bit slot, MSB first. Mute function The audio data portion of the Digital Out output can be set to all zero without altering the Channel Status Data by setting command bit DOUT_DMUT to 1. I/O sync circuit The DAC is automatically synchronized to the input LRCK during normal operation, but synchronization may not be possible when the input data contains a large amount of jitter or during power-on, etc. In such a case, internal operation must be forcibly resynchronized by setting the DOUT WOD command of $34A to 1. Forced synchronization is also necessary when the operating frequency is switched such as when switching between CLV and CAV. When performing resynchronization, be sure to first return DOUT WOD to 0 and then set to 1. Resynchronization clears the internal frame counter, so the count starts over from frame 0 after the resynchronization processing. The resynchronization circuit can be disabled by setting the WINEN command of $34A to 0 so that resynchronization processing is not performed automatically or to perform resynchronization processing at the user's discretion. DOUT circuit clock system The DOUT block master clock is set using the clock control command MCSL ($A) used by the DAC block. Therefore, set MCSL = 1 when using 768fs, and MCSL = 0 when using 384fs. - 80 - DOUT Block Input Timing Chart 48-bit slot LRCK 5 6 7 8 9 10 11 12 24 1 2 3 4 BCKI PCMDI L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 R0 Lch MSB (15) L3 L2 L1 L0 Rch MSB - 81 - CXD2598Q CXD2598Q 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ ON-OFF of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See "1 $4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed an accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. - 82 - CXD2598Q * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed an accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is made possible by controlling the sled. The track jump count N is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N - a in the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. * M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. - 83 - CXD2598Q Auto focus Focus search up FOK = H YES NO FZC = H YES NO Check whether FZC is continuosly high for the period of time E set with register 5. FZC = L YES Focus servo ON NO END Fig. 4-6-(a). Auto Focus Flow Chart $47 Latch XLAT FOK FZC BUSY Command for DSSP $03 Blind E $08 Fig. 4-6-(b). Auto Focus Timing Chart - 84 - CXD2598Q 1 Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) COUT = YES Track REV kick WAIT (Brake B) Track, sled servo ON NO (FWD kick for REV jump) END Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Command for DSSP Blind A $28 ($2C) $2C ($28) Brake B $25 Fig. 4-7-(b). 1-Track Jump Timing Chart - 85 - CXD2598Q 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT x 5) COUT = 5 ? YES Track, REV kick NO Checks whether the COUT cycle is longer than overflow C. C = Overflow ? YES Track, sled servo ON NO END Fig. 4-8-(a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A Command for DSSP COUT 5 count Overflow C $2A ($2F) $2E ($2B) $25 Fig. 4-8-(b). 10-Track Jump Timing Chart - 86 - CXD2598Q 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N NO YES Track REV kick Counts COUT for the first 16 times and MIRR for more times. C = Overflow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 4-9-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP $2A ($2F) COUT (MIRR) N count $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 4-9-(b). 2N-Track Jump Timing Chart - 87 - CXD2598Q Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N ? YES NO Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-10-(a). Fine Search Flow Chart $44 (REV = $45) latch XLAT COUT BUSY Command for DSSP Kick D $26 ($27) Kick F Traverse Speed Control (Overflow G) & COUT N count Kick D $27 ($26) $25 $2A ($2F) Fig. 4-10-(b). Fine Search Timing Chart - 88 - CXD2598Q M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M < 16. Counts MIRR for M 16. COUT (MIRR) = M NO YES Track, Sled Servo OFF END Fig. 4-11-(a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP $22 ($23) COUT (MIRR) M count $20 Fig. 4-11-(b). M-Track Move Timing Chart - 89 - CXD2598Q 4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDS 1/2 Mux Gain MDP + Gain DCLV Over Sampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI LPWR Mode Select MDP CLVS U/D: MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from microcomputer for CAV servo Fig. 4-12. Block Diagram - 90 - CXD2598Q 4-8. CD-DSP Block Playback Speed In the CXD2598Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode 1 2 3 4 5 6 7 XTAI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 1 VCOSEL11 0/1 0/1 1 1 0/1 0/1 0/1 ASHS 0 0 1 1 0 0 0 Playback speed 1x 2x 2x 4x 1x 2x 1x Error correction2 C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. 2 When the ERC4 command of $8 = 1, C2 is quadruple correction even when DSPB = 1. The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "3. Description of Modes" for details. 4-9. DAC Block Playback Speed The operating speed of the DAC block is determined by the crystal and the MCSL command of $9X regardless of the operating conditions of the CD-DSP block. This allows the DAC and CD-DSP block playback modes to be set independently. 1-bit DAC block playback speed X'tal 768Fs 768Fs 384Fs Fs = 44.1kHz. MCSL 1 0 0 DAC block playback speed 1x 2x 1x - 91 - CXD2598Q 4-10. DAC Block Input Timing The DAC block input timing is shown in Timing Chart 4-12. The CXD2598Q enables data transfer from the CD signal processor block to the DAC block via an external route. This makes it possible to send data to the DAC block via an external audio DSP, etc. When the data is input to the DAC block without using an audio DSP, either EMPH, LRCK, BCK and PCMD must be connected directly with EMPHI, LRCKI, BCKI and PCMDI outside the LSI, or the OUTL0 command of $8X must be set to 1. Note that when the OUTL0 command of $8X is set to 1, the EMPH, LRCK, BCK and PCMD outputs are low. 4-11. Description of DAC Block Functions Zero data detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X. * When zero data is detected * When a high signal is input to the SYSM pin * When the DAC SMUTL and DAC SMUTR commands of $9X are set (The flags change independently for the left and right channels.) The mute flag outputs during initialize are as follows. (When zero data is input from LRCKI, BCKI and PCMDI, and ZDPL of address $9 and MCSL of address $A are the initial values for the period in the figure below.) XRST LMUT RMUT Approximately 370ms when crystal = 16.9344MHz Approximately 185ms when crystal = 33.8688MHz Attenuation operation Assuming the attenuation commands X1, X3 and X2, the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches Y2. In addition, when the command X3 is sent before the audio output reaches Y2 (B or C in the figure), the audio output approaches Y3 from the value (B or C in the figure) at that point. 0dB 400 (H) A Y1 B Y3 C Y2 - 000 (H) 23.2 [ms] - 92 - CXD2598Q DAC block mute operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. * When attenuation data of 000 (high) is set * When the DAC SMUTL and DAC SMUTR commands of $9X are set to 1 * When a high signal is input to the SYSM input pin Soft mute OFF 0dB Soft mute ON Soft mute OFF -dB 23.2 [ms] 23.2 [ms] Forced mute Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low. Zero detection mute Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1. - 93 - Timing Chart 4-12 Normal-Speed Playback LRCKI (44.1k) 5 6 7 8 9 10 11 12 1 2 3 4 24 BCKI (2.12M) PCMDI R0 L14 L13 L12 L11 L10 L9 L8 L7 L6 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB - 94 - 24 Rch MSB L0 Double-Speed Playback LRCKI (88.2k) BCKI (4.23M) 1 2 PCMDI Lch MSB (15) R0 CXD2598Q DAC Block Input Timing CXD2598Q LRCK Synchronization Synchronization is performed at the first rising edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. * When the XTSL pin switches between high and low * When the DSPB command of $9X setting changes * When the MCSL command of $AX setting changes * When operation switches between CLV mode and CAV mode LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in these cases as well. For resynchronization, set the XWOC command of $9X to 0, wait for one LRCK cycle or more, and then set XWOC to 1. When setting XWOC to 0, be sure to set the SYCOF command of $9X to 0 beforehand. SYCOF When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores when the LRCKI input synchronization is lost, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI input. Set SYCOF to 0 other than when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode. - 95 - CXD2598Q Digital Bass Boost Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for this setting. See Graph 4-13 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 Normal DBB MID DBB MAX [dB] -2.00 -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 10 30 100 300 1k 3k 10k 30k Digital Bass Boost Frequency Response [Hz] Graph 4-13. - 96 - CXD2598Q 4-12. LPF Block The CXD2598Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (Vc) is (AVDD - AVSS) x 0.43. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc 40kHz. The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference. The resistors' values do not change at this time. * When fc 30kHz: C1 = 200pF, C2 = 910pF * When fc 50kHz: C1 = 120pF, C2 = 560pF LPF Block Application Circuit AOUT1 (2) 12k C2 680p 12k AIN1 (2) Vc C1 150p 12k Analog out LOUT1 (2) Fig. 4-14. LPF External Circuit - 97 - CXD2598Q 4-13. Asymmetry Correction Fig. 4-15 shows the block diagram and circuit example. ASYE ASYO R1 RFAC + - R1 R2 R1 ASYI + - R1 BIAS R1 2 = R2 5 Fig. 4-15. Asymmetry Correction Application Circuit. - 98 - CXD2598Q 4-14. CD TEXT Data Demodulation * In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, the CD TEXT demodulation circuit occupies the EXCK and SBSO pins, so connect EXCK to low and do not use the data output from SBSO. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1. * The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK. * The readable data are the CRC counting results for each pack and the CD TEXT data (16 bytes) except for CRC data. * When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Data which can be stored in the LSI is 1 packet (4 packs). TXON CD TEXT Decoder EXCK SBSO Subcode Decoder SQCK SQSO TXOUT Fig. 4-16. Block Diagram of CD TEXT Demodulation Circuit - 99 - SCOR Subcode Q Data CRC 80 Clocks 520 Clocks 0 Pack1 Pack3 Pack2 Pack4 4 bits 16 Bytes 4 bits 16 Bytes 16 Bytes 16 Bytes CRCF SQSO CRCF SQCK TXOUT (command) - 100 - ID1 (Pack1) LSB MSB R2 W1 V1 U1 T1 S1 R1 U3 1 CRC Data LSB T3 ID2 (Pack1) MSB LSB S3 R3 W2 V2 U2 ID3 (Pack1) SQSO CRC CRC CRC CRC 4 3 2 0 0 S2 0 0 T2 W4 V4 U4 T4 S4 SQCK TXOUT (command) CXD2598Q Fig. 4-17. CD TEXT Data Timing Chart CXD2598Q 5. Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Other: 345Hz (when MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 0.43VDD to VDD Other: RF zero level automatic measurement - 101 - CXD2598Q 5-2. Digital Servo Block Master Clock (MCK) The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default = 0 for each command) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 1 2 3 4 5 6 7 XTAI 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL 0 1 XT4D 0 1 0 XT2D 1 0 1 0 0 XT1D 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 5-1. - 102 - CXD2598Q 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD2598Q can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD2598Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (Hex). XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s AVRG measurement completed Timing Chart 5-2. CXD2598Q 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted as a result. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set for $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops if the FCSBIAS value and the value set beforehand in FBL9 to FBL1 of $34 match. Also, if the upper 8 bits of the command register are $3A at this time, SENS becomes high and the counter stop can be monitored. Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the FCSBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 x VDD x 0.4. A FBIAS setting value (FB9 to FB1) B C LIMIT value (FBL9 to FBL1) SENS value A: Register mode B: Counter mode C: Counter mode (when stopped) - 104 - CXD2598Q RFDC from A/D RF AVRG register - RFLC To RF In register SE from A/D - TLC1 * TLD1 TLC2 * TLD2 - To SLD In register TE from A/D - - To TRK In register TE AVRG register TLC1 TRVSC register TLC2 FE from A/D FE AVRG register - FLC1 FBIAS register + FBON To FCS In register FLC0 - To FZC register Fig. 5-3a. RFDC from A/D RF AVRG register - RFLC To RF In register SE from A/D - - To SLD In register TLC0 * TLD0 TLC2 * TLD2 TE from A/D - TLC0 VC AVRG register TRVSC register TLC2 - To TRK In register VCLC FE from A/D FE AVRG register - FBIAS register + FBON To FCS In register FLC0 - To FZC register Fig. 5-3b. - 105 - CXD2598Q 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 5-4 Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 106 - CXD2598Q AGCNTL default operation has two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted to approach a more appropriate value with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2598Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Conversion value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 5-5. Note) Fig. 5-5 shows the example where the AGCNTL coefficient value converges to the smaller value from the initial value. - 107 - CXD2598Q 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 108 - CXD2598Q 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 0010 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD2598Q has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x or 4x magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 5-10. - 109 - CXD2598Q 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to the peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and D4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold - Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 -Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. - 110 - CXD2598Q 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 5-13. 5-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It can also be monitored from the ATSK pin by setting the ASOT command of $3F to 1. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen Fig. 5-14. - 111 - CXD2598Q 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting unnecessary portions of it utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1 and 2 of $34B) Inner track Outer track Outer track Inner track FWD REV Servo ON JMP JMP TRK DRV TRK DRV REV FWD Servo ON JMP JMP RF Trace MIRR TE 0 RF Trace MIRR TE 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 0 0 Fig. 5-15. Register name Command D23 to D20 D19 to D16 10 0 1 1 TRACKING CONTROL 0001 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF Fig. 5-16. TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Table 5-17. - 112 - CXD2598Q 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases for each COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT signal generation when MIRR is externally input and for applications other than COUT generation This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) * DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by serial command $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result XLAT tDLS $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value tSPW SCLK 1/fSCLK *** Serial readout data (SENS) MSB *** LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 31.3 15 Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). - 113 - Unit MHz ns s tSPW tDLS CXD2598Q 5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients continuously, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. 5-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value -A Output value 0 FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK tMCK = 1 5.6448MHz 180ns Timing Chart 5-20. VCC R R RDR FDR R R VEE DRV Fig. 5-21. Driver Circuit - 114 - CXD2598Q 5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 5-18. Description of Commands and Data Sets $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 PGFS1 PGFS0 PFOK1 PFOK0 These commands set the GFS signal hold time. The hold time is inversely proportional to the playback speed. PGFS1 0 0 1 1 PGFS0 0 1 0 1 Processing High when the frame sync is the correct timing, low when not the correct timing. High when the frame sync is the correct timing, low when continuously not the correct timing for 2ms or longer. High when the frame sync is the correct timing, low when continuously not the correct timing for 4ms or longer. High when the frame sync is the correct timing, low when continuously not the correct timing for 8ms or longer. These commands set the FOK signal hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. PFOK1 0 0 1 1 PFOK0 0 1 0 1 Processing High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. - 115 - CXD2598Q $34A (preset: $34A 150) D15 1 D14 0 D13 1 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT SEL EN D b8 EN1 DMUT WOD EN EN2 Command bit A/DSEL = 0 A/DSEL = 1 Processing Bit 1 of the channel status data is output as audio data. Bit 1 of the channel status data is output as other than audio data. Command bit COPY EN1 = 0 COPY EN1 = 1 Processing Bit 2 of the channel status data is output as digital copying prohibited. Bit 2 of the channel status data is output as digital copying allowed. Command bit EMPH D = 0 EMPH D = 1 Processing Bit 3 of the channel status data is output as pre-emphasis off. Bit 3 of the channel status data is output as pre-emphasis on. Command bit CAT b8 = 0 CAT b8 = 1 Processing Bit 8 of the channel status data is output as 0. Bit 8 of the channel status data is output as 1. Command bit DOUT EN = 0 DOUT EN = 1 Processing The DOUT signal generated from the PCM data read out from the disc is output. The DOUT signal generated from the DA interface input is output. Command bit DOUT DMUT = 0 DOUT DMUT = 1 Digital Out output is output normally. Processing Digital Out output is output with the audio data portion set to all zero. Command bit Processing DOUT WOD = 0 The DOUT sync window does not open. DOUT WOD = 1 The DOUT sync window opens. Command bit WIN EN = 0 WIN EN = 1 Processing Automatic synchronization to the input LRCK to match the phase with the internal processing is disabled. Automatic synchronization to the input LRCK to match the phase with the internal processing is enabled. - 116 - CXD2598Q $34A commands cont. Command bit DOUT EN2 = 0 DOUT EN2 = 1 Processing Set to 0 when not generating Digital Out from the DA interface input. Set to 1 when generating Digital Out from the DA interface input. DOUT EN1 0 0 0 0 0 0 0 0 0 1 DOUT DMUT -- -- -- -- -- -- -- -- -- 0 MD2 pin 0 1 1 1 1 1 1 1 1 -- Other mute conditions -- 0 0 0 0 1 1 1 1 -- DOUT Mute -- 0 0 1 1 0 0 1 1 -- DOUT Mute F -- 0 1 0 1 0 1 0 1 -- DOUT output OFF 0dB Output from PCM data read out from disc. - dB Output from PCM data read out from disc. 0dB Output from DA interface input. - dB Output from DA interface input. --: don't care 1 1 -- -- -- -- See mute conditions (1) and (3) to (5) under $AX commands for other mute conditions. See $8 commands for DOUT Mute and DOUT Mute F. - 117 - CXD2598Q $34B (preset: $34B 000) D15 1 D14 0 D13 1 D12 1 D11 D10 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFBK1 SFBK2 The low frequency can be boosted for the brake operation. See 5-12 for brake operation. SFBK1: SFBK2: When set to 1, brake operation is performed by setting the LowBooster-1 input to 0. However, this is valid only when TLB1ON = 1. The preset is 0. When set to 1, brake operation is performed by setting the LowBooster-2 input to 0. However, this is valid only when TLB2ON = 1. The preset is 0. $34C (preset: $34C 000) D15 1 D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 0 D5 D4 D3 D2 D1 D0 THBON FHBON TLB1ON FLB1ON TLB2ON HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 These commands turn on the boost function. (See 5-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: FHBON: TLB1ON: FLB1ON: TLB2ON: When set to 1, the high frequency is boosted for the TRK filter. The preset is 0. When set to 1, the high frequency is boosted for the FCS filter. The preset is 0. When set to 1, the low frequency is boosted for the TRK filter. The preset is 0. When set to 1, the low frequency is boosted for the FCS filter. The preset is 0. When set to 1, the low frequency is boosted for the TRK filter. The preset is 0. The difference between TLB1ON and TLB2ON is the LowBoost position. TLB1ON performs LowBoost before the TRK jump, and TLB2ON performs LowBoost after the TRK jump. The following commands set the boosters. (See 5-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-24a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.) An example of characteristics is shown in Fig. 5-26a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.) An example of characteristics is shown in Fig. 5-26b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.) An example of characteristics is shown in Fig. 5-26c. This booster is used exclusively with the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz - 118 - CXD2598Q BK3 Z -1 BK1 Z -1 BK2 HBST1 0 1 1 HBST0 -- 0 1 HighBooster setting BK1 -120/128 -124/128 -126/128 BK2 96/128 112/128 120/128 BK3 2 2 2 Fig. 5-24a. Table 5-25a. BK6 Z -1 BK4 Z -1 BK5 LB1S1 0 1 1 LB1S0 -- 0 1 LowBooster-1 setting BK4 -255/256 -511/512 -1023/1024 BK5 1023/1024 2047/2048 4095/4096 BK6 1/4 1/4 1/4 Fig. 5-24b. Table 5-25b. BK9 Z -1 BK7 Z -1 BK8 LB2S1 0 1 1 LB2S0 -- 0 1 LowBooster-2 setting BK7 -255/256 -511/512 -1023/1024 BK8 1023/1024 2047/2048 4095/4096 BK9 1/4 1/4 1/4 Fig. 5-24c. Table 5-25c. - 119 - CXD2598Q 15 12 9 3 6 3 2 1 Gain [dB] 0 -3 -6 -9 -12 -15 1 10 100 Frequency [Hz] 1k 10k +90 +72 3 2 1 +36 Phase [degree] 0 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26a. Servo HighBooster Characteristics [FCS, TRK] (MCK = 128Fs) 1 HBST1 = 0 2 HBST1 = 1, HBST0 = 0 - 120 - 3 HBST1 = 1, HBST0 = 1 CXD2598Q 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26b. Servo LowBooster-1 Characteristics [FCS, TRK] (MCK = 128Fs) 1 LB1S1 = 0 2 LB1S1 = 1, LB1S0 = 0 - 121 - 3 LB1S1 = 1, LB1S0 = 1 CXD2598Q 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-26c. Servo LowBooster-2 Characteristics [FCS, TRK] (MCK = 128Fs) 1 LB2S1 = 0 2 LB2S1 = 1, LB2S0 = 0 - 122 - 3 LB2S1 = 1, LB2S0 = 1 CXD2598Q $34F D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/5 and FB9 to FB1 = 100000000 to -256/256 x VDD/5 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/5 and TV9 to TV0 = 1100000000 to -256/256 x VDD/5 respectively. (VDD: supply voltage) Note) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 123 - CXD2598Q $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDDV/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage FS5 to FS0: Focus search limit voltage Default value: 011000 ((1 24/64) x VDD/2, VDD: PWM driver supply voltage) Focus drive output conversion AGF convergence gain setting value Default value: 0101101 FG6 to FG0: $36 (preset: $36 0E 2E) D15 D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 TDZC DTZC TJ5 TDZC: TJ0 SFJP TG6 DTZC: TJ5 to TJ0: SFJP: TG6 to TG0: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. TDZC = 0: The edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: The edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See 5-12.) DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) Track jump voltage Default value: 001110 ((1 14/64) x VDD/2, VDD: PWM driver supply voltage) Tracking drive output conversion Surf jump mode on/off The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to TJ0), by setting D7 to 1 (on) AGT convergence gain setting value Default value: 0101110 - 124 - CXD2598Q $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD x 0.4, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD x 0.4 1/8 x VDD x 0.4 1/16 x VDD x 0.4 1/32 x VDD x 0.4 : preset SM5 to SM0: Sled move voltage Default value: 010000 ((1 16/64) x VDD/2, VDD: PWM driver supply voltage) Sled drive output conversion AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1/32 x VDD x 0.4 1 (large) 1/16 x VDD x 0.4 0 (small) 1/16 x VDD x 0.4 1 (large) 1/8 x VDD x 0.4 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) AGS: AGJ: AGGF: AGGT: - 125 - CXD2598Q $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC offset cancel. See 5-3. VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) Automatic gain control. See 5-6. AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) Anti-misoperation circuits. DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. DC offset cancel. See 5-3. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when set to 1. - 126 - CXD2598Q $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: SD6 to SD0: SD6 1 0 Serial data readout DAC mode (on/off) Serial readout data select SD5 Readout data Readout data length 8 bits 16 bits Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 SD3 to SD0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) - (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits $399F $399E $399D $399C $3993 $3992 $3991 0 $398C 9 bits $3988 9 bits $3984 9 bits $3983 8 bits $3982 8 bits $3981 8 bits $3980 8 bits Don't care Note) Coefficients K40 to K4F cannot be read out. See the description of data readout concerning readout methods for the above data. Note) Coefficient RAM data readout It is not possible to read out all coefficients at all times. Only the coefficients for the currently used filter composition can be read out. For example, if the TRK Gain Normal filter is selected by the presets, the TRK gain normal filter coefficients (K19 to K23) can be read out, but the TRK Gain Up filter coefficients (K36 to K3E) cannot be read out. This is the same for FCS. Note) Data RAM readout The meaning of each Data RAM address is as follows. M00 to 02: SLD-filter M03 to 07: FCS-filter M08 to 0A: HPTZC/AutoGain, AntiShock, Average M0B to 0F: TRK-filter M10, 11: FCS Hold-filter M12: FCS Hold Reg M13 to 17: reserved M18, 19: TRK Hold-filter M1A: TRK Hold Reg M1B to M1D: reserved M1E, 1F: FCS Hold Reg - 127 - CXD2598Q $3A (preset: $3A 00 00) D15 0 FBON: FBSS FBUP D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 0 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 SJHD INBK MTI0 These commands set the FBIAS (focus bias) register operation. FBON 0 1 1 1 FBSS 0 0 1 1 FBUP -- -- 0 1 Processing FBIAS (focus bias) register addition off. FBIAS (focus bias) register addition on. FBIAS register operates as a down counter. FBIAS register operates as an up counter. FBV1, FBV0: FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. The counter changes by one step for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 x VDD x 0.4, VDD = supply voltage. FBV1 0 0 1 1 FBV0 0 1 0 1 Number of steps per cycle 1 2 4 8 : preset This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0 : Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0 : Gain setting when transferring data from the tracking filter to the PWM block. This is effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SJHD: INBK: This holds the tracking filter output at the value when surf jump starts during surf jump. When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). - 128 - TJD0: MTI0: CXD2598Q $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD x 0.57, VDD = supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 x VDD x 0.57 20/256 x VDD x 0.57 24/256 x VDD x 0.57 28/256 x VDD x 0.57 32/256 x VDD x 0.57 40/256 x VDD x 0.57 48/256 x VDD x 0.57 56/256 x VDD x 0.57 : preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDD x 1.14V) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 0.0156 x VDD x 1.14 0.0234 x VDD x 1.14 0.0313 x VDD x 1.14 0.0391 x VDD x 1.14 : preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. - 129 - CXD2598Q D2V2, D2V1 : Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD x 1.14V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 0 0 1 1 D2V1 0 1 0 1 Count-down speed [V/ms] 0.0431 x VDD x 1.14 0.0861 x VDD x 1.14 0.172 x VDD x 1.14 0.344 x VDD x 1.14 [kHz] 22.05 44.1 88.2 176.4 : preset, VDD: supply voltage D1V2, D1V1 : Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD x 1.14V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2 0 0 1 1 D1V1 0 1 0 1 Count-down speed [V/ms] 0.344 x VDD x 1.14 0.688 x VDD x 1.14 1.38 x VDD x 1.14 2.75 x VDD x 1.14 [kHz] 176.4 352.8 705.6 1411.2 : preset, VDD: supply voltage RINT: This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. - 130 - CXD2598Q $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: These select the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When CETZ = 0, the TZC signal is generated by using the signal input to the TE pin. When CETZ = 1, the TZC signal is generated by using the signal input to the CE pin. When CETF = 0, the signal input to the TE pin is input to the TRK servo filter. When CETF = 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: This uses the TZC signal in place of the COUT signal. Concretely, the TZC signal is output from the COUT pin and it is also used in place of the COUT signal for auto sequence operation. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT : preset, --: don't care MOT2: This uses the STZC signal in place of the MIRR signal. Concretely, the STZC signal is output from the MIRR pin, and it is also used in place of the MIRR signal for COUT signal generation. These commands set the MIRR signal generation circuit. BTS1, BTS0 : This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. However, this is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. BTS1 BTS0 0 0 1 1 0 1 0 1 Number of count-up increments per step 1 2 4 8 - 131 - MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [s] 5.669 11.338 22.675 45.351 : preset (when MCK = 128Fs) CXD2598Q $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK SFID: TLD2 TLD1 TLD0 SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. See "5-20. Filter Composition" for further information on the SFID, SFSK, THID and THSK commands. SFSK: THID: THSK: TLD0 to 2: SLD filter correction turns on and off independently of the TRK filter. See $38 (TLC0 to TLC2) and Fig. 5-3. TLC2 0 1 TLD2 -- 0 1 Traverse center correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 TLD1 -- 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON SLD filter OFF ON OFF : preset, --: don't care - 132 - CXD2598Q * Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD2598Q outputs the servo drives which have the reversed phase to the error inputs. Negative input coefficient TE K19 TRK Filter Positive output coefficient K22 Negative input coefficient SE K00 SLD Filter Positive output coefficient K05 Positive input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) sign. (For example, inverting the sign for coefficient K00: E0h results in 60h.) For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) sign. Negative input coefficient TE K19 TRK Filter MOD Positive output coefficient K22 Positive input coefficient SE K00 SLD Filter Positive output coefficient K05 Negative input coefficient TRK Hold K40 TRK Hold Filter Positive output coefficient K45 for TRK servo gain normal See "5-20. Filter Composition". - 133 - CXD2598Q $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when set to 1; default = 0. Generally, the phase advance amount increases by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when set to 1; default = 0. Generally, the phase advance amount increases by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "5-20 Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when set to 1; default = 0 When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. TLCD: LKIN: COIN: The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care XT1D: When 1, the input to the servo master clock can be used without being frequency divided. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 134 - CXD2598Q $3F (preset: $3F 00 00) D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 0 D2 0 D1 D0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ LPAS AGHF ASOT This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGG4 AGGF AGGT 0 0 1 -- -- 0 1 0 1 1 -- -- 0 1 0 1 0 1 Sine wave amplitude FE input conversion TE input conversion See $37 for AGGF and AGGT. 1/32 x VDD x 0.4 -- The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. 1/16 x VDD x 0.4 -- : preset, --: don't care -- 1/16 x VDD x 0.4 -- 1/8 x VDD x 0.4 1/64 x VDD x 0.4 1/32 x VDD x 0.4 1/16 x VDD x 0.4 1/8 x VDD x 0.4 XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio when generating MCK to 1/4, 1/2 or 1/1. See the description of $3E for XT1D. Also, see "5-2. Digital Servo Block Master Clock (MCK)". XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when set to 1 (on) respectively; default = 0 DRR2:M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when set to 1; default = 0 FTQ: The slope of the output during focus search is a quarter of the conventional output slope. On when set to 1; default = 0. LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, first check whether each error signal is properly A/D converted using data readout, etc. AGHF: This halves the frequency of the internally generated sine wave during AGC. ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when set to 1; default = 0. Vibration detection when a high signal is output for the anti-shock signal output. - 135 - CXD2598Q Description of Data Readout SOCK (5.6448MHz) *** *** *** *** XOLT (88.2kHz) SOUT MSB *** LSB MSB *** LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * To the 7-segment LED * MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at a time. This enable Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 136 - CXD2598Q 5-19. List of Servo Filter Coefficients Fix indicates that normal preset values should be used. - 137 - CXD2598Q - 138 - 5-20. Filter Composition The internal filter composition is shown below. K indicates the coefficient RAM address and M indicates the Data RAM address. FCS Servo Gain Normal; fs = 88.2kHz M1F M1E K0F M05 M06 K11 K13 Z -1 K0E K10 M07 Z -1 K0A K0C 2 -7 K0B K0D Note) Set the MSB bit of the K0B and K0D coefficients to 0. 2 -7 27 To FCS Hold FCS AUTO Gain K0F M03 Z -1 K08 K09 Z -1 M04 To FCS Hold FCS Hold Reg2 DFCT FCS In Reg 2 -1 K06 AGFON Sin ROM K06 FCS Servo Gain Down; fs = 88.2kHz M1F M1E K2B M05 Z -1 K26 K28 2 -7 K27 K29 2 -7 K2A To FCS Hold M06 Z -1 K2C K2D K2B M03 Z -1 K24 K25 Z -1 M04 To FCS Hold FSC AUTO Gain M07 K13 FCS Hold Reg2 DFCT - 139 - Note) Set the MSB bit of the K27 and K29 coefficients to 0. FPS1, 0 BK3 Z -1 BK1 Z -1 BK2 BK6 Z -1 BK4 FCS In Reg 2 -1 K06 PWM Z -1 FCS SRCH BK5 CXD2598Q TRK Servo Gain Normal; fs = 88.2kHz To SLD Servo, TRK Hold M0B M0D M0E K22 K23 Z -1 K20 K21 M0F Z -1 K1C K1E 2 -7 K1D K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. 2 -7 Z -1 K1A K1B Z -1 M0C TRK AUTO Gain TRK Hold Reg DFCT TRK In Reg 2 -1 K19 AGTON Sin ROM K19 TRK Servo Gain Up1; fs = 88.2kHz TRK AUTO Gain M0B M0E K3E M0F K23 Z -1 K3D Z -1 K1A K1B K3C Z -1 M0C 27 TRK Hold Reg DFCT TRK In Reg 2 -1 K19 - 140 - M0B M0D Z -1 K38 K3A 2 2 K39 -7 -7 TRK Servo Gain Up2; fs = 88.2kHz TRK AUTO Gain M0C Z -1 K36 K37 K3C M0E Z -1 K3D K3E M0F K23 TRK Hold Reg DFCT TRK In Reg Z -1 2 -1 K19 K3B Note) Set the MSB bit of the K39 and K3B coefficients to 0. TPS1, 0 BK3 Z -1 BK1 BK2 Z -1 BK6 BK9 Z -1 BK4 BK5 BK7 Z -1 TRK JMP Z -1 BK8 Z -1 PWM CXD2598Q FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) K0F M03 M05 K11 K13 Z -1 K0C 2 -7 K09 K0B K0D 27 K0E 2 -7 2 -7 80H K10 Z -1 Z -1 Z -1 7FH K0A 2 -7 K08 2 -7 81H M04 M06 M07 M1F To FCS Hold K0F To FCS Hold M1E FCS AUTO Gain FCS Hold Reg 2 DFCT FCS In Reg 2-1 K06 AGFON Sin ROM K06 Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E cofficients during quasi double accuracy to 0. FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) K2B M03 M05 M06 K2D Z -1 K2C 2 -7 K29 K2A Z -1 K28 2 -7 K25 K27 2 -7 80H Z -1 Z -1 7FH K26 2 -7 K24 2 -7 81H M04 M07 M1F To FCS Hold K2B To FCS Hold M1E FCS AUTO Gain K13 FCS Hold Reg 2 DFCT FCS In Reg 2 -1 K06 - 141 - FPS1, 0 BK3 Z -1 BK1 BK2 Z -1 BK6 Z -1 BK4 Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A cofficients during quasi double accuracy to 0. 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy PWM Z -1 FCS SRCH BK5 CXD2598Q TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK AUTO Gain M0C M0D M0E K22 K23 Z -1 80H K21 2 -7 K1F K20 M0F Z -1 K1E 2 -7 K1B K1D 2 -7 Z -1 7FH K1C 2 -7 2 -7 TRK Hold Reg DFCT TRK In Reg 2 -1 M0B K19 AGTON Z -1 Sin ROM K19 81H K1A Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 cofficients during quasi double accuracy to 0. TRK Servo Gain up1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK AUTO Gain M0C K3E M0F K23 Z -1 7FH K3D 2 -7 K1B K3C 2 -7 2 -7 80H Z -1 M0E 27 TRK Hold Reg DFCT TRK In Reg 2 -1 K19 M0B Z -1 81H K1A - 142 - M0C M0D Z -1 K38 2 -7 K37 K39 K3B K3C 2 -7 2 -7 K3A 80H Z -1 7FH 2 -7 2 -7 M0E Z -1 K3D K3E M0F TPS1, 0 BK3 Z -1 BK1 Z -1 BK2 BK6 Z -1 Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. TRK Servo Gain up2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK AUTO Gain K23 TRK Hold Reg DFCT TRK In Reg 2 -1 K19 M0B Z -1 81H K36 Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C cofficients during quasi double accuracy to 0. 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy BK9 Z -1 TRK JMP BK4 BK5 BK7 BK8 Z -1 Z -1 PWM CXD2598Q CXD2598Q SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D 2 -1 SLD In Reg SFID K00 Z -1 K01 2 -7 K02 2 -7 K04 Z -1 SLD MOV K03 SFSK (only when TGUP2 is used.) M00 M01 K05 TRK AUTO Gain M02 27 K07 PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2 -1 AGFON 2 -1 AGTON AGFON M08 Z -1 K14 K15 M09 Z -1 Slice TZC Reg M0A Z -1 K17 AUTO Gain Reg Slice - 143 - CXD2598Q Anti Shock fs = 88.2kHz TRK In Reg 2 -1 K12 M08 Z -1 M09 Z -1 K31 K16 2 -7 M0A Z -1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2 -1 VC, TE, FE, RFDC 2 -7 M08 Z -1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2 -1 THID K40 Z -1 K41 2 -7 K42 2 -7 K44 Z -1 K43 THSK (only when TGUP2 is used) M18 SLD In Reg M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS SERVO FILTER First-stage output M04 DFIS ($3E) K2B M1F K2B when using the FSC Gain Down filter M10 Z -1 K49 2 -7 K4A 2 -7 K4C K4B M11 Z -1 M12 FCS Hold Reg 2 M05 FCS SERVO FILTER Second-stage output K0F M1E K48 K4D Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 144 - CXD2598Q 5-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 180 G - Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 1k f - Frequency [Hz] -180 20k When using the preset coefficients with the boost function off. FOCUS frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 1k f - Frequency [Hz] -180 20k When using the preset coefficients with the boost function off. - 145 - - Phase [degree] G - Gain [dB] - Phase [degree] 6. Application Circuit FG TD TG PCMD LRCK DOUT V16M FD LDON Vcc GND RFO 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TE VSS VDD FILI CE SE FZC FE TE FE 50 VC 49 XTSL 48 TES1 47 TEST 46 VSS 45 VDD 44 FRDR 43 FFDR 42 TRDR 41 TFDR 40 SRDR 39 SFDR 38 FSTIO 37 SSTP 36 MDP 35 LOCK 34 PWMI 33 FOK 32 DFCT 31 DFCT LOCK FSTIO Driver Circuit +5V SSTP SLED SPDL GND CE VC MD2 PCO FILO BIAS ASYI LRCK ASYE V16M VCTL CLTV RFAC IGEN ADIO RFDC COUT MIRR VSS COUT MIRR WDCK DOUT VPCO ASYO PCMD LRCKI AVSS3 BCK 81 BCK 82 BCKI EMPH 83 EMPH 84 EMPHI 85 XVDD 86 XTAI 87 XTAO 88 XVSS 89 AVDD1 90 AOUT1 91 AIN1 92 LOUT1 93 AVSS1 94 AVSS2 ATSK WFCK XUGF XPCK GFS C2PO SCOR C4M VDD VSS SOUT SOCK XOLT 1 2 3 7 4 8 5 SQSO 6 SQCK SCSY SBSO 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 EXCK XRST SYSM DATA XLAT CLOK SENS SCLK XOLT SOUT XUGF XPCK SOCK SBSO WFCK C2PO C4M GFS FOK VDD DATA XLAT SQCK XRST SENS SCLK PWMI SCSY SQSO CXD2598Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. MUTE CLOK SCOR LDON GND WDCK VDD - 146 - 95 LOUT2 96 AIN2 97 AOUT2 98 AVDD2 RMUT 99 RMUT LMUT 100 LMUT PCMDI AVDD3 AVDD0 AVSS0 CXD2598Q Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05 81 50 + 0.4 14.0 - 0.1 17.9 0.4 15.8 0.4 A 100 31 1 0.65 + 0.15 0.3 - 0.1 30 0.13 M + 0.35 2.75 - 0.15 + 0.2 0.1 - 0.05 0.15 DETAIL A 0.8 0.2 0 to 10 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g - 147 - |
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