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| CD4046BC Micropower Phase-Locked Loop October 1987 Revised January 1999 CD4046BC Micropower Phase-Locked Loop General Description The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal. Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90 phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency. Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal (phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0 phase shift between signal input and comparator input. The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1 A, C1B, R1 and R2. The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 k or more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary. Features s Wide supply voltage range: 3.0V to 18V 70 W (typ.) at fo = s Low dynamic power consumption: 10 kHz, VDD = 5V s Low frequency drift: perature s VCO frequency: 1.3 MHz (typ.) at VDD = 10V 0.06%/C at VDD = 10V with tem- s High VCO linearity: 1% (typ.) Applications * FM demodulator and modulator * Frequency synthesis and multiplication * Frequency discrimination * Data synchronization and conditioning * Voltage-to-frequency conversion * Tone decoding * FSK modulation * Motor speed control Ordering Code: Order Number CD4046BCM CD4046BCN Package Number M16A N16E Package Description 16-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for SOIC and DIP Top View (c) 1999 Fairchild Semiconductor Corporation DS005968.prf www.fairchildsemi.com CD4046BC Block Diagram FIGURE 1. www.fairchildsemi.com 2 CD4046BC Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW -0.5 to +18 VDC -0.5 to VDD +0.5 VDC -65C to +150C Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3 to 15 VDC 0 to VDD VDC -40C to +85C Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 2) Symbol IDD Parameter Quiescent Device Current Conditions Pin 5 = VDD, Pin 14 = VDD, Pin 3, 9 = VSS VDD = 5V VDD = 10V VDD = 15V Pin 5 = VDD, Pin 14 = Open, Pin 3, 9 = VSS VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage Comparator and Signal In VIH HIGH Level Input Voltage Comparator and Signal In IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V All Inputs Except Signal Input VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V CIN PT Input Capacitance Total Power Dissipation Any Input (Note 3) fo = 10 kHz, R1 = 1 M, R2 = , = /2 VDD = 5V VDD = 10V VDD = 15V Note 3: Capacitance is guaranteed by periodic testing. Note 4: IOH and IOL are tested one output at a time. -40C Min Max Min +25C Typ Max +85C Min Max Units 20 40 80 0.005 0.01 0.015 20 40 80 150 300 600 A A A 70 530 1500 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 -0.52 -1.3 -3.6 -0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 -0.44 -1.1 -3.0 4.95 9.95 14.95 5 20 50 0 0 0 5 10 15 2.25 4.5 6.25 2.75 5.5 8.25 0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 55 410 1200 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 -0.36 -0.9 -2.4 -0.3 0.3 7.5 205 710 1800 0.05 0.05 0.05 A A A V V V V V V 1.5 3.0 4.0 V V V V V V mA mA mA mA mA mA -1.0 1.0 A A pF 0.07 0.6 2.4 mW mW mW 3 www.fairchildsemi.com CD4046BC AC Electrical Characteristics (Note 5) TA = 25C, CL = 50 pF Symbol VCO SECTION IDD Operating Current fo = 10 kHz, R1 = 1 M, R2 = , = /2 VDD = 5V VDD = 10V VDD = 15V fMAX Maximum Operating Frequency C1 = 50 pF, R1 = 10 k, R2 = , = VDD = 5V VDD = 10V VDD = 15V Linearity VCOIN = 2.5V 0.3V, R1 10 k, V DD = 5V VCOIN = 5V 2.5V, R1 400 k, VDD = 10V VCOIN = 7.5V 5V, R1 1 M, VDD = 15V Temperature-Frequency Stability No Frequency Offset, fMIN = 0 %/C1/. R2 = VDD = 5V VDD = 10V VDD = 15V Frequency Offset, fMIN 0 VDD = 5V VDD = 10V VDD = 15V VCOIN Input Resistance VDD = 5V VDD = 10V VDD = 15V VCO Output Duty Cycle VDD = 5V VDD = 10V VDD = 15V tTHL tTHL VCO Output Transition Time VDD = 5V VDD = 10V VDD = 15V PHASE COMPARATORS SECTION RIN Input Resistance Signal Input VDD = 5V VDD = 10V VDD = 15V Comparator Input VDD = 5V VDD = 10V VDD = 15V AC-Coupled Signal Input Voltage Sensitivity CSERIES = 1000 pF f = 50 kHz VDD = 5V VDD = 10V VDD = 15V 200 400 700 400 800 1400 mV mV mV 1 0.2 0.1 3 0.7 0.3 106 106 106 M M M M M M 0.12-0.24 0.04-0.08 0.015-0.03 0.06-0.12 0.05-0.1 0.03-0.06 106 106 106 50 50 50 90 50 45 200 100 80 %/C %/C %/C %/C %/C %/C M M M % % % ns ns ns 1 % 1 % 1 % 0.4 0.6 1.0 0.8 1.2 1.6 MHz MHz MHz 20 90 200 A A A Parameter Conditions Min Typ Max Units www.fairchildsemi.com 4 CD4046BC AC Electrical Characteristics Symbol DEMODULATOR OUTPUT VCOIN- VDEM Offset Voltage Parameter (Continued) Conditions Min Typ Max Units RS 10 k, VDD = 5V RS 10 k, VDD = 10V RS 50 k, VDD = 15V RS 50 k VCOIN = 2.5V 0.3V, VDD = 5V VCOIN = 5V 2.5V, VDD = 10V VCOIN = 7.5V 5V, VDD = 15V 1.50 1.50 1.50 2.2 2.2 2.2 V V V Linearity 0.1 0.6 0.8 % % % ZENER DIODE VZ RZ Zener Diode Voltage Zener Dynamic Resistance IZ = 50 A IZ = 1 mA 6.3 7.0 100 7.7 V Note 5: AC Parameters are guaranteed by DC correlated testing. Phase Comparator State Diagrams FIGURE 2. 5 www.fairchildsemi.com CD4046BC Typical Waveforms FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition www.fairchildsemi.com 6 CD4046BC Typical Performance Characteristics Typical Center Frequency vs C1 for R1 = 10 k, 100 k and 1 M FIGURE 5. Typical Frequency vs C1 for R2 = 10 k, 100 k and 1 M FIGURE 6. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). 7 www.fairchildsemi.com CD4046BC Typical fMAX/fMIN vs R2/R1 FIGURE 7. Typical VCO Power Dissipation at Center Frequency vs R1 FIGURE 8. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). www.fairchildsemi.com 8 CD4046BC Typical VCO Power Dissipation at fMIN vs R2 FIGURE 9. Typical Source Follower Power Dissipation vs RS FIGURE 10. Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). 9 www.fairchildsemi.com CD4046BC FIGURE 11. Typical VCO Linearity vs R1 and C1 Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (fMIN) + PD (RS); Phase Comparator II, PD (Total) = PD (fMIN). www.fairchildsemi.com 10 CD4046BC Design Information This information is a guide for approximating the value of external components for the CD4046B in a phase-lockedloop system. The selected external components must be within the following ranges: R1, R2 10 k, RS 10 k, C1 50 pF. In addition to the given design information, refer to Figure 5, Figure 6, Figure 7 for R1, R2 and C1 component selections. Using Phase Comparator I Characteristics VCO Frequency VCO Without Offset R2 = VCO With Offset Using Phase Comparator II VCO Without Offset R2 = VCO With Offset For No Signal Input Frequency Lock Range, 2 fL Frequency Capture Range, 2 fC VCO in PLL system will adjust to center frequency, fo 2 fL = fmax - fmin VCO in PLL system will adjust to lowest operating frequency, fmin 2 fL = full VCO frequency range Loop Filter Component Selection For 2 fC, see Ref. fC = fL Phase Angle Between Single and Comparator Locks on Harmonics of Center Frequency Signal Input Noise Rejection 90 at center frequency (fo), approximating 0 and 180 at ends of lock range (2 fL) Yes High Always 0 in lock No Low 11 www.fairchildsemi.com CD4046BC Using Phase Comparator I Characteristics VCO Component Selection VCO Without Offset R2 = Given: fo. Use fo with Figure 5 to determine R1 and C1. Given: fo and fL. Calculate fmin from the equation fmin = fo - fL. Use fmin with Figure 6 to determine R2 and C1. VCO With Offset Using Phase Comparator II VCO Without Offset R2 = Given: fmax. Calculate fo from the equation Given: fmin and fmax. Use fmin with Figure 6 to to determine R2 and C1. Calculate VCO With Offset Use fo with Figure 5 to Calculate determine R1 and C1. Use with Figure 7 from the equation to determine ratio R2/R1 to obtain R1. Use with Figure 7 to determine ratio R2/ R1 to obtain R1. References G.S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. Floyd Gardner, "Phaselock Techniques", John Wiley & Sons, 1966. www.fairchildsemi.com 12 CD4046BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Package Number M16A 13 www.fairchildsemi.com CD4046BC Micropower Phase-Locked Loop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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