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a
FEATURES On-Chip Reference and Track/Hold On-Chip Input Buffer 850 mW Typical Power Dissipation at 105 MSPS 500 MHz Analog Bandwidth SNR = 67 dB @ 49 MHz AIN at 105 MSPS SFDR = 80 dB @ 49 MHz AIN at 105 MSPS 2.0 V p-p Differential Analog Input Range Single +5.0 V Supply Operation +3.3 V CMOS/TTL Outputs Two's Complement Output Format APPLICATIONS Communications Basestations and `Zero-IF' Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) HDTV Broadcast Cameras and Film Scanners GENERAL INTRODUCTION
12-Bit, 80 MSPS/105 MSPS A/D Converter AD9432
FUNCTIONAL BLOCK DIAGRAM
VCC VDD AIN AIN ENCODE ENCODE PIPELINE ADC 12 OUTPUT STAGING 12 D11-D0 OR
BUF
T/H
TIMING
REF
AD9432
GND VREFOUT VREFIN
The AD9432 is a 12-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for high-speed conversion and ease of use. The product operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single 5.0 V power supply and a 105 MHz encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V logic. The encode input supports either differential or single-ended and is TTL/CMOS-compatible.
Fabricated on an advanced BiCMOS process, the AD9432 is available in a 52-lead plastic quad flatpack package (LQFP) specified over the industrial temperature range (-40C to +85C).
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD9432-SPECIFICATIONS otherwise noted)
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (AIN-AIN) Common-Mode Voltage Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power ANALOG REFERENCE Output Voltage Tempco Input Bias Current SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Output Rise Time (tR)2 Output Fall Time (tF) Out-of-Range Recovery Time Transient Response Time Latency DIGITAL INPUTS Encode Input Common Mode Differential Input (ENC-ENC) Single-Ended Logic "1" Voltage Logic "0" Voltage Input Resistance Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage (VDD = +3.3 V) Logic "0" Voltage (VDD = +3.3 V) Output Coding POWER SUPPLY Power Dissipation3 Power Supply Rejection Ratio (PSRR) IVCC IVDD +25C Full +25C Full Full +25C Full Full Full Full Full +25C +25C Full Full Full Full Full +25C +25C +25C +25C Full Full Full Full +25C +25C Full Full Full Full Full Full +25C Full Full I VI I VI VI I V V V VI VI V V VI V VI VI IV IV IV V V VI VI V V V V IV V V IV IV VI V VI VI Temp Test Level
(VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless
AD9432BST-80 Min Typ Max 12 -0.75 0.25 -1.0 0.5 -1.0 0.5 -1.5 1.0 Guaranteed -3 +2 150 1.0 3.0 0 3 4 500 2.5 50 15 +0.75 +1.0 +1.0 +1.5 +7 -0.75 -1.0 -1.0 -1.5 -3 AD9432BST-105 Min Typ Max 12 0.25 0.5 0.5 1.0 Guaranteed +2 150 1.0 3.0 0 3 4 500 2.5 50 15 +0.75 +1.0 +1.0 +1.5 +7
Unit Bits LSB LSB LSB LSB % FS ppm/C V V mV k pF MHz V ppm/C MSPS MSPS ns ns ns ps rms ns ns ns ns ns ns Cycles V mV V V k pF V V
-5 2
+5 4
-5 2
+5 4
2.4
2.6 50
2.4
2.6 50
80 1 4.0 4.0 6.2 6.2 2.0 0.25 5.3 5.5 2.1 1.9 2 2 10 1.6 750 2.0 3 5 4.5 0.8 8
105 1 4.0 4.0 4.8 4.8 2.0 0.25 5.3 5.5 2.1 1.9 2 2 10 1.6 750 2.0 3 5 4.5 0.8 8
3.0
3.0 8.0
8.0
VDD - 0.05 0.05 Two's Complement 790 0.5 158 9.5 1000 +5 200 12.2
VDD - 0.05 0.05 Two's Complement 850 0.5 170 12.5 1100 +5 220 16
Full +25C Full Full
VI I VI VI
-5
-5
mW mV/V mA mA
-2-
REV. B
AD9432
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Effective Number of Bits fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Second and Third Harmonic Distortion fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Worst Harmonic or Spur (Excluding Second and Third) fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Two-Tone Intermod Distortion (IMD) fIN1 = 29.3 MHz; fIN2 = 30.3 MHz fIN1 = 70.3 MHz; fIN2 = 71.3 MHz
4
Temp
Test Level
AD9432BST-80 Min Typ Max
AD9432BST-105 Min Typ Max
Unit
+25C +25C +25C +25C
I I I V
65.5 65
67.5 67.2 67.0 66.1
65.5 64
67.5 67.2 67.0 66.1
dB dB dB dB
+25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C
I I I V V V V V I I I V
65 64.5
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
65 63
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc
-75 -73
-85 -85 -83 -80
-75 -72
-85 -83 -80 -78
+25C +25C +25C +25C +25C +25C
I I I V V V
-80 -80
-90 -90 -90 -90 -75 -66
-80 -80
-90 -90 -90 -90 -75 -66
dBc dBc dBc dBc dBc dBc
NOTES 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input). 2 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. Rise and fall times measured from 10% to 90%. 3 Power dissipation measured with encode at rated speed and a dc analog input. (Outputs Static, I VDD = 0.) 4 SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 2 V full-scale input range. Typical JA for LQFP package = 50C/W. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V VREFIN . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE Temperature Ranges -40C to +85C Package Descriptions Package Option
Model AD9432BST -80, -105
AD9432/PCB +25C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9432 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
52-Lead Plastic Quad ST-52 Flatpack (LQFP) Evaluation Board
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD9432
GND GND VCC GND VCC DNC GND
39 GND 38 GND 37 VCC 36 VCC 35 GND 34 GND 33 GND 32 VDD 31 DGND 30 D0 (LSB) 29 D1 28 D2 27 D3 14 15 16 17 18 19 20 21 22 23 24 25 26
VCC
II
100% production tested at +25C and sample tested at specified temperatures.
52 51 50 49 48 47 46 45 44 43 42 41 40
GND 1 VCC 2 GND 3 GND 4 VCC 5 VCC 6 ENCODE 7 ENCODE 8 GND 9 VCC 10 GND 11 DGND 12 VDD 13
PIN 1 IDENTIFIER
III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range.
AIN AIN
I
100% production tested.
AD9432
TOP VIEW (Not to Scale)
(MSB) D11 D10 D9
OR
VREFOUT VREFIN VCC
EXPLANATION OF TEST LEVELS Test Level
PIN CONFIGURATION
DGND D5
D8 D7
D6 DGND
PIN FUNCTION DESCRIPTIONS Pin Number AD9432BST 1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 2, 5, 6, 10, 36, 37, 42, 44, 47, 52 7 8 14 15-20, 25-30 12, 21, 24, 31 13, 22, 23, 32 41 45 46 49 50 DEFINITION OF SPECIFICATIONS
Name GND VCC ENCODE ENCODE OR D11-D6, D5-D0 DGND VDD DNC VREFIN VREFOUT AIN AIN
Function Analog Ground. Analog Supply (+5 V). Encode Clock for ADC-Complementary. Encode Clock for ADC-True (ADC samples on rising edge of ENCODE). Out of Range Output. Digital Output. Digital Output Ground. Digital Output Power Supply (2.7 V to 3.6 V). Do Not Connect. Reference Input for ADC (2.5 V Typical); Bypass with 0.1 F to Ground. Internal Reference Output (2.5 V Typical). Analog Input-True. Analog Input-Complementary. Minimum Conversion Rate
Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise Plus Distortion (SINAD)
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Integral Nonlinearity
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. -4-
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. REV. B
VDD VDD
D4
AD9432
Spurious-Free Dynamic Range (SFDR) Two-Tone SFDR
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Worst Harmonic
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc.
SAMPLE N-1 AIN
SAMPLE N
SAMPLE N+10
SAMPLE N+11
tA t EH
ENCODE ENCODE
SAMPLE N+1
SAMPLE N+9
t EL
1/f S
t PD
D11-D0 DATA N-11 DATA N-10 N-9 N-2 DATA N-1 DATA N
tV
DATA N + 1
Figure 1. Timing Diagram
VCC
VCC
17k ENCODE
VREFIN
17k ENCODE 100 100 8k
8k
Figure 2. Equivalent Voltage Reference Input Circuit
VCC
Figure 4. Equivalent Encode Input Circuit
VDD
Q1 NPN VREFOUT
DIGITAL OUTPUT
VREF OUTPUT
DIGITAL OUTPUT
Figure 3. Equivalent Voltage Reference Output Circuit
VCC
Figure 5. Equivalent Digital Output Circuit
5k AIN
5k
AIN 7k 7k
ANALOG INPUT
Figure 6. Equivalent Analog Input Circuit
REV. B
-5-
AD9432 -Typical Performance Characteristics
90 AIN = 10.3MHz 85 SFDR 80 65 70
75
SNR - dB
SNR SINAD
dB
60
70
55 65
60
50 0 20 40 60 80 100 ENCODE - MSPS 120 140 160 0 50 100 150 200 AIN INPUT FREQUENCY - MHz (-0.5dBFS) 250
Figure 7. SNR/SINAD/SFDR vs. fS: fIN = 10.3 MHz
Figure 10. SNR vs. AIN Input Frequency, Encode = 105 MSPS
-50 AIN = 10.3MHz -55
100 ENCODE = 105MSPS 90
-60 -65 -70
dBc
80 2nd or 3rd (-6.0dBFS)
dBc
3rd
-75 -80 -85 -90 -95 2nd
70
60
50
2nd or 3rd (-0.5dBFS) 2nd or 3rd (-3.0dBFS)
-100 0 20 40 60 80 100 ENCODE - MSPS 120 140 160
40 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY - MHz 180 200
Figure 8. Harmonics vs. fS: fIN = 10.3 MHz
Figure 11. Harmonics vs. fIN: fS = 105 MSPS
70 ENCODE = 105MSPS 65
100 ENCODE = 105MSPS WORST OTHER (-0.5dBFS) 90
60 SINAD (-3.0dBFS)
80 WORST OTHER (-6.0dBFS)
dBc
WORST OTHER (-3.0dBFS) 70
dB
55
SINAD (-6.0dBFS) SINAD (-0.5dBFS)
50
60
45
50
40 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY - MHz 180 200
40 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY - MHz 180 200
Figure 9. SINAD vs. fIN: fS = 105 MSPS
Figure 12. Worst-Case Spur (Other than Second and Third) vs. fIN: fS = 105 MSPS
-6-
REV. B
AD9432
0 -10 -20 -30 -40 -50
dB
0
ENCODE = 105MSPS AIN = 10.3MHz (-0.53dBFS) SNR = 67.32dB SINAD = 67.07dB SFDR = -85dBc
-10 -20 -30 -40 -50
ENCODE = 105MSPS AIN = 50.3MHz (-0.46dBFS) SNR = 67.0dB SINAD = 66.7dB SFDR = -80dBc
dB
-60 -70 -80 -90
-60 -70 -80 -90
-100 -110 -120 SAMPLES
-100 -110 -120 SAMPLES
Figure 13. Spectrum: fS = 105 MSPS, fIN = 10.3 MHz
Figure 16. Spectrum: fS = 105 MSPS, fIN = 50.3 MHz
0 -10 -20 -30 -40 -50 ENCODE = 105MSPS AIN = 27.0MHz (-0.52dBFS) SNR = 67.3dB SINAD = 67.0dB SFDR = -83.1dBc
0 -10 -20 -30 -40 -50 AIN1 = 29.3MHz (-7dBFS) AIN2 = 30.3MHz (-7dBFS) ENCODE = 105MSPS
dBc
dB
-60 -70 -80 -90 -100 -110 -120 SAMPLES
-60 -70 -80 -90
-100 -110 -120 SAMPLES
Figure 14. Spectrum: fS = 105 MSPS, fIN = 27 MHz
Figure 17. Two-Tone Spectrum, Wideband: fS = 105 MSPS, AIN1 = 29.3 MHz, AIN2 = 30.3 MHz
0 -10 -20 -30 -40 -50 ENCODE = 105MSPS AIN = 40.9MHz (-0.56dBFS) SNR = 67.2dB SINAD = 66.9dB SFDR = -80dBc
0 -10 -20 -30 -40 -50 AIN1 = 70.3MHz (-7dBFS) AIN2 = 71.3MHz (-7dBFS) ENCODE = 105MSPS
dBc
dB
-60 -70 -80 -90 -100 -110 -120 SAMPLES
-60 -70 -80 -90
-100 -110 -120 SAMPLES
Figure 15. Spectrum: fS = 105 MSPS, fIN = 40.9 MHz
Figure 18. Two-Tone Spectrum, Wideband: fS = 105 MSPS, AIN1 = 70.3 MHz, AIN2 = 71.3 MHz
REV. B
-7-
AD9432
110
WORST CASE SPURIOUS - dBc AND dBFS
1.00 0.75 0.50
100 90 80 70 60 50 40 30 20 dBc ENCODE = 105MSPS AIN = 50.3MHz
LSB
dBFS
0.25 0.00
-0.25 -0.50 -0.75
10 0 -80
-1.00
-70
-60 -50 -40 -30 -20 -10 ANALOG INPUT POWER LEVEL - dBFS
0
INL
Figure 19. Single Tone SFDR
Figure 21. Integral Nonlinearity: fS = 105 MSPS
1.00 0.75 0.50
3.0
2.5
0.25 LSB 0.00
-0.25 -0.50 -0.75 -1.00 DNL
VOLTAGE - V
2.0 1.5 0 2 4 6 CURRENT - mA 8 10
Figure 20. Differential Nonlinearity: fS = 105 MSPS
Figure 22. Voltage Reference Output vs. Current Load
-8-
REV. B
AD9432
APPLICATION NOTES Theory of Operation
The AD9432 is a multibit pipeline converter that uses a switched capacitor architecture. Optimized for high speed, this converter provides flat dynamic performance up to frequencies near Nyquist. DNL transitional errors are calibrated at final test to a typical accuracy of 0.25 LSB or less.
Often, the cleanest clock source is a crystal oscillator producing a pure sine wave. In this configuration, or with any roughly symmetrical clock input, the input can be ac-coupled and biased to a reference voltage that also provides the ENCODE. This ensures that the reference voltage is centered on the encode signal.
Digital Outputs
USING THE AD9432
ENCODE Input
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOScompatible for lower power consumption.
Analog Input
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9432, and the user is advised to give commensurate thought to the clock source. The ENCODE input supports either differential or single-ended and is fully TTL/CMOS compatible. Note that the ENCODE inputs cannot be driven directly from PECL level signals (VIHD is 3.5 V max). PECL level signals can easily be accommodated by ac coupling as shown in Figure 23. Good performance is obtained using an MC10EL16 in the circuit to drive the encode inputs.
0.1 F PECL GATE 510 510 0.1 F
The analog input to the AD9432 is a differential buffer. The input buffer is self-biased by an on-chip resistor divider that sets the dc common-mode voltage to a nominal 3 V (see Equivalent Circuits section). Rated performance is achieved by driving the input differentially. Minimum input offset voltage is obtained when driving from a source with a low differential source impedance such as a transformer in ac applications. Capacitive coupling at the inputs will increase the input offset voltage by as much as 25 mV. Driving the ADC single-endedly will degrade performance. For best dynamic performance, impedances at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9432 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 2.0 V p-p. Each analog input will be 1 V p-p when driven differentially.
4.0
AD9432
ENCODE ENCODE
AIN 3.5
GND
Figure 23. AC Coupling to ENCODE Inputs
ENCODE Voltage Level Definition
3.0
The voltage level definitions for driving ENCODE and ENCODE in single-ended and differential mode are shown in Figure 24. ENCODE Inputs Differential Signal Amplitude (VID) . . . . . . . . . . . 500 mV min, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mV nom High Differential Input Voltage (VIHD) . . . . . . . . . . 3.5 V max Low Differential Input Voltage (VILD) . . . . . . . . . . . . . 0 V min Common-Mode Input (VICM) . . . . . . . 1.25 V min, 1.6 V nom High Single-Ended Voltage (VIHS) . . . . . 2 V min to 3.5 V max Low Single-Ended Voltage (VILS) . . . . . 0 V min to 0.8 V max
ENCODE ENCODE VIHD VICM VILD VID
AIN 2.5
2.0
Figure 25. Full-Scale Analog Input Range
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the AD9432 (VREFOUT). In normal operation the internal reference is used by strapping Pin 45 to Pin 46 and placing a 0.1 F decoupling capacitor at VREFIN. The input range can be adjusted by varying the reference voltage applied to the AD9432. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage changes linearly.
Timing
VIHS ENCODE
0.1 F VILS
Figure 24. Differential and Single-Ended Input Levels
The AD9432 provides latched data outputs, with 10 pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figure 1). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9432; these transients can detract from the converter's dynamic performance.
REV. B
-9-
AD9432
The minimum guaranteed conversion rate of the AD9432 is 1 MSPS. At internal clock rates below 1 MSPS, dynamic performance may degrade. Therefore, input clock rates below 1 MHz should be avoided.
Table I. Output Coding (VREF = +2.5 V) (Two's Complement)
dB
66 65 SNR 64
Code +2047 * * 0 -1 * * -2048
AIN-AIN (V) 1.000 * * 0 -0.00049 * * -1.000
Digital Output 0111 1111 1111 * * 0000 0000 0000 1111 1111 1111 * * 1000 0000 0000
63 SINAD 62
61
60 0 20 AIN MHz 40 60
Figure 27. Measured SNR and SINAD (Encode = 105 MSPS)
-70
Using the AD8138 to Drive the AD9432
H2
A new differential output op amp from Analog Devices, Inc., the AD8138 can be used to drive the AD9432 in dc-coupled applications. The AD8138 was specifically designed for ADC driver applications. Superior SNR performance is maintained up to analog frequencies of 30 MHz. The AD8138 op amp provides single-ended-to-differential conversion, providing for a low cost option to transformer coupling for ac applications as well. The circuit in Figure 26 was breadboarded and the measured performance is shown in Figures 27 and 28. The figures shown are for 5 V supplies at the AD8138--performance dropped by about 1 dB-2 dB with a single +5 V supply at the AD8138. Figure 27 shows SNR and SINAD for a -1 dBFS analog input frequency varied from 2 MHz to 40 MHz with an encode rate of 105 MSPS. The measurements are for nominal conditions at room temperature. Figure 28 shows the second and third harmonic distortion performance under the same conditions. The dc common-mode voltage for the AD8138 outputs can be adjusted via input VOCM to provide the 3 V common-mode voltage the AD9432 inputs require.
500
-80
dB
H3
-90
-100 0 20 AIN MHz 40 60
Figure 28. Measured Second and Third Order Harmonic Distortion (Encode = 105 MSPS)
EVALUATION BOARD
The AD9432 evaluation board offers an easy way to test the AD9432. It requires an analog signal, encode clock, and power supplies as inputs. The clock is buffered on the board to provide the clocks for an on-board DAC and latches. The digital outputs and output clock are available at a standard 37-pin connector P7.
Power Connector
AD9432
10pF
Power is supplied to the board via two detachable 4-pin power strips P30, P40.
P40
VIN
50 500 50 AD8138 22pF 50 VOCM 5V 500 2k AIN AIN
P1 P2 P3 P4
P30
VCC2 5 V/165 mA GND VCC 5 V/200 mA GND
DAC Supply ADC Analog Supply
25
500
10pF
3k
0.1 F
P5 P6 P7 P8
VD GND
No Connect No Connect 3.3 V /105 mA Latch, ADC Digital Output Supply
Figure 26. AD8138/AD9432 Schematic
-10-
REV. B
AD9432
Analog Inputs
The evaluation board accepts a 2 V p-p analog input signal at SMB connector P2. This single-ended signal is ac-coupled by capacitor C11 and drives a wideband RF transformer T1 (MiniCircuits ADT1-1WT) that converts the single-ended signal to a differential signal. (The AD9432 should be driven differentially to provide optimum performance.) The evaluation board is shipped with termination resistors R4, R5, which provide the effective 50 termination impedance; input termination resistor R10 is optional. Note: The second harmonic distortion that some RF transformers tend to introduce at high frequencies can be reduced by coupling two transformers in series as shown in Figure 29 below. (Improvements on the order of 3 dB-4 dB can be realized.)
TO AIN+ C2 0.1 F IN R2 25 C1 0.1 F TO AIN- T1 T2 R1 25
Note: Jitter performance on the clock source is critical at this performance level; a stable, crystal-controlled signal generator is used to generate all of the ADC performance plots. Figure 31 shows the Encode+ clock at the ADC. The 3 V Latch clock generated on the card is also shown in the plot.
TEK STOP: 5.00GS/s 86 ACQS [T]
C1 MAX 2.33V C1 MIN 810mV T
C1 FREQ 106.3167MHz LOW SIGNAL AMPLITUDE
2
Figure 29. Improving Second Harmonic Distortion Performance
TEK STOP: 5.00GS/s 14 ACQS [T]
CH1
1.00V
CH2
1.00V
M 5.00ns CH1
1.20V
Figure 31. Encode+ Clock and Latch Clock
DATA OUTPUTS
T
C1 MAX 3.4V C1 MIN 2.5mV
C1 FREQ 49.995MHz LOW SIGNAL AMPLITUDE
The ADC digital outputs are latched on the board by two 574s, the latch outputs are available at the 37-pin connector at Pins 25-36. A latch output clock (data ready) is available at Pin 21, with the complement at Pin 2. There are series termination resistors on the data and clock outputs. These can be changed if required to accommodate different loading situations. Figure 32 shows a data bit switching and output clock (DR) at the connector.
TEK STOP: 5.00GS/s 265 ACQS [T]
2
CH1 500mV CH3 2.00V
CH2
500mV
M 5.00ns CH1
3.00V
C1 MAX 3.06V C1 MIN -390mV T C1 FREQ 105.4562MHz
Figure 30. Analog Input Levels
The full-scale analog inputs to the ADC should be two 1 V p-p signals 180 degrees out of phase with each other as shown in Figure 30. The analog inputs are dc biased by two on-chip resistor dividers that set the common-mode voltage to approximately 0.6 x VCC (0.6 x 5 = 3 V). AIN+ and AIN- each vary between 2.5 V and 3.5 V as shown in the two upper traces in Figure 30. The lower trace is the input at SMB P2 (on a 2 V/div scale).
Encode
2
The encode input to the board is at SMB connector P3. The (>1 V p-p) input is ac-coupled and drives two high-speed differential line receivers (MC10EL16). These receivers provide subnanosecond rise times at their outputs--a requirement for the ADC clock inputs for optimum performance. The EL16 outputs are PECL levels and must be ac-coupled to meet the common-mode dc levels required at the AD9432 encode inputs. A PECL/TTL translator (MC100ELT23), provides the clocks required at the output latches, DAC, and 37-pin connector.
CH1
1.00V
CH2
1.00V
M 5.00ns
CH1
1.20V
Figure 32. Data Bit and Clock at 37-Pin Connector
REFERENCE
The AD9432 has an on-chip reference of 2.5 V available at VREFOUT (Pin 46). Most applications will simply tie this output to the VREFIN input (Pin 45). This is accomplished jumping E4 to E6 on the board. An external voltage reference can drive the VREFIN pin if desired by strapping E4 to E3 and placing an AD780 voltage reference on the board (not supplied).
REV. B
-11-
AD9432
DAC TROUBLESHOOTING
The evaluation board has an on board reconstruction DAC (AD9752). This is placed only to facilitate testing and debug of the board. It should not be used to measure the performance of the ADC, as it will not accurately indicate the ADC performance. The DAC output is available at SMB P1. It will drive a 50 load. Provision to power-down the DAC is at Pin 15 at the DAC.
PCB LAYOUT
If the board does not seem to be working correctly, try the following: * Verify power at IC pins. * Check that all jumpers are in the correct position for the desired mode of operation. * Verify VREF is at 2.5 V. * Try running encode clock and analog inputs at low speeds (10 MSPS/1 MHz) and monitor 574 outputs, DAC output, and ADC outputs for toggling. The AD9432 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
The PCB is designed on a four-layer (1 oz. Cu) board. Components and routing are on the top layer with a ground flood for additional isolation. Test and ground points were judiciously placed to facilitate high-speed probing. A common ground plane exists on the second layer. The third layer has three split power planes, two for the ADC and one for support logic. The DAC, components, and routing are located on the bottom layer.
PCB Bill of Materials
# 1
Quantity 30
REFDES C1-C8, C10-C13, C17, C19-C22, C27-C29, C41, C42, C47, C48, C53, C56, C58, C60, C61, C70 C9 C14, C18, C31, C34 C15 E1-E13, E30, E32, E40, E42, E43 P1, P2, P3 P7 P30, P40 R1, R2, R7, R8, R10, R18 (R1, R2, R10 Optional) R3, R35 R25, R26, R31, R32 R6, R24 RP1-RP4 T1 U1 U2 U3, U4 U9 U12-U13 Z1 Z2, Z3 R4, R5, R15
Device Capacitor
Package 603
Value 0.1 F 0.01 F 10 F 1 F
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1 4 1 18 3 1 2 6 2 4 2 4 1 1 1 2 1 2 1 2 3
Capacitor Capacitor Capacitor E-HOLE Connector 37-Pin Connector Power Connector Resistor Resistor Resistor Resistor RES PAK Transformer DAC Reference (Not Supplied) Inverter (U4 Not Supplied) ADC Latch PECL/TTL Translator Differential Receiver Resistor
603 CAPTAJD CAPTAJD Test Point SMB Female 1206 1206 1206 1206
AMP 747462-2 50 100 500 2 k 100 Mini-Circuits ADT1-1WT AD9752 AD780N NC7SZ04P5 AD9432 74AC574M MC100ELT23 MC10EL16 24.9
SOIC SOIC SC70 52QFP SOIC SOIC SOIC 1206
-12-
REV. B
34
9
10
32
23
22
36 13
52
47
44
37
6
5
AGND
2
4
3
31
24
21
33
11
35
12
51
48
43
Figure 33a. PCB Schematic
-13-
AGND AGND AGND C61 0.1 F R31 500 C7 0.1 F 8 VCC 7 6 5 AGND R32 500 C8 0.1 F Z2 1 2 3 DB VBB MC10EL16 AGND AGND AGND Z3 VCC2 R25 500 C60 0.1 F AGND Z1 VEE QB R35 100 C58 0.1 F 4 D Q NC VCC AGND R3 100 AGND C6 0.1 F MC10EL16 1 NC 2 D 3 DB 4 VBB 8 VCC 7 Q 6 QB 5 VEE R26 500 1 D0 2 D08 3 D18 4 D1 8 VCC 7 Q0 6 Q1 5 GND MC100ELT23 AGND AGND
38
AGND
1
REV. B
VCC E2 U2 (NOT SUPPLIED) C4 0.1 F AGND VCC U9 EXTREF VCC 41 40 (MSB) D11 EXTREF AGND 45 46 VREFOUT VREFIN E4 C2 E5 0.1 F E3 39 D10 D9 D8 D7 D6 AIN R5 24.9 8 AIN ENC C70 0.1 F C9 0.01 F 7 ENC D5 D4 49 AIN 50 AIN 15 16 17 18 19 20 25 26 8 7 6 8 7 6 55 44 33 22 AGND AGND AGND 11 RP1 OR 14 FLOAT AGND 42 + C14 10 F VCC 8 7 6 8 7 6 55 44 33 22 11 E1 VD 100 RPAK_742 DR D11 D10 D9 D8 D7 D6 16 16 D5 14 14 15 15 AGND AD780N AGND 1 NC 2 +VIN 3 TEMP 4 GND 8 2.5/3V 7 NC 6 VOUT 5 TRIM 9 9 10 10 11 11 12 12 13 13
VCC
C15 1F
AD9432
ANALOG
AGND R4 24.9 2
P2 SMBPN
C11 0.1 F
AGND
T1 ADT1-1WT 1 6
100 RP2 RPAK_742 D4 D3 D2 D1 D0 14 14 15 15 16 16
3 PAI
4 SEC
R10 50 (OPTIONAL)
27 D3 28 D2 29 D1 30 D0
9 9 10 10 11 11 12 12 13 13
ENCODE
P3 SMBPN
C47 0.1 F
VD (R1, R2, OPTIONAL) AGND C1 0.1 F VCC2 AGND AGND NC7SZ04P5 U4 (NOT SUPPLIED) AGND R7 50 DR R8 50 DR NC = NO CONNECT R1 100 1 2 NC A 3 GND VCC Y 5 4 VD C5 0.1 F AGND
R2 100 CLOCK
AD9432
OUT BYPASS VCC + C34 10 F C48 0.1 F AGND C19 0.1 F C20 0.1 F C21 0.1 F C22 0.1 F C56 0.1 F C53 0.1 F C18 10 F VCC2
P30
AGND
8
AGND
7
VD (+3V)
AD9432
6
NC
5 OUT BYPASS VD + C31 10 F AGND C28 0.1 F C27 0.1 F C29 0.1 F C41 0.1 F C42 0.1 F VD LATCHES
NC
P40
4
AGND
3
VCC (+5V)
2
AGND
1 AGND
VCC2 (+5V)
U13 AGND VD 16 16 15 15 14 14 AGND AGND AGND AGND AGND AGND AGND AGND AGND U12 20 19 VD 18 AGND 100 RP4 AGND AGND AGND AGND AGND AGND AGND DR BDR CLOCK INV MSB AGND RPAK_742 18 20 19 100 RP3
P7 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 2 P2 1 P1 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 DR B0R B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B0 B1 B2 B3 B4
D0 D1 D2 D3 D4 GND 13 12 11 10 9 RPAK_742 13 12 11 10 9 CLOCK 74AC574M GROUND PLANE CONNECTING E-HOLES E30 E32 E9 E10 E11 AGND E12 D8 D9 D10 D11 DR GND 74AC574M
1 OUT_EN VCC 2 D0 Q0 3 D1 Q1 4 D2 Q2 5 D3 Q3 6 D4 Q4 7 D5 Q5 8 D6 Q6 9 D7 Q7 10 GND CLOCK 17 16 15 14 13 12 11 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8
SCOPE TEST POINTS
D0
E42
D11
E43
Figure 33b. PCB Schematic (Continued)
GND D5 D6 D7
-14-
17 16 15 14 13 12 11 AGND U3 VCC U1 MSB 1 D11 CLK DVDD DCON NC2 AVDD ICOMP IOUTA IOUTB ACON NC3 FSADJ D0 13 14 NC NC1 REFIO REFLO SLEEP AD9752 NC = NO CONNECT AGND VCC2 AGND AGND AGND 24 23 22 21 20 19 18 D1 17 16 15 R6 2k E1 E8 C13 0.1 F R24 2k AGND AGND R15 24.9 C10 0.1 F AGND 25 26 27 GND D10 D9 D8 D7 D6 2 3 4 5 6 7 D5 8 D4 9 D3 D2 10 11 12 D10 D9 NC7SZ04P5 D8 D7 D6 D5 D4 D3 D2 D1 D0 28 CLOCK Y 4 5 VCC2 C3 0.1 F AGND C17 0.1 F VCC2
DR
E40
CLOCK
E6
DR
E7
1 OUT_EN VCC 2 D0 Q0 3 D1 Q1 4 D2 Q2 5 D3 Q3 6 D4 Q4 7 D5 Q5 8 D6 Q6 9 D7 Q7 10 GND CLOCK
1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8
16 16 B5 B6 15 15 B7 14 14 B8 13 13 B9 12 12 11 11 B10 10 10 B11 99
1
NC
INV
2
A
AGND
3
GND
DACOUT
VCC2 P1 SMBPN R18 50
C12 0.1 F
AGND
REV. B
AD9432
Figure 34. Top Silkscreen
Figure 37. Split Power Plane
Figure 35. Top Level Routing
Figure 38. Bottom Layer Route
Figure 36. Ground Plane
Figure 39. Bottom Silkscreen
REV. B
-15-
AD9432
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead Plastic Quad Flatpack (LQFP) (ST-52)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
40 39
0.472 (12.00) SQ
27 26
SEATING PLANE TOP VIEW
(PINS DOWN)
0.394 (10.0) SQ
52
14 1 13
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.026 (0.65) BSC
0.015 (0.38) 0.009 (0.22)
-16-
REV. B
PRINTED IN U.S.A.
C3619-0-6/00 (rev. B) 00587

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