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FEATURES Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC Low Power: 90 mW at 100 MSPS per Channel On-Chip Reference and Track/Holds 475 MHz Analog Bandwidth Each Channel SNR = 47 dB @ 41 MHz 1 V p-p Analog Input Range Each Channel Single +3.0 V Supply Operation (2.7 V-3.6 V) Standby Mode for Single Channel Operation Twos Complement or Offset Binary Output Mode Output Data Alignment Mode APPLICATIONS Battery Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes I and Q Communications
ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB
8-Bit, 40/80/100 MSPS Dual A/D Converter AD9288
FUNCTIONAL BLOCK DIAGRAM
VDD TIMING
OUTPUT REGISTER
AD9288
T/H ADC 8
8
D7A-D0A SELECT #1 SELECT #2
REF
OUTPUT REGISTER
DATA FORMAT SELECT 8 D7B-D0B
T/H
ADC
8
TIMING
VD
GND
VDD
GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.
The encode input is TTL/CMOS compatible and the 8-bit digital outputs can be operated from +3.0 V (2.5 V to 3.6 V) supplies. User-selectable options are available to offer a combination of standby modes, digital data formats and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface mount plastic package (7 x 7 mm, 1.4 mm LQFP) specified over the industrial temperature range (-40C to +85C).
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9288-SPECIFICATIONS (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 Gain Matching Voltage Matching ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage
3
DD
= 3.0 V; VD = 3.0 V, Differential Input; External reference unless otherwise noted.)
AD9288BST-80 Min Typ Max 8 +1.25 +1.50 +1.25 +1.50 -6 -8 0.5 0.50 +1.25 +1.50 +1.25 +1.50 -6 -8 AD9288BST-40 Min Typ Max 8 0.5 0.50 +1.25 +1.50 +1.25 +1.50 Units Bits LSB LSB LSB LSB % FS % FS ppm/C % FS mV
Temp
Test Level
AD9288BST-100 Min Typ Max 8
+25C Full +25C Full Full +25C Full Full +25C +25C
I VI I VI VI I VI VI V V
0.5 0.50
-6 -8
Guaranteed 2.5 +6 +8 80 1.5 15
Guaranteed 2.5 +6 +8 80 1.5 15
Guaranteed 2.5 +6 +8 80 1.5 15
Full Full +25C Full Full Full +25C Full +25C +25C Full +25C +25C +25C +25C +25C Full Full Full Full Full Full +25C Full Full Full Full +25C +25C +25C
V V I VI VI VI I VI V V VI IV IV IV V V VI VI VI VI VI VI V VI VI VI VI I V V
-35 1.2 7 5
512 200 10 40 1.25 130 10 2 475
+35 1.3 13 16
-35 1.2 7 5
512 200 10 40 1.25 130 10 2 475
+35 1.3 13 16
-35 1.2 7 5
512 200 10 40 1.25 130 10 2 475
+35 1.3 13 16
mV p-p mV mV mV V ppm/C k k pF MHz MSPS MSPS ns ns ns ps rms ns ns V V A A pF V V mW mW mV/V ns ns
100 4.3 4.3 0 5 3.0 4.5 2.0 0.8 1 1 2.0 2.45 0.05 180 6 8 2 2 218 11 20 1 1000 1000
80 5.0 5.0 0 5 3.0 4.5 2.0 0.8 1 1 2.0 2.45 0.05 171 6 8 2 2 207 11 20 1 1000 1000
40 8.0 8.0 0 5 3.0 4.5 2.0 0.8 1 1 2.0 2.45 0.05 156 6 8 2 2 189 11 20 1 1000 1000
POWER SUPPLY Power Dissipation4 Standby Dissipation4, 5 Power Supply Rejection Ratio (PSRR) DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz
6
+25C +25C +25C
I I I
44
47.5 47.5 47.0
44
47.5 47
44
47.5
dB dB dB
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AD9288
Parameter
6
Temp
Test Level
AD9288BST-100 Min Typ Max
AD9288BST-80 Min Typ Max
AD9288BST-40 Min Typ Max
Units
DYNAMIC PERFORMANCE (Continued) Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz +25C I fIN = 26 MHz +25C I fIN = 41 MHz +25C I Effective Number of Bits fIN = 10.3 MHz +25C I fIN = 26 MHz +25C I +25C I fIN = 41 MHz 2nd Harmonic Distortion +25C I fIN = 10.3 MHz fIN = 26 MHz +25C I +25C I fIN = 41 MHz 3rd Harmonic Distortion +25C I fIN = 10.3 MHz fIN = 26 MHz +25C I +25C I fIN = 41 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz +25C V
44
47 47 47 7.5 7.5 7.5 70 70 70 60 60 60 60
44
47 47 47 7.5 7.5 7.5 70 70 70 60 60 60 60
44
47
dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc
7.0
7.5
7.0
7.0
55
70
55
55
55
60
55
52
60
NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and t PD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. 3 Digital supply current based on V DD = +3.0 V output drive with <10 pF loading under dynamic test conditions. 4 Power dissipation measured under the following conditions: f S = 100 MSPS, analog input is -0.7 dBFS, both channels in operation. 5 Standby dissipation calculated with encode clock in operation. 6 SNR/harmonics based on an analog input voltage of -0.7 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V Analog Inputs . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Test Level I 100% production tested. II 100% production tested at +25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Table I. User Select Options
ORDERING GUIDE
S1 Package Options ST-48* Evaluation Board 0 0 1 1
S2 0 1 0 1
User Select Options Standby Both Channels A and B. Standby Channel B Only. Normal Operation (Data Align Disabled). Data align enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed a 1/2 clock cycle).
Model AD9288BST -40, -80, -100 AD9288/PCB
Temperature Ranges -40C to +85C +25C
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 x 7 mm: LQFP).
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9288 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9288
PIN CONFIGURATION
D7A (MSB)
Aperture Delay
The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled.
D6A D5A D4A D3A D2A D1A D0A
ENCA VDD
GND
VD
Aperture Uncertainty (Jitter)
48 47 46 45 44 43 42 41 40 39 38 37
The sample-to-sample variation in aperture delay.
36 NC 35 NC 34 GND 33 VDD 32 GND
GND 1 AINA 2 AINA 3 DFS 4 REFINA 5 REFOUT 6 REFINB 7 S1 8 S2 9 AINB 10 AINB 11 GND 12
Differential Nonlinearity
PIN 1 IDENTIFIER
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
AD9288
TOP VIEW (Not to Scale)
31 VD 30 VD 29 GND 28 VDD 27 GND 26 NC 25 NC
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Integral Nonlinearity
ENCB VDD
GND
VD
D3B D2B
D1B
(MSB) D7B D6B
D5B D4B
D0B
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
PIN FUNCTION DESCRIPTIONS
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
Pin No.
Name
Description Ground. Analog Input for Channel A. Analog Input for Channel A (Complementary). Data Format Select: (Offset binary output available if set low. Twos complement output available if set high). Reference Voltage Input for Channel A. Internal Reference Voltage. Reference Voltage Input for Channel B. User Select #1 (Refer to Table I), Tied with Respect to VD. User Select #2 (Refer to Table I), Tied with Respect to VD. Analog Input for Channel B (Complementary). Analog Input for Channel B. Analog Supply (3 V). Clock Input for Channel B. Digital Supply (3 V). Digital Output for Channel B. Do Not Connect. Digital Output for Channel A. Clock Input for Channel A.
1, 12, 16, 27, 29, 32, 34, 45 GND 2 AINA 3 AINA 4 DFS
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
5 6 7 8 9 10 11 13, 30, 31, 48 14 15, 28, 33, 46 17-24 25, 26, 35, 36 37-44 47
REFINA REFOUT REFINB S1 S2 AINB AINB VD ENCB VDD D7B-D0B NC D0A-D7A ENCA
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal)
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Worst Harmonic
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. -4-
The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc. REV. 0
AD9288
SAMPLE N SAMPLE N+1 SAMPLE N+5
A IN A, A IN B
tA tEH tEL
1/ f
S
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A, B
tPD
tV
D7A-D0A
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
D7B-D0B
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE N
SAMPLE N+1
SAMPLE N+5
AINA, AINB
tA tEH tEL
1/ fS
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A ENCODE B
tPD
tV
D7A-D0A
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
D7B-D0B
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
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AD9288
SAMPLE N SAMPLE N+1 SAMPLE N+5
AINA, AINB
tA tEH tEL
1/ fS
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A ENCODE B
tPD
tV
D7A-D0A
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
D7B-D0B
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
DATA N+1
Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
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Typical Performance Characteristics-AD9288
0 -10 -20 -30
60.00 72.00
ENCODE = 100MSPS AIN = 10.3MHz SNR = 48.52dB SINAD = 48.08dB 2ND HARMONIC = -62.54dBc 3RD HARMONIC = -63.56dBc
ENCODE RATE = 100MSPS 68.00 64.00 2ND
-40
dB
dB -50
56.00 52.00 3RD
-60 -70 -80 -90 SAMPLE
48.00 44.00 40.00 0 10 20 30 40 MHz 50 60 70 80 90
Figure 4. Spectrum: fS = 100 MSPS, fIN = 10 MHz, Single-Ended Input
Figure 7. Harmonic Distortion vs. AIN Frequency
0 -10 -20 -30 -40
dB
0
ENCODE = 100MSPS AIN = 41MHz SNR = 47.87dB SINAD = 46.27dB 2ND HARMONIC = -54.10dBc 3RD HARMONIC = -55.46dBc
-10 -20 -30 -40
ENCODE = 100MSPS AIN1 = 9.3MHz AIN2 = 10.3MHz IMD = -60.0dBc
dB
-50 -60 -70 -80 -90 SAMPLE
-50 -60 -70 -80 -90 SAMPLE
Figure 5. Spectrum: fS = 100 MSPS, fIN = 41 MHz, Single-Ended Input
Figure 8. Two-Tone Intermodulation Distortion
0 -10 -20 -30 -40
dB
50.00
ENCODE = 100MSPS AIN = 76MHz SNR = 47.1dB SINAD = 43.2dB 2ND HARMONIC = -52.2dBc 3RD HARMONIC = -51.5dBc
ENCODE RATE = 100MSPS 48.00 SNR 46.00 SINAD 44.00 dB 42.00
-50 -60
40.00
-70 -80 -90 SAMPLE
38.00 36.00 0 10 20 30 40 MHz 50 60 70 80 90
Figure 6. Spectrum: fS = 100 MSPS, fIN = 76 MHz, Single-Ended Input
Figure 9. SINAD/SNR vs. AIN Frequency
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AD9288
49.00 AIN = 10.3MHz SINAD 48.00 175
POWER - mW
190 SNR 185 180 AIN = 10.3MHz
170 165 160 155
dB
47.00
46.00 150 145 45.00 30 40 50 60 70 MSPS 80 90 100 110 140 0 10 20 30 40 50 MSPS 60 70 80 90 100
Figure 10. SINAD/SNR vs. Encode Rate
Figure 13. Analog Power Dissipation vs. Encode Rate
50.00 SNR AIN = 10.3MHz
48.0 47.5 ENCODE RATE = 100MSPS AIN = 10.3MHz
46.00
SINAD
47.0 46.5
SNR SINAD
42.00
46.0
dB
dB
45.5 38.00 45.0 34.00 44.5 44.0 30.00 7.0 6.5 6.0 5.5 5.0 4.5 4.0 ENCODE HIGH PULSEWIDTH - ns 3.5 3.0 43.5
-40
25 TEMPERATURE - C
85
Figure 11. SINAD/SNR vs. Encode Pulsewidth High
Figure 14. SINAD/SNR vs. Temperature
0.5 0.0 -0.5 -1.0 -1.5
ENCODE RATE = 100MSPS
0.6 0.4 0.2 0 ENCODE RATE = 100MSPS AIN = 10.3MHz
-2.5 -3.0 -3.5 -4.0 -4.5
% GAIN
-2.0 dB
-3dB
-0.2 -0.4 -0.6 -0.8
-5.0 -5.5 0 100 200 300 400 BANDWIDTH - MHz 500 600 -1.0 -40 25 TEMPERATURE - C 85
Figure 12. ADC Frequency Response: fS = 100 MSPS
Figure 15. ADC Gain vs. Temperature (with External +1.25 V Reference)
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2.0 1.5 1.0 0.5
LSB
VD 28k AIN 12k 28k AIN 12k
0.0 -0.5 -1.0 -1.5 -2.0
Figure 19. Equivalent Analog Input Circuit
VD
VBIAS
CODE
REFIN
Figure 16. Integral Nonlinearity Figure 20. Equivalent Reference Input Circuit
1.00 0.75 0.50 0.25
LSB
VD
ENCODE
0.00
Figure 21. Equivalent Encode Input Circuit
-0.25 -0.50
VDD
-0.75 -1.00 CODE
OUT
Figure 17. Differential Nonlinearity Figure 22. Equivalent Digital Output Circuit
1.3 ENCODE = 100MSPS VD = 3.0V TA = +25 C
VD
1.2
1.1
VREFOUT - V
OUT
1.0
0.9
0.8
Figure 23. Equivalent Reference Output Circuit
0.7
0
0.25
0.5
0.75 1 LOAD - mA
1.25
1.5
1.75
Figure 18. Voltage Reference Out vs. Current Load
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AD9288
APPLICATION NOTES
THEORY OF OPERATION Timing
The AD9288 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of comparator accuracy. The input buffers are differential and both sets of inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels.
USING THE AD9288
The AD9288 provides latched data outputs, with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figures 1, 2 and 3). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9288. These transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD9288 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance will degrade. Typical power-up recovery time after standby mode is 15 clock cycles.
User Select Options
Good high speed design practices must be followed when using the AD9288. To obtain maximum benefit, decoupling capacitors should be physically as close to the chip as possible, minimizing trace and via inductance between chip pins and capacitor (0603 surface mount caps are used on the AD9288/PCB evaluation board). It is recommended to place a 0.1 F capacitor at each power-ground pin pair for high frequency decoupling, and include one 10 F capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 F capacitor. It is also recommended to use a split power plane and contiguous ground plane (see evaluation board section). Data output traces should be short (<1 inch), minimizing on-chip noise at switching.
ENCODE Input
Two pins are available for a combination of operational modes. These options allow the user to place both channels in standby, excluding the reference, or just the B channel. Both modes place the output buffers and clock inputs in high impedance states. The other option allows the user to skew the B channel output data by 1/2 a clock cycle. In other words, if two clocks are fed to the AD9288 and are 180 out of phase, enabling the data align will allow Channel B output data to be available at the rising edge of Clock A. If the same encode clock is provided to both channels and the data align pin is enabled, then output data from Channel B will be 180 out of phase with respect to Channel A. If the same encode clock is provided to both channels and the data align pin is disabled, then both outputs are delivered on the same rising edge of the clock.
EVALUATION BOARD
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer. Any noise, distortion or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9288, and the user is advised to give commensurate thought to the clock source. The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
The AD9288 evaluation board offers an easy way to test the AD9288. It provides a means to drive the analog inputs singleendedly or differentially. The two encode clocks are easily accessible at on-board SMB connectors J2, J7. These clocks are buffered on the board to provide the clocks for an on-board DAC and latches. The digital outputs and output clocks are available at a standard 37-pin connector, P2. The board has several different modes of operation, and is shipped in the following configuration: * Single-Ended Analog Input * Normal Operation Timing Mode * Internal Voltage Reference
Power Connector
The digital outputs are TTL/CMOS compatible for lower power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option supports either twos complement (set high) or offset binary output (set low) formats.
Analog Input
Power is supplied to the board via a detachable 6-pin power strip, P1. VREFA VREFB VDL VDD VD - - - - - Optional External Reference Input (1.25 V/1 A) Optional External Reference Input (1.25 V/1 A) Supply for Support Logic and DAC (3 V/215 mA) Supply for ADC Outputs (3 V/15 mA) Supply for ADC Analog (3 V/30 mA)
The analog input to the AD9288 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input stage of the AD9288 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.024 V p-p centered at VD x 0.3.
Voltage Reference
Analog Inputs
A stable and accurate 1.25 V voltage reference is built into the AD9288 (REFOUT). In normal operation, the internal reference is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6 (REFOUT). The input range can be adjusted by varying the reference voltage applied to the AD9288. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage, which changes linearly.
The evaluation board accepts a 1 V analog input signal centered at ground at each analog input. These can be single-ended signals using SMB connectors J5 (channel A) and J1 (Channel B). In this mode use jumpers E4-E5 and E6-E7. (E1-E2 and E9- E10 jumpers should be lifted.) Differential analog inputs use SMB connectors J4 and J6. Input is 1 V centered at ground. The single-ended input is converted
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AD9288
to differential by transformers T1, T2--allowing the ADC performance for differential inputs to be measured using a singleended source. In this mode use jumpers E1-E2, E3-E4, E7-E8 and E9-E10. (E4-E5 and E6-E7 jumpers should be lifted.) Each analog input is terminated on the board with 50 to ground. Each input is ac-coupled on the board through a 0.1 F capacitor to an on-chip resistor divider that provides dc bias. Note that the inverting analog inputs are terminated on the board with 25 (optimized for single-ended operation). When driving the board differentially these resistors can be changed to 50 to provide balanced inputs.
Encode
1
PIN 22 (DATA)
PIN 2 (CLOCK)
Ch1
2.00V
CH2
2.00V
M 10.0ns CH4
40mV
Figure 24. Data Output and Clock at 37-Pin Connector
DAC Outputs
The encode clock for channel A uses SMB connector J7. Channel B encode is at SMB connector J2. Each clock input is terminated on the board with 50 to ground. The input clocks are fed directly to the ADC and to buffers U5, U6 which drive the DAC and latches. The clock inputs are TTL compatible, but should be limited to a maximum of VD.
Voltage Reference
The AD9288 has an internal 1.25 V voltage reference. An external reference for each channel may be employed instead. The evaluation board is configured for the internal reference (use jumpers E18-E41 and E17-E19. To use external references, connect to VREFA and VREFB pins on the power connector P1 and use jumpers E20-E18 and E21-E19.
Normal Operation Mode
Each channel is reconstructed by an on-board dual channel DAC, an AD9763. This DAC is intended to assist in debug--it should not be used to measure the performance of the ADC. It is a current output DAC with on-board 50 termination resistors. Figure 25 is representative of the DAC output with a fullscale analog input. The scope setting was low bandwidth, 50 termination.
1
In this mode both converters are clocked by the same encode clock; latency is four clock cycles (see timing diagram). Signal S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is set at jumpers E22-E29 and E26-E23.
Data Align Mode
Ch1 500mV
BW
M 50.0ns CH1
380mV
In this mode channel B output is delayed an additional 1/2 cycle. Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This is set at jumpers E22-E29 and E26-E28.
Data Format Select
Figure 25. AD9763 Reconstruction DAC Output
Troubleshooting
Data Format Select sets the output data format that the ADC outputs. Setting DFS (Pin 4) low at E30-E27 sets the output format to be offset binary; setting DFS high at E30-E25 sets the output to be twos complement.
Data Outputs
The ADC digital outputs are latched on the board by two 574s, the latch outputs are available at the 37-pin connector at Pins 22-29 (Channel A) and Pins 30-37 (Channel B). A latch output clock (data ready) is available at Pin 2 or 21 on the output connector. The data ready signal can be aligned with clock A input by connecting E31-E32 or aligned with clock B input by connecting E31-E33.
If the board does not seem to be working correctly, try the following: * Verify power at IC pins. * Check that all jumpers are in the correct position for the desired mode of operation. * Verify VREF is at 1.25 V * Try running encode clock and analog inputs at low speeds (10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs, and ADC outputs for toggling. The AD9288 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
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AD9288
BILL OF MATERIALS
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QTY 22 5 43 8 1 1 10 2 2 2 2 1 1 2 2
REFDES C1-C15, C20-C25, C27 C16-C19, C26 E1-E43 J1-J8 P1 P2 R1, R3, R5-R7, R10-R14 R2, R4 R8, R9 R15, R16 T1, T2 U1 U2 U3, U4 U5, U6
DEVICE Ceramic Cap Tantalum Cap W-HOLE SMBPN TB6 37DRFP Resistor Resistor Resistor Resistor Transformer AD9288 AD9763 74ACQ574 SN74LCX86
PACKAGE 0603 TAJD W-HOLE SMBP TB6 C37DRFP R1206 R1206 R1206 R1206 T1-1T LQFP48 LQFP48 DIP20\SOL SO14
VALUE 0.1 F 10 F
50 25 2 k 0
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REV. 0
GND
GND GND
2k 50
J3 DAC OUTPUT A GND R12 50 GND GND GND
DAC OUTPUT B J8 GND R14 50 GND VDL C20 0.1 F GND
50 GND 2k GND C21 0.1 F
48 47 46 45 44 43 42 41 40 39 38 37
A1 B1
R13 R9
VDL
B2
R8 R10
MODE AVDD
REFIO
A2 ACOM
FSADJ1
D7B D6B D5B
1 DB9-P1
2 DB8-P1 3 DB7-P1 4 DB6-P1 5 DB5-P1 6 DB4-P1
REFIO FSADJ2
SLEEP
NC2
NC3 DCOM1 DVDD1
WRT1/IQWRT
CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL DCOM2
J7 GND CLKLATA VDL GND VDL VDL C23 0.1 F D7 D6 GND D5 D4 U3 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 D0 GND
44 43 42 41 40 39 38 37
1 VDL
13 14 15 16 17 18 19 20 21 22 23 24
DVDD2
DB9-P2 DB8-P2
VDL E37 CLKDACA GND Q1 Q2 Q3 Q4 D0 Q0 C22 0.1 F GND OUT_EN VCC
GND GND GND
CLKDACA CLKDACA
CLKDACB
GND
GND
7
CLKDACB GND
VD
VDD
GND C7 0.1 F
AINA SINGLE-ENDED
48 47 46 45
E5
D9A D8A D7A D6A D5A D4A D3A VD3 VDD3 GND D2A
E4 GND C9 0.1 F
2 3
C10 0.1 F
ENCA
J5
C8 GND 0.1 F
GND C27 0.1 F
AINA AINAB 2COMP REFINA REFOUT REFINB
GND C24 0.1 F
GND
1
GND1
ENCA
VD
ENCB
VDD
GND3
D9B
D8B
D7B
D6B
D5B
D4B
D3B
E8
R3 50
13
14
15
16
17
18
19
20
21 22
23
24
D2B
ENCB
GND
GND C5 0.1 F
C6 0.1 F
VD
GND
VDD
REV. 0
P1
NC7 36 NC6 35 NC5 34 NC4 33 DB0-P2 32
1
2
3
4
5
6
D4B D3B D2B D1B
7 DB3-P1
GND
VD
VDD
VDL
VREFA VREFB
AD9763 U2
DB1-P2 31 DB2-P2 30 DB3-P2 29 DB4-P2 28 DB5-P2 27 DB6-P2 26 DB7-P2 25
GND GND D0A D1A D2A D3A VD VDD VDL D4A D5A C16 10 F C17 10 F VREFA VREFB
D0B
8 DB2-P1 9 DB1-P1 10 DB0-P1 11 NC 12 NC1
ENCA GND C25 0.1 F
GND GND
ENCODE A
R16 00
74LCX86
C18 10 F
C19 10 F
C26 10 F GND
R11 50 D6A D7A GND 74ACQ574 C14 0.1 F VDL D7A D6A D5A D4A D3A D2A D1A GND E39 E38
GND
2
3
GND GND
E35
E36
4 5
E34
CLKCONA
6
14 VCC 1A 13 4B 1B 12 4A 1Y U6 4Y 11 2A 10 3B 2B 9 3A 2Y 8 3Y GND
GND
1 2 3 4 5 6 7 D0A LSB CLKLATA CLKCONA 8 9 10 E32 11 E31 E33 12
D1 D2 D3 D4 D5 D6 D7 GND
GND
GND
R1 50
Q5 Q6 Q7 CLOCK
Figure 26 . Dual Evaluation Board Schematic
GND
D1A 36
D0A 35 GND7 34 VDD2 33 GND6 32 VD2 31 VD1 30
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VD E41 E27 VREFA GND
6 7 8 9 4 5
GND
E3
GND
GND
13 14 GND VDD GND GND C4 GND 0.1 F C3 0.1 F CLKCONB 15 16 17 18 VD VD
GND5 29 VDD1 28
GND4 27 D0B 26
R5 50 E25 E20 E17 VREFB E24 VD E29
S2
10 AINBB
R2 25 E30
J4
AINA DIFFERENTIAL GND GND E21 E19
S1
T1-1T 1 6 E2 2 E1 4 T2 3
E18
AD9288 U1
19 GND GND GND GND C1 0.1 F GND
D1B 25
GND E23 E22 VD E28
11 AINB
GND E26
C2 0.1 F
20 21 VDD 22 23 24 GND GND 74ACQ574 GND 1 2 3 OUT_EN D0 VCC Q0 Q1 Q2 U4 Q3 Q4 Q5 7 D5 8 D6 GND 9 D7 10 GND 20 19 18 17 16 15 14 C15 0.1 F VDL D0B D1B D2B D3B D4B D5B D6B D7B MSB E43 E40 E42 CLKLATB C37DRPF P2 13 Q6 12 Q7 11 CLOCK 25 26 27 28 29 30 31 32 33 34 35 36 37 D1 4 D2 5 D3 6 D4
R6 50 C12 0.1 F GND
12 GND2
J6
E9
4
T1
AINB DIFFERENTIAL
E10
6 T1-1T
3 2 1
GND
R4 25
GND
GND
GND
E6
E7
J1
C11 0.1 F
AINB SINGLE-ENDED
ENCB GND C13 0.1 F VDL GND CLKLATB
ENCODE B
R15 00
74LCX86
J2
1
1A
R7 50 E15 E12 CLKDACB GND E11
GND
2
3
GND GND
4
VDL
E13
E16
5
CLKLATA VDL
AD9288
E14
CLKCONB
6
GND
GND
7
14 VCC 13 4B 1B 12 4A 1Y U5 4Y 11 2A 10 3B 2B 9 3A 2Y 8 3Y GND
AD9288
Figure 27. Printed Circuit Board Top Side Copper
Figure 29. Printed Circuit Board Ground Layer
Figure 28. Printed Circuit Board Bottom Side Silkscreen
Figure 30. Printed Circuit Board "Split" Power Layer
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REV. 0
AD9288
Figure 31. Printed Circuit Board Bottom Side Copper
Figure 32. Printed Circuit Board Top Side Silkscreen
REV. 0
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AD9288
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
48 1
0.354 (9.00) BSC 0.276 (7.0) BSC
37 36
SEATING PLANE TOP VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05) 0 - 7
0 MIN 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
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REV. 0
PRINTED IN U.S.A.
C3546-8-4/99

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