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Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Features
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Description
The T7507 device is a single-chip, four-channel A-law PCM codec with filters. This integrated circuit provides analog-to-digital and digital-to-analog conversion. It provides the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. This device is packaged in a 44-pin PLCC. This codec is intended for use with Lucent Technologies Microelectronics Group's L8567 SLIC. When used with that SLIC, the line tip/ring pair is terminated in the network required for central office applications in the People's Republic of China (PRC). Proper hybrid balance and transmit and receive gains are also obtained. This device uses a serial data control scheme to interface with the controlling processor. This device has a latched parallel data control scheme to provide control bits to, and receive status bits from, the SLIC and switch. This interface is designed to be compatible with the Lucent L8567 SLIC and L7583 solidstate switch.
5 V only Low-power, latch-up-free CMOS technology: -- 37 mW/channel typical operating power dissipation -- 1 mW/channel typical powerdown dissipation Fixed master clock frequency: 2.048 MHz On-chip sample and hold, autozero, and precision voltage reference Differential architecture for high noise immunity and power supply rejection PCM interface: -- Fixed 2.048 MHz data rate -- Delayed and nondelayed PCM modes -- Fully flexible time-slot assignment -- Transmit and receive aligned or offset Transmit PCM data output enable Serial control interface with controlling processor Latched parallel control interface with SLIC and switch Meets or exceeds D3/D4 (as per Lucent PUB 43801) and ITU-T G.711--G.714 requirements Operating temperature range: -40 C to +85 C A-law companding Hybrid balance and termination impedance: -- 200 in series with 680 || 0.1 F (People's Republic of China ZT) -- Matched with L8567 SLIC Programmable receive gain (-3.5 dB or -7 dB), fixed transmit gain (0 dB) when matched with L8567 SLIC 44-pin PLCC
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Table of Contents
Contents Page Figures Page
Features ......................................................................1 Description...................................................................1 Pin Information ............................................................5 Functional Description .................................................7 PCM Interface ........................................................7 Analog Interface .....................................................8 Transmission Levels...............................................8 Microprocessor Serial Data Control and L8567 SLIC/L7583 Switch (or EMR) Control Interfaces .............................................................8 Enable Transfers when CCLK Is Bursted with CSEL ...........................................................9 Enable Transfers when CCLK Is Not Restricted to CSEL Low.......................................9 Input Word Definition............................................12 Output Word Definition .........................................14 Powerup ...............................................................14 T7507 ..............................................................14 Output Word....................................................14 EN Status ........................................................14 Input Word--PCM Interface ............................14 Input Word--Relay Control/Timing .................14 Input Word--Control Mode .............................14 State Definitions ...................................................14 Powerup ..........................................................14 Standby ...........................................................14 Full-Chip Powerdown ......................................14 Absolute Maximum Ratings.......................................15 Handling Precautions ................................................15 Electrical Characteristics ...........................................15 dc Characteristics.................................................15 Transmission Characteristics ....................................16 ac Transmission Characteristics ..........................17 Overload Compression ...................................18 Chip Set Performance Specifications ........................21 Gain......................................................................21 Gain Flatness--In Band .......................................21 Gain Flatness--Out of Band--High Frequencies .......................................................21 Gain Flatness--Out of Band--Low Frequencies .......................................................22 Loss vs. Level Relative to Loss at -10 dBm Input at 1020 Hz ................................................22 Return Loss ..........................................................22 Hybrid Balance .....................................................22 Microprocessor Interface ...........................................23 Timing Characteristics ...............................................25 Applications ...............................................................28 Outline Diagram.........................................................29 44-Pin PLCC ........................................................29 Ordering Information..................................................30 2
Figure 1. Block Diagram ............................................ 4 Figure 2. Pin Diagram................................................. 5 Figure 3. Typical Analog Input Section ...................... 8 Figure 4. Overload Compression ............................. 18 Figure 5. Termination Impedance ............................ 21 Figure 6. Transmit and Receive Direction Frequency-Dependent Loss Relative to Gain at 3400 Hz ................................... 21 Figure 7. Loss vs. Level ........................................... 22 Figure 8. Return Loss .............................................. 22 Figure 9. Hybrid Balance ......................................... 22 Figure 10. SLIC/Switch Interface Timing ................. 24 Figure 11. Microprocessor Interface Write Timing .................................................... 24 Figure 12. T7507 Transmit and Receive Timing, FSEP = 1 MCLK or IFS = 1, Delayed Timing (D0 = 0) ...................................... 26 Figure 13. T7507 Transmit and Receive Timing, FSEP = 1 MCLK or IFS = 1, Nondelayed Timing (D0 = 1) ...................................... 26 Figure 14. T7507 Receive Timing, FSEP > 1 MCLK and IFS = 0, Delayed Timing (D3 = 0) .................................................. 27 Figure 15. Typical Frame Sync Timing (IFS = 0) ..... 27 Figure 16. Basic Loop Start Application Using the T7507 and the L7583 Switch for 200 + (680 || 100 nF) Complex Termination and Hybrid Balance ............ 28
Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Table of Contents (continued)
Tables Page
Table 1. Pin Descriptions ........................................................................................................................................5 Table 2. Microprocessor Interface Descriptions ....................................................................................................11 Table 3. C0, C1 Channel Select .............................................................................................................................12 Table 4. M, D4, D3, D2, D1, D0 Mode Select and Data .........................................................................................12 Table 5. M = 0 Mode (PCM Time-Slot Assignment) ...............................................................................................12 Table 6. M = 1, D4 = 0 Mode (Relay State Control and Delayed/Nondelayed Timing) .........................................13 Table 7. M = 1, D4 = 1 Mode (Codec State Control and SLIC State Control) .......................................................13 Table 8. Digital Interface .......................................................................................................................................15 Table 9. Power Dissipation ....................................................................................................................................16 Table 10. Analog Interface ....................................................................................................................................16 Table 11. Absolute Gain ........................................................................................................................................17 Table 12. Gain Tracking .........................................................................................................................................17 Table 13. Distortion ................................................................................................................................................17 Table 14. Envelope Delay Distortion .....................................................................................................................18 Table 15. Decoder Limits Relative to Gain at 1020 Hz ...........................................................................................19 Table 16. Encoder Limits, Includes Effect of Termination Impedance Filter Relative to Gain at 1020 Hz ..............19 Table 17. Termination Impedance Limits Relative to Gain at 1020 Hz ...................................................................19 Table 18. Hybrid Path Limits Relative to Gain at 1020 Hz ......................................................................................19 Table 19. Noise .....................................................................................................................................................20 Table 20. Interchannel Crosstalk (Between Channels) .........................................................................................20 Table 21. Gain ........................................................................................................................................................21 Table 22. Gain Flatness--In Band .........................................................................................................................21 Table 23. Gain Flatness--Out of Band--Low Frequencies ..................................................................................22 Table 24. T7507 Microprocessor Interface Timing .................................................................................................23 Table 25. Clock Section ..........................................................................................................................................25 Table 26. T7507 Transmit Section (Delayed Timing)..............................................................................................25 Table 27. T7507 Transmit Section (Nondelayed Timing)........................................................................................25 Table 28. T7507 Receive Section ..........................................................................................................................25
Lucent Technologies Inc.
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Description (continued)
VFXIN0
+ - ZT HYBAL
BANDPASS FILTER NETWORK
ENCODER
PCM INTERFACE
DX DR FSEP IFS DXEN GNDD
CHANNEL 0 LOW-PASS FILTER NETWORK
VFRON0 VFROP0
DECODER
POWERDOWN CONTROL MCLK CSEL CCLK DI DO
VFXIN1 VFRON1 VFROP1 VFXIN2 VFRON2 VFROP2 VFXIN3 VFRON3 VFROP3 EN0C EN1C EN2C EN3C RD1C RD2C RD3C B0C B1C NSTATC NTSDC NTSD0 NTSD1 NTSD2 NTSD3
INTERNAL TIMING & CONTROL CHANNEL 1
CHANNEL 2 BIAS CIRCUITRY & REFERENCE VDD (2) GNDA (4)
CHANNEL 3
SLIC & SWITCH CONTROL INTERFACE
5-3579.a(F)
Figure 1. Block Diagram
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Pin Information
GNDD MCLK CCLK FSEP
CSEL
DXEN
IFS
6 NTSDC NSTATC B1C B0C RD3C RD2C RD1C VDD VFXIN2 AGND2 VFRON2 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NTSD0 NTSD1 NTSD3 NTSD2 EN0C EN1C EN3C EN2C VDD VFXIN0 AGND0
T7507
18 19 20 21 22 23 24 25 26 27 28 VFRON3 VFRON1 VFRON0 VFROP2 VFROP3 VFROP1 VFROP0 VFXIN3 AGND3 AGND1 VFXIN1
DO
DR
DX
DI
5-5347a(F)
Figure 2. Pin Diagram Table 1. Pin Descriptions Pin 1 Symbol FSEP Type I
d
Name/Function Frame Sync Separation. The pulse width of this 8 kHz signal defines the timing offset between the transmit and receive frames. If the IFS pin is 0, internally generated receive frame sync pulses are delayed from the corresponding transmit frame sync pulse rising edge by one less than the FSEP pulse width in negative MCLK edges. If the pulse width is one MCLK period or less or if IFS is high, the transmit and receive frame syncs are made coincident. Loss of FSEP causes the device to power down. A delay of 255 clock pulses is not allowed. Timing relationships between FSEP and time slot 0 are given in Figures 12--14. This input is also the frame sync for all the codec filters and PCM interface timing generated from MCLK. An internal pull-down is on FSEP. Digital Ground. Ground connection for the digital circuitry. All ground pins must be connected on the circuit board. Transmit PCM Data Output. This pin remains in the high-impedance state except during active transmit time slots. An active transmit time slot is defined by programming, FSEP , and the state of IFS. Data is shifted out on the rising edge of MCLK. Receive PCM Data Input. The data on this pin is shifted into the device on the falling edges of MCLK. Data is only entered for valid time slots as defined by the relationship of the time-slot programming pulse on the FSEP input, and the state of IFS. Master Clock Input. The frequency must be 2.048 MHz. This clock serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is required. Transmit PCM Data Output Flag. An open-drain output that pulses low during the period when the DX output is enabled.
2 3
GNDD DX
-- O
4
DR
I
5 6
MCLK
DxEN
I O
Lucent Technologies Inc.
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 7 Symbol NTSDC Type I Name/Function Not Thermal Shutdown Status Input--L8567 SLIC. Logic level status input from L8567 SLIC indicating if SLIC is in thermal shutdown or normal device operation. This input is accepted from the latched parallel data output of the SLIC and outputted on the serial data output bus DO to the microcontroller. This pin is meant to be a shared output among the four channels associated with the quad T7507, using the EN control to determine valid data among the four channels. Not Loop Closure/Not Ring Trip Status Input. Logic level status input from L8567 SLIC indicating loop on-/off-hook status. This input is accepted from the latched parallel data output of the SLIC and outputted on the serial data output bus DO to the microcontroller. This pin is meant to be a shared output among the four channels associated with the quad T7507, using the EN control to determine valid data among the four channels. SLIC State Control. These logic level outputs control the state of the L8567 SLIC. These pins are meant to be a shared output among the four channels associated with the quad T7507, using the EN control to determine valid data among the four channels. Driver Control. These logic level outputs control the state of an electromechanical relay driver on the L8567 SLIC or a solid-state relay contact on the L7583 via the L7583 logic control inputs. These pins are meant to be a shared output among the four channels associated with the quad T7507, using the EN control to determine valid data among the four channels. 5 V Analog Power Supplies. Both pins must be connected on the circuit board. Each pin should be bypassed to ground with at least 0.1 F of capacitance as close to the device as possible. Voice Frequency Transmitter Input. Analog inverting input to the noninverting operational amplifier at the transmit filter input. Connect the signal to be digitized to this pin through a capacitor CI (see Figure 3). Analog Grounds. All ground pins must be connected on the circuit board.
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NSTATC
I
9 10 11 12 13
B1c B0c RD3C RD2C RD1C
O
O
14 31 22 15 24 30 21 16 23 29 20 17 25 28 19 18 26 27 39 38 36 37
VDD
--
VFXIN3 VFXIN2 VFXIN1 VFXIN0 AGND3 AGND2 AGND1 AGND0 VFRON3 VFRON2 VFRON1 VFRON0 VFROP3 VFROP2 VFROP1 VFROP0 NTSD0 NTSD1 NTSD2 NTSD3
I
--
O
Voice Frequency Receiver Negative Output. This pin can drive 2000 (or greater) loads.
O
Voice Frequency Receive Positive Output. This pin can drive 2000 (or greater) loads.
I
Not Thermal Shutdown Status Input--L7583 Switch. Logic level status input from L7583 solid-state switch indicating if switch is in thermal shutdown or normal device operation. This input is accepted on a per-line basis from the four switches associated with the quad T7507, and outputted on the serial data output bus DO to the microcontroller. If unused, tie to ground or 5 V.
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 35 34 32 33 Symbol EN0C EN1C EN2C EN3C Type O Name/Function Enable. Per-line data enable control for L8567 SLIC and L7583 solid-state switch. Connect to EN pin of L8567 SLIC and LATCH input of L7583 switch on a per-line basis. When low, data latch on L8567 and L7583 inputs are transparent and data will flow through the latch. When low, data is valid on L8567 supervision outputs. When high, data input latches on L8567 and L7583 are latched and data on L8567 supervision outputs is not valid. These pulses are generated internally by the T7507 and are generated sequentially when CCLK is present. Data Output for Serial Microprocessor Interface. Data Input for Serial Microprocessor Interface. Control Clock for Serial Microprocessor Interface. This is the clock for the micro interface, SLIC, and switch parallel interface. This clock shifts serial information into the DI pin during valid write-read cycles (defined by detection of valid CSEL). This clock can be asynchronous to other system clocks. Note: Maximum clock frequency is 2.048 MHz. Chip Select for Serial Microprocessor Interface (Active-Low). Chip select for serial microprocessor interface. An internal pull-up is on CSEL. Inhibit Frame Separation. If this bit is set to 0, FSEP functions as defined. If this bit is set to 1, the width of FSEP has no effect on Dx and DR timing relationship. In this case, timing is as if FSEP = 1 MCLK. An internal pull-down is on IFS.
40 41 42
DO DI CCLK
O I I
43 44
CSEL
Iu Id
IFS
Functional Description
PCM Interface
Four channels of PCM data input and output are passed through two ports, DX and DR, so some type of time-slot assignment is necessary. The scheme used here is to utilize a timing mode of 32 time slots corresponding to a fixed master clock frequency of 2.048 MHz. Transmit to PCM data is output on pin DX, and receive from PCM data is input on pin DR. Timeslot assignment is done via the serial control data interface and is fully flexible. Any channel of any codec may be assigned to any of the 32 time slots. See Table 2 for additional details. Delayed or nondelayed timing is selectable via the serial control data interface. In the nondelayed mode, time slot 0 nominally begins on the rising edge of FSEP In the delayed mode, time slot 0 nominally starts . on the MCLK positive edge following the negative edge that detects FSEP The start of PCM data can be . delayed in 8 MCLK increments by programming the time-slot bits via the microprocessor interface. There is a single frame sync separation input pin, FSEP This input provides two functions: it provides a . clock for internal timing, and it sets the timing offset (if Lucent Technologies Inc.
any) between the transmit and receive frames for a given channel on the PCM highway. There must always be an 8 kHz signal on FSEP since this input provides , the 8 kHz clock required to maintain internal timing. By adjusting the duty cycle of FSEP, the offset between the transmit and receive frames for a given channel on the PCM highway is set. The number of negative clock edges minus one that occurs while FSEP is high is the delay (in clock periods) that is placed between the rising edge of a transmit frame sign bit and the falling edge used by the receiver to sample the sign bit. If FSEP is high for one clock period or less, the device makes the transmit edges and receive sampling edges one-half clock period apart. Alternately, the inhibit frame separation (IFS) pin can be used to force the one-half clock period state, regardless of the length of FSEP. If the IFS pin is tied low, FSEP functions as defined above in determining the PCM transmit/receive offset. If IFS is tied high, the width of FSEP has no effect on the DX/DR timing relationship; timing is as if FSEP = 1 MCLK. Regardless of how IFS is tied, an 8 kHz signal must still be applied to FSEP to maintain internal timing. Tying IFS high simply negates the effect of the duty cycle of FSEP on the DX/ DR timing relationship.
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Functional Description (continued)
PCM Interface (continued)
SLIC C1 0.07 F VFXIN
T7507
26 dB
The entire device is placed in a powerdown mode if FSEP remains low for 500 s. Powerdown is not guaranteed if MCLK is lost unless the device is already in the powerdown mode due to FSEP low for at least 500 s. The T7507 also offers an output pin, DxEN. This pin is an open-drain output that pulses low during the period when the DX output is enabled.
TO CODEC FILTERS
R 100 k
VCM = 2.4 V
5-4821(F)
Figure 3. Typical Analog Input Section
Analog Interface
The analog input section (Figure 3) includes an on-chip buffer op amp and internal gain. Feedback paths (ZT and HYBAL in Figure 1) are included in the T7507 to generate signals needed for termination impedance and hybrid balance. When matched with a SLIC with a transconductance from tip/ring of 39.75 V/A and a differential gain to tip/ring of 2 (such as the Lucent Technologies L8567), and when a solid-state switch (such as the Lucent L7583) and 50 of series protection are used, the T7507 will synthesize a complex line termination impedance and hybrid balance network of 200 + 680 || 100 nF. Additionally, the T7507 will fix the line circuit tip/ring to PCM transmit gain at 0 dB (at 1000 Hz, -0.7 dB, +0.3 dB) and will allow a user-selectable (via the serial control input) PCM to tip/ring receive gain of -3.5 dB or -7.0 dB (at 1000 Hz, -0.7 dB, +0.3 dB). Thus, the ac interface between the T7507 and the L8567 SLIC consists of a single dc blocking capacitor in the transmit direction, and a direct connection requiring no external components in the receive direction. The T7507/L8567/L7583 chip set is designed to meet all MPT requirements for the People's Republic of China.
Microprocessor Serial Data Control and L8567 SLIC/L7583 Switch (or EMR) Control Interfaces
The basic logic control scheme is a serial data interface between the microcontroller and the T7507. Through this interface, an 8-bit input control word and an 8-bit output status word is passed between the T7507 and microcontroller. The input control word contains information for the T7507, L8567 SLIC, and L7583 switch. The output status word contains off-hook and thermal shutdown status information from the L8567 SLIC and L7583 switch. See the Input Word Definition and Output Word Definition sections of this data sheet for specific details on the input and output words. Control and status information are passed between the T7507 and L8567 SLIC/L7583 switch via a latched parallel data interface. Data latches are integrated into the L8567 SLIC inputs and outputs and L7583 switch inputs. Thus, a given data I/O on the T7507 serves the corresponding data I/O on the L8567 SLIC for the four channels associated with the quad T7507. Additionally, a given data output on the T7507 serves the corresponding data inputs on the L7583 switch for the four channels associated with the quad T7507. Status information from the L7583 switch is passed to the T7507 on a per-line basis. The T7507 control interface consists of an 8-bit input serial shift register, an 8-bit output serial shift register, an 8-bit loop status input latch, logic to generate the enable (EN) pulses required to control the SLIC and switch data latches, interface logic/buffers between the DI shift register and the internal codec control, and interface logic buffers between the SLIC/switch output control leads.
Transmission Levels
Zero transmission-level points are specified relative to the digital milliwatt sequence prescribed by ITU-T recommendation G.711. Under these conditions, an analog input of 0.0452 Vrms applied to VFXIN produces a 0 dBm digital code, while a 0 dBm code input at DR produces an output of 0.394 Vrms differentially at VFRON/VFROP when using the -7.0 dB gain mode (data bit D4 = 0).
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Enable Transfers when CCLK Is Bursted with CSEL
When EN is low, status information from the SLIC and switch is updated in the T7507 8-bit loop status latch. This data will be transferred into the data out shift register and shifted out to the microcontroller on the next CSEL cycle. Thus, to make a write from the L8567 SLIC or L7583 switch, it takes two CSEL cycles: the first to create an EN pulse for a given channel and to shift updated status information to the 8-bit status latch, and the second CSEL cycle to shift the updated channel information to the microcontroller. Each time the CSEL goes low and status information is shifted to the microcontroller, only one of the four channels has new status data; the other channels are shifting out status data that has previously been presented to the microcontroller. Thus, it takes five CSEL cycles to a T7507 device to ensure that supervision data for each of the four channels associated with the T7507 device has been updated. When EN goes low, updated control information is also fed to the SLIC and switch from the T7507. Since EN for each channel is generated sequentially during successive CSEL, four CSELs to a given T7507 device are required to ensure that updated control information is given to each of the four channels. Note that to apply ringing, before the ring relay is activated to apply power ringing to the subscriber loop, the L8567 SLIC must first be changed from the low-power scan mode to the active mode. This is because the ring trip detector is not active when the L8567 SLIC is in the low-power scan mode. Thus, application of ringing to a given channel may require as many as eight CSEL cycles to the T7507 associated with the channel.
Functional Description (continued)
Microprocessor Serial Data Control and L8567 SLIC/L7583 Switch (or EMR) Control Interfaces (continued)
The serial data interface has pins for data in (DI), data out (DO), chip select (CSEL), and control clock (CCLK). Data is read by the microcontroller from the output shift register at the T7507 DO lead. The T7507 reads data from the microcontroller into the data input shift register at the DI lead. The loop status latch stores updated supervision information from the SLIC and switch until it is transferred to the DO shift register. On the falling edge of CSEL, the first bit of DO output data becomes valid and ready for transmission in the time specified by tCSLCCL. On the next falling CCLK edge, the microprocessor will read the first bit of valid data from the T7507 DO output. Also, on this first falling CCLK edge, the T7507 will read the first bit of control information on the DI input from the microcontroller. Thus, upon the falling CSEL edge, the microcontroller must have valid data ready at its data out lead in a time specified by tCIVCCL. On the next seven falling CCLK edges, the remaining seven status bits are read by the microcontroller at the T7507 DO lead and the remaining 7 control input bits are read by the T7507 at the DI lead from the microcontroller. During the time tCCLCSH, which is the period after the eight falling CCLK edges, the data at the DI register is applied to the T7507 codec and made available to the L8567 SLIC and L7583 switch input data latches. Data is applied only if CSEL is low and has remained low on the eighth negative edge of CCLK. Upon the falling edge of CSEL, DO data is passed from the loop status latch to the DO shift register. During the period when CSEL is low, DO status data will not be passed from the loop status latch to the DO shift register. Consecutive read/write periods are not allowed. CSEL must remain high for a specified time, tCSHCSL, before CSEL can transition low again. During CSEL low interval, the T7507 generates an EN pulse low for one of the four channels served by the particular T7507. These EN pulses are generated sequentially. Thus, if EN0 is generated on a given CSEL low, EN1 will be generated during the next CSEL low, etc. Only one of the four EN outputs associated with a given T7507 codec will be low during a given CSEL interval.
Enable Transfers when CCLK Is Not Restricted to CSEL Low
The T7507 will continue to generate EN pulses sequentially, free-running with CCLK falling edges, when CSEL is not applied low. Thus, if there are long periods of time when CSEL low is not presented to a given T7507 device, enable pulse low will be generated sequentially during this time. This feature allows for the most recent SLIC and switch status information to be maintained in the 8-bit loop status latch during long periods of time when CSEL to a given T7507 device is maintained high.
Lucent Technologies Inc.
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
ferred on a multiplexed basis through the B0c and B1c output leads on the T7507. L7583 control information (or L8567 relay driver information) is transferred on a multiplexed basis through the RD1c, RD2c, and RD3c output leads. Three features for the T7507 can be programmed via the serial data interface. The channel receive gain and codec powerup or powerdown are set on a per-channel basis. Delayed and nondelayed timing mode is set globally; all four channels are set to the same mode via the serial data bus. Additionally, PCM time-slot assignment is set via the serial data input bus. The L8567 B0, B1 state control inputs are latched data inputs. Control data is sent to these inputs via the B0c and B1c outputs of the T7507. The B0c and B1c outputs of the T7507 are meant to control the four SLICs associated with the quad T7507. Switch control information is sent to the INRING, INTESTin, or INTESTin logic control inputs of the L7583 switch, or to the RD1I, RD2I, and RD3I relay driver control inputs of the L8567 SLIC (if EMRS are used) via the RD1c, RD2c, and RD3c T7507 parallel data control outputs. Again, the L7583 state control inputs and the L8567 relay driver control inputs are latched, so control information from the RD1c, RD2c, and RD3c T7507 control outputs are meant to control four lines. The L8567 SLIC outputs loop status information via the latched NSTAT output. NSTAT is a wired-OR or the outputs of the L8567 SLIC's loop closure detector and ring trip detector. The loop status information is input to the T7507 via the NSTATc input. Since the L8567 SLIC NSTAT bit is latched, the SLIC output from the four channels associated with the T7507 are accepted at NSTATc. The L8567 SLIC also outputs a thermal shutdown flag via the latched NTSD output. This thermal shutdown information is input to the T7507 via the NTSDc input. Since the L8567 SLIC NSTAT and NTSD bits are latched, the SLIC output from the four channels associated with the T7507 are accepted at NSTATc and NTSD, respectively. The L7583 also outputs thermal shutdown status via the TSD output. The TSD output on the L7583 is not latched, so the TSD information is input to the T7507 for the four channels associated with the quad T7507 on a per-line basis via the NTSD0, NTSD1, NTSD2, and NTSD3 T7507 inputs. The multiplexed thermal shutdown information from the four L8567 SLICs and the per-line thermal shutdown information from the four L7583 switches are manipulated by the T7507 into a per-channel thermal shutdown bit and output on the serial data output DO pin. Lucent Technologies Inc.
Functional Description (continued)
Enable Transfers when CCLK Is Not Restricted to CSEL Low (continued)
If CSEL drops low, during the time an EN for a given channel is low, the write cycle to/from the codec will be aborted. However, the EN pulse that will be generated during the eight CCLK cycles that CSEL is low will be for the channel whose EN pulse was aborted by the CSEL dropping low. Thus, for example, if EN2 is low and during the time EN2 is low CSEL is also low, EN2 will immediately go high and any associated write is aborted. Then the EN that is generated because CSEL is low is for channel 2. The T7507 generates the required enable control signals for the L8567 input data latches, the output data latches, and the L7583 input data latch. A logic low on the L8567 or L7583 latch enable input allows data to flow through the latch. A logic high on the latch enable of the L8567 or L7583 latches the latch. The latch enable is output on a per-line basis from the EN0c, EN1c, EN2c, and EN3c outputs of the T7507. The L8567 SLIC and L7583 latches are level sensitive, so when ENx is low, the data from the SLIC and switch latch flows directly to the T7507 loop status latch. After a high-to-low CSEL transition, on the next falling edge of CCLK, data is transferred from the loop status latch to the serial shift register. Therefore, it is not desirable to update the loop status register on this CCLK edge. For this reason, EN pulses are generated during the rising edge of CCLK. Note that loop status information from the four channels is accepted on a multiplexed basis at the NSTATc input of the T7507. This information is decoded by the T7507 and placed at the appropriate bit in the 8-bit output word. NSTAT is a wired-OR of the loop closure and ring trip status from the L8567 SLIC. Thermal shutdown information from the four SLICs is accepted on a multiplexed basis at the NTSDc input of the T7507. Thermal shutdown information from the L7583 switch is accepted on a per-line basis from the four L7583s associated with the quad T7507. The thermal shutdown information from the SLICs is decoded by the T7507 and then ANDed with the thermal shutdown information from the corresponding L7583. This thermal shutdown information for the SLIC and switch is then placed at the appropriate bit in the 8-bit output word. The control word contains control information for the T7507, L8567 SLIC, and L7583 switch. Thus, the control bits for the L8567 SLIC and L7583 switch need to be transferred via the latched parallel control interface. SLIC control information for the four channels is trans10
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Functional Description (continued)
Enable Transfers when CCLK Is Not Restricted to CSEL Low (continued)
It is recommended that a polling process be used during idle periods to ensure that a loop closure detection is recognized by the microcontroller. The maximum nominal control clock (CCLK) frequency is 2.048 MHz. Also note that DO is 3-stated based on the state of CSEL. This allows multiple DO outputs from multiple T7507s to be tied to a common DO bus. Table 2. Microprocessor Interface Descriptions Symbol CCLK
CSEL
Description May be gapped; Maximum frequency is 2.048 MHz. EN pulses are generated on rising CCLK edges. A low-going CSEL initiates a write to the T7507 via the DI pin. At the same time, this initiates a read from the T7507 on the DO pin. Data is written and read on the first eight CCLK negative transitions after CSEL goes low. Data is applied to the T7507 operation only if CSEL is low on the eighth negative edge of CCLK. Consecutive writes are not allowed; CSEL must go high for a minimum 50 ns between write cycles. Additionally, data is shifted from the loop status latch to the serial shift register on the first falling CCLK pulse after CSEL goes low. Pin for serial input data. Input data is an 8-bit word which sends control information from the microcontroller to the T7507, L8567 SLIC, and L7583 switch. T7507 information is codec state information and PCM time-slot assignment. L8567 and L7583 control information is passed to these components via parallel control output pins. See Input Word Definition section for additional details. Pin for serial data output. Output data is an 8-bit word which sends status information from T7507 parallel status inputs to the microcontroller via the serial data interface. Status information is received from the T7507 via the parallel control inputs from the L8567 SLIC and L7583 switch. See Output Word Definition section for additional details.
DI
DO
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Functional Description (continued)
Input Word Definition
The control data input on DI is an 8-bit word of the format: C1 C0 M D4 D3 D2 D1 D0 Bits C0 and C1 are the channel select bits. Bit M is a mode control bit. Bits D0, D1, D2, and D3 are data bits. Bit D4 can be either a mode control bit or a data bit. If M is set to 0, the data word is set to the PCM time-slot assignment mode and bit D4 is a data bit. If M is set to 1, then D4 is also a mode set bit. If M, D4 = 1, 0, then the data word represents the relay/switch control delayed/nondelayed timing mode. If M, D4 = 1, 1 then the data word represents the codec/SLIC control mode. Table 3. C0, C1 Channel Select C1 0 0 1 1 C0 0 1 0 1 Channel 0 1 2 3
Table 4. M, D4, D3, D2, D1, D0 Mode Select and Data M 0 1 D4 Time-Slot Assignment 0 D3 Time-Slot Assignment Delayed/Nondelayed PCM Timing Mode or Reserved* T7507 Per Channel Powerup/Powerdown D2 Time-Slot Assignment Relay State Control Information 3 Channel Receive Gain D1 Time-Slot Assignment Relay State Control Information 2 B1 SLIC Control Bit D0 Time-Slot Assignment Relay State Control Information 1 B0 SLIC Control Bit
1
1
* Delayed/nondelayed PCM timing is a global parameter--all channels are programmed to the most recent value. To program PCM timing, use C0 = C1 = 0. (That is channel 0.) M = 1, D4 = 0. When programming C1, C0 = 01, M = 1, D4 = 0, then D3 must be programmed to 0. When C1, C0 = 10, 11, M = 1, D4 = 0, then D3 is ignored.
Table 5. M = 0 Mode (PCM Time-Slot Assignment) D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 1 Function Time Slot 0 Time Slot 1
. . .
1 1 1 1 1 Time Slot 31
Note: Do not assign two channels to the same time slot. If two channels are assigned to the same time slot, the result is indeterminate. It is recommended that time-slot assignment should only be done when the channel is powered down. If multiple chips are tied to the same DX bus, this can result in bus contention. Thus, reassignment of time slots should be done before the channel is powered up. For all codecs, upon powerup, channel 0 will be assigned to time slot 0, channel 1 will be assigned to time slot 1, channel 2 will be assigned to time slot 2, and channel 3 will be assigned to time slot 3.
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Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Functional Description (continued)
Input Word Definition (continued)
Table 6. M = 1, D4 = 0 Mode (Relay State Control and Delayed/Nondelayed Timing) D3 0 1 X D2 X X 0 D1 X X X D0 X X X Function Delayed timing mode (see Figure 12)*. With C0 = C1 = 00, bit D3 set PCM delayed or nondelayed timing. With C0, C1 = 01, 10, 11, bit D3 is ignored. Nondelayed timing mode (see Figure 13)*. With C0 = C1 = 00, bit D3 set PCM delayed or nondelayed timing. With C0, C1 = 01, 10, 11, bit D3 is ignored. T7507 driver output RD3c at logic low. If T7507 driver output RD3c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD3O, into the relay not active state. If T7507 output RD3c is used to drive the logic inputs of an L7583 solidstate switch, a logic 0 is applied. T7507 driver output RD3c at logic high. If T7507 driver output RD3c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD3O, into the relay active state. If T7507 output RD3c is used to drive the logic inputs of an L7583 solid-state switch, a logic 1 is applied. T7507 driver output RD2c at logic low. If T7507 driver output RD2c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD2O, into the relay not active state. If T7507 output RD2c is used to drive the logic inputs of an L7583 solidstate switch, a logic 0 is applied. T7507 driver output RD2c at logic high. If T7507 driver output RD2c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD2O, into the relay active state. If T7507 output RD2c is used to drive the logic inputs of an L7583 solid-state switch, a logic 1 is applied. T7507 driver output RD1c at logic low. If T7507 driver output RD1c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD1O, into the relay not active state. If T7507 output RD1c is used to drive the logic inputs of an L7583 solidstate switch, a logic 0 is applied. T7507 driver output RD1c at logic high. If T7507 driver output RD1c is applied to the L8567 SLIC RD3I input, this will place the relay driver output on the L8567, RD1O, into the relay active state. If T7507 output RD1c is used to drive the logic inputs of an L7583 solid-state switch, a logic 1 is applied.
X
1
X
X
X
X
0
X
X
X
1
X
X
X
X
0
X
X
X
1
* Delayed or nondelayed timing is a global parameter. All channels will use the most recently programmed value. Note: Upon powerup, D3 = D2 = D1 = D0 = 0; that is, delayed timing mode and all relay drivers in the not active state, or 0, 0, 0, are applied to L7583 solid-state relay, which is the idle/talk state.
Table 7. M = 1, D4 = 1 Mode (Codec State Control and SLIC State Control) D3 0 1 X X X X X X D2 X X 0 1 X X X X D1 X X X X 1 0 1 0 D0 X X X X 1 1 0 0 Function T7507 Channel Standby T7507 Channel Powerup Channel Receive Gain -3.5 dB* Channel Receive Gain -7.0 dB* L8567 SLIC Powerup, Forward Battery L8567 SLIC Powerup, Reverse Battery L8567 SLIC Low-Power Scan L8567 Disconnect
* Receive gain of -3.5 and -7.0 will be achieved in a 200 + 680 || 0.1 F termination, when using the T7507 with the L8567 SLIC, L7583 switch, and 50 protection resistors.
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Input Word--Relay Control/Timing Upon application of power, all relay driver control inputs are forced to logic 0. If the relay driver outputs are tied to the L8567 relay driver inputs, upon application of an EN signal, the relay drivers are forced into the off state. If applied to the L7583 control input, upon application of an EN pulse, the L7583B is forced into the idle/talk state. Input Word--Control Mode Upon application of power, the receive gain is -3.5 dB and with the B0/B1 control outputs set to 0/0. Note that B0/B1 = 0/0, the L8567 SLIC is set into the disconnect state upon application of EN pulse.
Functional Description (continued)
Output Word Definition
The status data input on D0 is an 8-bit word of the format: NSTAT-Ch0, NTSD-Ch0, NSTAT-Ch1, NTSD-Ch1, NSTAT-Ch2, NTSD-Ch2, NSTAT-Ch3, NTSD-Ch3 Where: NSTAT-Ch[0:3] is the wired-OR loop supervision status of the off-hook detector and ring trip detector from Channel [0:3]. NTSD-Ch[0:3] is the wire-ORed thermal shutdown status of the L8567 SLIC and L7583 for Channel [0:3].
State Definitions Powerup
This section defines the state of the T7507 when power is first applied to the device. T7507 Upon initial application of power, the T7507 is in the full-chip powerdown state and delayed timing mode. Output Word With the initial CSEL, after application of power, all eight bits of the output word are undefined. With subsequent CSEL, all eight bits of the output word will be set to zero. The output word will remain all 0s until application of EN pulses to update the output status information. An output word of all 0s implies that all four channels are in thermal shutdown state and are offhook. EN Status Upon application of power, all four EN channels will be at logic 1 (which means that no control data is transferred to, and no status information is received from, the SLIC or switch). All EN will remain at logic 1 until application of an initial FSEP pulse, at which time EN is created as defined in the Microprocessor Interface section of this data sheet. Input Word--PCM Interface Upon application of power, the PCM time-slot assignment defaults to the following time-slot assignment: CH0 Time Slot 0 CH1 Time Slot 1 CH2 Time Slot 2 Ch3 Time Slot 3 Standby This mode is programmed on a per-channel basis via the microprocessor control interface. In this mode, individual channels are powered down (not ready for transmission). All reference circuits are always powered up. EN pulses are generated free-running with CCLK. Analog outputs are held at a nominal 2.35 V. Full-Chip Powerdown This is a global parameter; that is, all channels are globally set into this mode. In this mode, all channels and all reference circuits are powered down. EN is forced to logic high. The T7507 is in this state upon application of power. The T7507 enters this state if FSEP is removed for four 8 kHz frames. The T7507 will remain in this state until reapplication of FSEP . Powerup All circuits are active. All channels are ready for transmission. EN pulses are generated free-running with CCLK.
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Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Maximum Power Dissipation (package limit) Symbol Tstg VDD -- PD Min -55 -- -0.5 -- Max 150 6.5 0.5 + VDD 600 Unit C V V mW
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Voltage Device Rating T7507 >2000 V
Electrical Characteristics
Specifications apply for TA = -40 C to +85 C, VDD = 5 V 5%, MCLK = 2.048 MHz, and GND = 0 V, unless otherwise noted.
dc Characteristics
Table 8. Digital Interface Parameter Input Low Voltage Input High Voltage Input Current Input Current, Pins with Pull-up (CSEL) Input Current, Pins with Pull-down (FSEP, IFS) Output Low Voltage Output High Voltage Output Current in High-impedance State Input Capacitance Symbol VIL VIH II II II VOL VOH IOZ CI Test Conditions All digital inputs All digital inputs Any digital input GND < VIN < VDD Any digital input GND < VIN < VDD Any digital input GND < VIN < VDD
DxEN, DX = 3.2 mA
Min -- 2.0 -10 2 -2 -- 2.4 3.5 -30 --
Typ -- -- -- -- -- -- -- -- -- --
Max 0.8 -- 10 150 -150 0.4 -- -- 30 5
Unit V V A A A V V V A pF
DX = -3.2 mA DX = -320 A
DxEN, DX
--
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Electrical Characteristics (continued)
dc Characteristics (continued)
Table 9. Power Dissipation Power measurements are made with outputs unloaded. Parameter Powerdown Current Powerup Current* Standby Current Symbol Test Conditions Min IDDO MCLK present; FSEP = 0.4 V -- IDD1 MCLK, FSEP present; all channels powered up -- IDDS MCLK, FSEP present; all channels powered down -- Typ 0.4 33 7 Max 1 40 10 Unit mA mA mA
* A nominal 6 mA decrease in current per channel put into standby.
Transmission Characteristics
Table 10. Analog Interface Parameter Input Resistance, VFXIN Input Voltage, VFXIN Load Resistance, VFRON to VFROP Load Capacitance, VFRON to VFROP Output Resistance, VFRO Symbol RVFXI VIX RLVFRO CLVFRO ROVFRO Test Conditions 1 V < |VFxI| < 4 V Relative to ground Differential load -- 0 dBm0, 1020 Hz PCM code applied to DR Channel under test in powerdown Alternating 0 A-law PCM code applied to DR FSEP = active, no load, channel under test in powerdown Alternating 0 A-law PCM code applied to DR FSEP = 0.4 V RL = 2 k (differential) Min Typ 100 -- 2.25 2.35 2 -- -- -- -- 2 Max 300 2.5 -- 100 20 Unit k V k pF V V mV A Vp-p
dc Output Voltage, VFROP, VFRON
VOR
3000 -- 10000 2.20 2.35 2.5 2.15 2.35 -60 -30 2.6 -- -- -- 2.65 60 30 --
dc Output Voltage, VFROP, VFRON VORPD Standby Differential dc Output VOR VFROP - VFRON Output Leakage Current, VFROP, IOVFRO VFRON Powerdown Output Voltage Swing, VFROP - VFRON VSWR
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Transmission Characteristics (continued)
ac Transmission Characteristics
Unless otherwise noted, the analog input is a -26 dBm (at 813 ), 1020 Hz sine wave. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Table 11. Absolute Gain Parameter Encoder Milliwatt Response (transmit gain tolerance) Decoder Milliwatt Response (receive gain tolerance) Relative Gain Variation Referenced to DmW Symbol EmW Test Conditions Signal input of 0.0452 Vrms (-26 dBm at 813 at 1020 Hz) Measured differential relative to 0.902 Vrms, PCM input of 0 dBm0 1020 Hz RL = 10 k, receive gain in -7.0 dB mode Decoder gain = -3.5 dB mode Min* Typ -- -0.20 Max* Unit -- dBm0
DmW
--
-7.20
--
dBm0
RGR
--
3.5
--
dB
* Combination test results are translated into system-level characteristics guaranteed by Table 21, Figure 8, and Figure 9. Overall system-level tolerances are +0.3 dB to -0.7 dB in both directions. Therefore, nominal analog levels are shifted by -0.2 dB.
Table 12. Gain Tracking Parameter Transmit Gain Tracking Error Sinusoidal Input A-law Receive Gain Tracking Error Sinusoidal Input A-law Table 13. Distortion Parameter Transmit Signal to Distortion Symbol SDX Test Conditions 3 dBm0 VFXI -30 dBm0 -30 dBm0 VFXI -40 dBm0 -40 dBm0 VFxI -45 dBm0 3 dBm0 VFRO -30 dBm0 -30 dBm0 VFRO -40 dBm0 -40 dBm0 VFRO -45 dBm0 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz 200 Hz--3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz Transmit or receive, two frequencies in the range (300 Hz--3400 Hz) at -6 dBm0 Min 35 29 25 35 29 25 -- Typ -- -- -- -- -- -- -- Max Unit -- dB -- dB -- dB -- dB -- dB -- dB -38 dBm0 Symbol GTX GTR Test Conditions +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 +3 dBm0 to -37 dBm0 -37 dBm0 to -50 dBm0 Min -0.25 -0.50 -0.25 -0.50 Typ -- -- -- -- Max 0.25 0.50 0.25 0.50 Unit dB dB dB dB
Receive Signal to Distortion
SDR
Single-frequency Distortion, Transmit Single-frequency Distortion, Receive Intermodulation Distortion
SFDX
SFDR
--
--
-40
dBm0
IMD
--
--
-42
dBm0
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 14. Envelope Delay Distortion Parameter TX Delay, Absolute* TX Delay, Relative to 1600 Hz Symbol DXA DXR Test Conditions f = 1600 Hz f = 500 Hz--600 Hz f = 600 Hz--800 Hz f = 800 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz f = 1600 Hz f = 500 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz Any time slot/channel to any time slot/channel f = 1600 Hz Min -- -- -- -- -- -- -- -- 135 -44 -30 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 165 to 425 220 145 75 40 75 105 155 135 to 395 -- -- 90 125 175 305 to 625 Unit s s s s s s s s s s s s s s s
RX Delay, Absolute* RX Delay, Relative to 1600 Hz
DRA DRR
Round Trip Delay, Absolute*
DRTA
* Varies as a function of time slots chosen.
Overload Compression Figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dBm0).
9
8
FUNDAMENTAL OUTPUT POWER (dBm)
7
6
5 ACCEPTABLE REGION 4
3
2
1
1
2
3
4
5
6
7
8
9
FUNDAMENTAL INPUT POWER (dBm)
5-3586(F)
Figure 4. Overload Compression 18 Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 15. Decoder Limits Relative to Gain at 1020 Hz
Frequency (Hz) 15.6 46.8 62.5 453 2734 3140 3375 3984 5015 Min -0.150 -0.150 -0.150 -0.150 -0.150 -0.550 -0.850 -- -- Typ -- -- -- -- -- -- -- -- -- Max 0.150 0.150 0.150 0.150 0.150 0.150 0.150 -13.40 -28.00 Unit dB dB dB dB dB dB dB dB dB
Table 16. Encoder Limits, Includes Effect of Termination Impedance Filter Relative to Gain at 1020 Hz
Frequency (Hz) 15.6 46.8 62.5 453 2734 3140 3375 3984 5015 Min -- -- -- 0.400 -2.950 -3.950 -4.550 -- -- Typ -- -- -- -- -- -- -- -- -- Max -30.500 -25.600 -29.400 0.700 -2.650 -3.250 -3.850 -18.30 -35.00 Unit dB dB dB dB dB dB dB dB dB
Table 17. Termination Impedance Limits Relative to Gain at 1020 Hz
Frequency (Hz) 46.8 62.5 453 2734 3140 3375 3984 5015 Min 0 0.3 0.45 -2.95 -3.60 -4.05 -5.05 -6.35 Typ -- -- -- -- -- -- -- -- Max 1 0.8 0.65 -2.65 -3.20 -3.55 -4.45 -5.65 Unit dB dB dB dB dB dB dB dB
Table 18. Hybrid Path Limits Relative to Gain at 1020 Hz
Frequency (Hz) 46.8 62.5 453 2734 3140 3375 3984 Min -- -- -0.180 -0.410 -0.700 -1.640 -- Typ -- -- -- -- -- -- -- Max -26.000 -30.000 0.180 -0.050 0.100 -0.840 -25.00 Unit dB dB dB dB dB dB dB
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Transmission Characteristics (continued)
ac Transmission Characteristics (continued)
Table 19. Noise Parameter Transmit Noise Receive Noise Noise, Single Frequency f = 0 kHz--100 kHz Power Supply Rejection Transmit Symbol Test Conditions NXP -- NRP PCM code is A-law positive one NRS VFXIN = 0 Vrms, measurement at VFRO, DR = DX PSRX VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--50 kHz PSRX PCM code is positive one LSB. VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz f = 4 kHz--25 kHz f = 25 kHz--50 kHz SOS 0 dBm0, 300 Hz--3400 Hz input PCM code applied: 4600 Hz--7600 Hz 7600 Hz--8400 Hz 8400 Hz--50 kHz Min -- -- -- Typ -- -- -- Max -68 -75 -53 Unit dBm0p dBm0p dBm0
36 30
-- --
-- --
dB dB
Power Supply Rejection Receive
36 40 30
-- -- --
-- -- --
dB dB dB
Spurious Out-of-band Signals at VFRO Relative to Input
-- -- --
-- -- --
-30 -40 -30
dB dB dB
Table 20. Interchannel Crosstalk (Between Channels) Parameter Transmit to Receive Crosstalk 0 dBm0 Transmit Levels Receive to Transmit Crosstalk 0 dBm0 Receive Levels Transmit to Transmit Crosstalk 0 dBm0 Transmit Levels Receive to Receive Crosstalk 0 dBm0 Receive Levels Test Conditions f = 300 Hz--3400 Hz idle PCM code for channel under test; 0 dBm0 into any other single-channel VFXIN CTRX-XY f = 300 Hz--3400 Hz VFXIN = 0 Vrms for channel under test; 0 dBm0 code level on any other single-channel DR CTXX-XY f = 300 Hz--3400 Hz 0 dBm0 applied to any single-channel VFXIN except channel under test, which has VFXIN = 0 Vrms CTRX-RY f = 300 Hz--3400 Hz 0 dBm0 code level on any single-channel DR except channel under test, which has idle code applied Symbol CTXX-RY Min -- Typ -90 Max -75 Unit dB
--
-90
-75
dB
--
-90
-75
dB
--
-90
-75
dB
Note: For interchannel, crosstalk into the transmit channels (VFxIN) can be significantly affected by parasitic capacitive feeds from VFRO outputs. PWB layouts should be arranged to keep these parasitics low. The equivalent resistor looking from VFxIN toward VITR (Figure 16) should be kept as low as possible to minimize crosstalk. A maximum of 7 k at 3 kHz is recommended. This is easily achievable in this design with the structure as shown in Figure 16.
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Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Gain Flatness--Out of Band--High Frequencies
The transmit and receive directions' frequency-dependent loss relative to gain at 3400 Hz is shown below. This specification is met by using the T7507, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination).
Chip Set Performance Specifications
When using the T7507, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors, the following line card requirements are achieved; specified termination impedance is shown in Figure 5.
680 200
30 25
5-5324a(F)
ACCEPTABLE REGION
0.1 F
20 LOSS (dB)
Figure 5. Termination Impedance
12.5 10
Gain
Table 21. Gain Gain @ 1020 Hz Transmit Receive Receive Min -0.7 -4.2 -7.7 Typ 0 -3.5 -7.0 Max 0.3 -3.2 -6.7 Unit dB dB dB
0 -5 3400 4000 FREQUENCY (Hz)
5-5340(F)
4600
5000
Gain Flatness--In Band
Table 22. Gain Flatness--In Band The in-band frequency-dependent loss relative to gain at frequency = 1020 Hz, for the transmit and receive directions. This specification is met by using the T7507, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination). Frequency (Hz) 300--400 400--600 600--2400 2400--3000 3000--3400 Min -0.3 -0.3 -0.3 -0.3 -0.3 Max 1.00 0.75 0.35 0.55 1.50 Unit dB dB dB dB dB
Figure 6. Transmit and Receive Direction Frequency-Dependent Loss Relative to Gain at 3400 Hz The loss for frequencies 3400 Hz < f < 4600 Hz is given by: ( 4000 - f ) b = 12.5 1 - sin ---------------------------- dB 1200
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T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Return Loss
The following template is achieved.
Chip Set Performance Specifications
(continued)
Gain Flatness--Out of Band--Low Frequencies
Transmit direction only, loss relative to 1020 Hz. This specification is met by using the T7507, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination). Table 23. Gain Flatness--Out of Band--Low Frequencies Frequency (Hz) 16.67 40 50 60 Min Loss (dB) 30 26 30 30
18 RL (dB) 14
300 500
2000
3400
FREQUENCY (Hz)
5-5325(F)
Figure 8. Return Loss
Hybrid Balance
The following template is achieved.
Loss vs. Level Relative to Loss at -10 dBm Input at 1020 Hz
This specification is met by using the T7507, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination).
20 TBRL (dB) 16
1.6
300 500
2500
3400
FREQUENCY (Hz)
5-5326(F)
Figure 9. Hybrid Balance
0.6 LOSS (dB) 0.3 0 -0.3 -0.6 -55 -50 -40 -10 +3 dBm0
-1.6
5-5341(F)
Figure 7. Loss vs. Level
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Microprocessor Interface
Table 24. T7507 Microprocessor Interface Timing Frequency of CCLK = 2.048 MHz. Symbol tCCLCCH tCCHCCL tCCHCCH tCCH1CCH2 tCCL1CCL2 tCSLCCL tCCLCSH tCIVCCL tCCLCIX tCSHCSL tSU1BO2 tSU2BO1 tSU1RD tSU2RD tENL Parameter Time of CCLK Low Time of CCLK High Period of CCLK Rise Time of CCLK Fall Time of CCLK CSEL Low to CCLK Transition Test Conditions Min 160 160 488 -- -- 50 30 50 50 50 488 488 488 488 977 Max -- -- -- 50 50 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-- -- -- -- -- Measured from first CCLK low transition CSEL High Measured from eighth CCLK Low to CCLK low transition Setup Time, Data Input/Output Valid to CCLK Low -- Hold Time, CCLK Low to Data Input/Output Invalid -- Minimum Time Between Writes -- Setup Time for B0--B1 Data -- Setup Time for B0--B1 Data -- Setup Time for RD1, RD2, RD3 Data -- Setup Time for RD1, RD2, RD3 Data -- Enable Pulse Width --
Lucent Technologies Inc.
23
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Microprocessor Interface (continued)
1465 ns AT CCLK 2.048 MHz CSEL
CCLK
EN tCCL1CCL2 tSU1BO2 tSU1RD RD1, RD2, RD3 B0/B1 tENL tSU2BO1 tSU2RD tCCH1CCH2
NSTAT/NTSD
5-5808(F)
Figure 10. SLIC/Switch Interface Timing
tCCHCCL tCCL1CCL2 CCLK tCSLCCL CSEL tCIVCCL tCCLCIX DI tCIVCCL tCCLCIX DO NSTAT CH0 NTSD CH0 NSTAT CH1 NTSD CH1 NSTAT CH2 NTSD CH2 NSTAT CH3 NTSD CH3 NSTAT CH0
5-4517.b(F)
tCCHCCH
tCCLCCH tCCH1CCH2 tCSHCSL
tCCLCSH M D4 D3 D2 D1 D0 M
C1
D0
Figure 11. Microprocessor Interface Write Timing
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Timing Characteristics
Table 25. Clock Section See Figures 12--14. Symbol tMCHMCL1 tCDC tMCH1MCH2 tMCL2MCL1 Parameter Clock Pulse Width Duty Cycle, MC Clock Rise and Fall Time Test Conditions -- -- -- Min 97 40 0 Typ -- -- -- Max -- 60 15 Unit ns % ns
Table 26. T7507 Transmit Section (Delayed Timing) See Figure 12. Symbol tMCHDV tMCHDV1 tMCLDZ* tSPHMCL tMCLSPH tSPLMCL tSPHSPL Parameter Data Enabled on TS Entry Data Delay from MC Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 15 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 60 60 100 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCLDZ is referenced to a high-impedance state.
Table 27. T7507 Transmit Section (Nondelayed Timing) See Figure 13. Symbol tSPHDV tMCHDV1 tMCHDZ* tSPHMCL tMCLSPH tSPLMCL tSPHSPL Parameter Data Enabled on TS Entry Data Delay from FSX Data Float on TS Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Low Setup Frame-sync Pulse Width Test Conditions 0 < CLOAD < 100 pF 0 < CLOAD < 100 pF CLOAD = 0 -- -- -- -- Min 0 0 0 50 50 50 0.1 Typ -- -- -- -- -- -- -- Max 80 60 30 -- -- -- 125 - tMCHMCH Unit ns ns ns ns ns ns s
* Timing parameter tMCHDZ is referenced to a high-impedance state.
Table 28. T7507 Receive Section See Figures 12--14. Symbol tDVMCL tMCLDV tSPHMCL tSPLMCL Parameter Receive Data Setup Receive Data Hold Frame Separation Hold Time Frame Separation Low Setup Test Conditions -- -- -- -- Min 30 15 50 50 Typ -- -- -- -- Max -- -- -- -- Unit ns ns ns ns
Lucent Technologies Inc.
25
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Timing Characteristics (continued)
TIME SLOT tMCHMCL1 MCLK tMCLSPH tSPHMCL FSEP tSPHSPL tMCHDV1 Dx BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCLDZ BIT 7 BIT 8 1 2 tMCH1MCH2 tSPLMCL 3 4 5 tMCL2MCL1 tSPLMCL 6 7 8 1
tDVMCL
tMCLDV
DR
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
DR STABLE
5-3581.g(F)
Figure 12. T7507 Transmit and Receive Timing, FSEP = 1 MCLK or IFS = 1, Delayed Timing (D0 = 0)
TIME SLOT tMCHMCL1 MCLK tMCLSPH tSPHMCL FSEP tSPHSPL tMCHDV1 Dx BIT 1 tMCHDV1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 tMCHDZ BIT 7 BIT 8 tSPLMCL 1 2 3 tMCH1MCH2 4 5 tMCL2MCL1 tSPLMCL 6 7 8 1
tDVMCL
tMCLDV
DR
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
DR STABLE
5-3581.h(F)
Figure 13. T7507 Transmit and Receive Timing, FSEP = 1 MCLK or IFS = 1, Nondelayed Timing (D0 = 1)
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Lucent Technologies Inc.
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Timing Characteristics (continued)
TIME SLOT tMCHMCL1 MCLK tSPHMCL FSEP tDVMCL DR BIT 1 BIT 2 DR STABLE
5-3582.b(F)
1
2
3
4
5
6
7
8
tSPLMCL
tMCLDV BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
Figure 14. T7507 Receive Timing, FSEP > 1 MCLK and IFS = 0, Delayed Timing (D3 = 0)
TIME SLOTS
19 20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FSEP
DX X0 X1 X3 X2
DR R2 R0 R1 R3
Programming: 00010111 00100101 01001111 01101000 CHANNEL 0 IN TIME SLOT 23 CHANNEL 1 IN TIME SLOT 5 CHANNEL 2 IN TIME SLOT 15 CHANNEL 3 IN TIME SLOT 8
5-4853(F)
Figure 15. Typical Frame Sync Timing (IFS = 0)
Lucent Technologies Inc.
27
28
RPROG 63.4 k IPROG DCOUT TG RTG 7.87 k CB2 DX DR VTX 0.1 F VFXIN PER CHANNEL PCM HIGHWAY VBAT2 PWR VBAT2 CBAT2 0.1 F TO TEST BUS RD1I RD2I RD3I TRING RCVN TLINE PT RCVP VFROP FSEP IFS SYNC L7583 SWITCH RBAT PR L8567 SLIC EN FGND TBAT VFRON 1/4 T7507 CODEC COMMON EN0 EN1 EN2 TSD INTESTin INTESTout B0 RTSP 2.0 M RTSP NSTAT NTSD RD1C RD2C RD3C RTSN RTS2 274 k VBAT1 CF1 DGND BGND AGND AGND VCC VDD RTSN 2.0 M CF2 NTSD0 NTSD1 NTSD2 NTSD3 RTS1 402 CRTS2 0.27 F CRTS1 0.022 F B1 AGND EN3 B0C B1C NSTATC NTSDC VDD CDD 0.1 F DXEN MCLK CSEL CCLK DI DO TIMING AND CONTROL INRING LATCH RRING 0.1 F VBAT CBAT1 CDD CCC 0.1 F 0.1 F 0.1 F CF2 CF1 0.47 F TO TO L8567 SLIC AND L8567 L7583 SLIC SWITCH 1, 2, 1, 2, OR 3 AND 3 FROM L8567 SLIC 1, 2, AND 3 FROM L7583 1, 2, AND 3 TO L7583B 1, 2, AND 3
Applications
CROWBAR PROTECTOR
RPT
TIP
50
RPR
RING
50
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
CROWBAR PROTECTOR
Figure 16. Basic Loop Start Application Using the T7507 and the L7583 Switch for 200 + (680 || 100 nF) Complex Termination and Hybrid Balance
VRING
5-5807a(F)
Lucent Technologies Inc.
Data Sheet August 1999
Data Sheet August 1999
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Outline Diagram
44-Pin PLCC
Controlling dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative.
17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.66 MAX 17.65 MAX
17
29
18
28
4.57 MAX SEATING PLANE 0.10
1.27 TYP
0.53 MAX
0.51 MIN TYP
5-2506r.8(F)
Lucent Technologies Inc.
29
T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance
Data Sheet August 1999
Ordering Information
Device Part No. T - 7507 - - - ML2-D T - 7507 - - - ML2-DT Description Quad PCM Codec (Dry-bagged) Quad PCM Codec (Dry-bagged, Tape and Reel) Package 44-Pin PLCC 44-Pin PLCC Comcode 108496704 108496712
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved
August 1999 DS99-273ALC (Replaces DS99-080ALC)

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