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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12534-4E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89620R Series
MB89623R/625R/P625/W625/626R/627R/P627/W627/T627R MB89PV620
s DESCRIPTION
The MB89620R series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, an A/D converter, and an external interrupt. The MB89620R series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Various package options Three types of QFP packages (1 mm, 0.65 mm, or 0.5 mm lead pitch) SDIP packages * High-speed processing at low voltage Minimum execution time: 0.4 s/3.5 V, 0.8 s/2.7 V * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
* Four types of timers 8-bit PWM timer (also usable as a reload timer) 8-bit pulse width count timer (Continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 20-bit timebase timer * Two serial interfaces Switchable transfer direction allows communication with various equipment. * 8-bit A/D converter Sense mode function enabling comparison at 5 s Activation by an external input capable
(Continued)
MB89620R Series
(Continued) * External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) * Bus interface functions Including hold and ready functions
s PACKAGE
64-pin Plastic SH-DIP 64-pin Plastic LQFP 64-pin Plastic QFP 64-pin Plastic QFP
(DIP-64P-M01)
(FPT-64P-M03)
(FPT-64P-M06)
(FPT-64P-M09)
64-pin Ceramic SH-DIP
64-pin Ceramic MQFP
64-pin Ceramic MDIP
(DIP-64C-A06)
(MQP-64C-P01)
(MDP-64C-P02)
2
MB89620R Series
s PRODUCT LINEUP
Part number Parameter
MB89P625 MB89P627 MB89623R MB89625R MB89626R MB89627R MB89T627R MB89W625 MB89W627 MB89PV620 Piggyback/ evaluation product for evaluation and development
Classificati on Mass production products (mask ROM products)
External ROM products
One-time PROM products/EPROM products
16 K x 8 bits (internal PROM, programmable with generalpurpose EPROM programmer)
ROM size
8 K x 8 bits 16 K x 8 bits 24 K x 8 bits 32 K x 8 bits External (internal (internal (internal (internal ROM mask ROM) mask ROM) mask ROM) mask ROM)
32 K x 8 bits 32 K x 8 bits (internal (external PROM, programmable ROM) with generalpurpose EPROM programmer)
RAM size CPU functions
256 x 8 bits 512 x 8 bits 768 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Input ports: Output ports (N-ch open-drain): I/O ports (N-ch open-drain) Output ports (CMOS): I/O ports (CMOS): Total:
1 K x 8 bits
1 K x 8 bits
512 x 8 bits
1 K x 8 bits
1 K x 8 bits
136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 s /10 MHz 3.6 s/10 MHz 5 (4 ports also serve as peripherals.) 8 (All also serve as peripherals.) 8 (4 ports also serve as peripherals.) 8 (All also serve as bus control pins.) 24 (All also serve as bus pins or peripherals.) 53
Ports
8-bit PWM timer 8-bit pulse width count timer 16-bit timer/ counter 8-bit serial I/O 1, 8-bit serial I/O 2 8-bit A/D converter
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 s to 3.3 ms) 8-bit resolution PWM operation (conversion cycle: 102 s to 839 ms) 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 s) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 s) 8-bit pulse width measurement operation (Continuous measurement "H" pulse width/"L" pulse width/from to /from to capable) 16-bit timer operation (operating clock cycle: 0.4 s) 16-bit event counter operation (Rising/falling/both edges selectable) 8 bits LSB first/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 s, 3.2 s, 12.8 s) 8-bit resolution x 8 channels A/D conversion mode (conversion time: 18 s) Sense mode (conversion time: 5 s) Continuous activation by an external activation or an internal timer capable Reference voltage input
(Continued)
3
MB89620R Series
(Continued)
Part number Parameter
MB89P625 MB89P627 MB89623R MB89625R MB89626R MB89627R MB89T627R MB89W625 MB89W627 MB89PV620 4 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Sleep mode, stop mode CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V
MBM27C256 A-20TV MBM27C256 A-20CZ
External interrupt Standby modes Process Operating voltage* EPROM for use
--
*: Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.")
s PACKAGE AND CORRESPONDING PRODUCTS
Package MB89623R MB89625R MB89626R MB89627R MB89T627R MB89P625 x* MB89P627 MB89W625 MB89W627 x x* x* x x* x x x x x x x x x x x MB89PV620 x x* x x* x
DIP-64P-M01 FPT-64P-M03 FPT-64P-M06 FPT-64P-M09 DIP-64C-A06 MQP-64C-P01 MDP-64C-P02 : Available
x: Not available
*: Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available. 64SD-64QF2-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M03 64SD-64SQF-8L: For conversion from DIP-64P-M01 or DIP-64C-A06 to FPT-64P-M09 Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Note: For more information about each package, see section "s Package Dimensions."
4
MB89620R Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * On the MB89623R, the upper half of the register bank cannot be used. * On the MB89P627, the program area starts from address 8007H but on the MB89PV620 and MB89627R starts from 8000H. (On the MB89P627, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV620 and MB89627R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P627.) * The stack area, etc., is set at the upper limit of the RAM. * The external area is used.
2. Current Consumption
* In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section "s Electrical Characteristics".)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following points: * A pull-up resistor cannot be set for P40 to P47 on the MB89P625, MB89W625, MB89P627, and MB89W627. * A pull-up resistor is not selectable for P50 to P57 when the A/D converter is used. * Options are fixed on the MB89PV620.
5
MB89620R Series
4. Differences between the MB89620 and MB89620R Series
* Memory access area Memory access area of the following products is the same; both the MB89625 and MB89625R, and both the MB89627 and MB89627R. The access area of the MB89623 and MB89626 is different from that of the MB89623R and MB89626R respectively when using in external bus mode. See below. Address 0000H to 007FH 0080H to 017FH 0180H to 027FH 0280H to BFFFH C000H to DFFFH E000H to FFFFH ROM area External area I/O area RAM area Memory area MB89623 I/O area RAM area Access prohibited External area Access prohibited ROM area MB89623R
Address 0000H to 007FH 0080H to 037FH 0380H to 047FH 0480H to 7FFFH 8000H to 9FFFH A000H to FFFFH ROM area I/O area RAM area
Memory area MB89626 I/O area RAM area Access prohibited External area External area Access prohibited ROM area MB89626R
* Other specifications Both the MB89620R and MB89620 series is the same. * Electrical specifications/electrical characteristics Electrical specifications of the MB89620R series are the same with that of the MB89620 series.
s CORRESPONDENCE BETWEEN THE MB89620 AND MB89620R SERIES
* The MB89620R series is the reduction version of the MB89620 series. * The MB89620 and MB89620R series consist of the following products:
MB89620 series MB89620R series MB89623 MB89623R MB89625 MB89625R MB89626 MB89626R MB896267 MB89P625 MB896267R MB89P627 MB89PV620
MB89620 series MB89620R series 6
MB89W625 MB89W627 MB89T627R
MB89620R Series
s PIN ASSIGNMENT
(Top view) P36/WTO P37/PTO P40 P41 P42 P43 P44/BZ P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 VCC 62 92 61 A14 91 60 A13 90 59 A8 89 58 A9 88 57 A11 87 56 OE 86 55 A10 85 54 CE 84 53 O8 83 52 O7 82 51 O6 81 50 O5 80 49 O4 79 48 47 46 45 44 Each pin inside the 43 dashed line is for the 42 41 MB89PV620 only. 40 39 38 37 36 35 34 33 VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30/ADST VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS
65 66 67 68 69 70 71 72 73 74 75 76 77 78
(DIP-64P-M01) (DIP-64C-A06) (MDP-64C-P02)
(Top view)
P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P45/SCK2 P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P30/ADST VSS
P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15
P63/INT3 P64 RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC
(FPT-64P-M03) (FPT-64P-M09)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7
MB89620R Series
(Top view) P44/BZ P43 P42 P41 P40 P37/PTO P36/WTO VCC P35/PWC P34/EC P33/SI1 P32/SO1 P31/SCK1 P45/SCK2 P46/SO2 P47/SI2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 P64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
85 86 87 88 89 90 91 92 93
77 76 75 74 73 72 71 70 69
Each pin inside the dashed line is for the MB89PV620 only. 20 21 22 23 24 25 26 27 28 29 30 31 32
P30/ADST VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC
* Pin assignment on package top (MB89PV620 only) Pin no. 65 66 67 68 69 70 71 72 Pin name N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 73 74 75 76 77 78 79 80 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin name OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. 8
RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK (FPT-64P-M06) (MQP-64C-P01)
94 95 96 65 66 67 68
84 83 82 81 80 79 78
MB89620R Series
s PIN DESCRIPTION
Pin no. SH-DIP*1 MDIP*2 30 31 28 29 27 QFP1*3 MQFP*4 23 24 21 22 20 LQFP*5 QFP2*6 22 23 20 21 19 Pin name X0 X1 MOD0 MOD1 RST C B Operating mode selection pins Connect directly to VCC or VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower address output and data I/O. General-purpose I/O ports When an external bus is used, these ports function as upper address output. General-purpose output-only port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. General-purpose output-only port When an external bus is used, this port can also be used as a hold acknowledge output by setting the BCTR. General-purpose output-only port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. General-purpose output-only port When an external bus is used, this port functions as a ready input. General-purpose output-only port When an external bus is used, this port functions as a clock output. General-purpose output-only port When an external bus is used, this port functions as a write signal output. General-purpose output-only port When an external bus is used, this port functions as a read signal output. General-purpose output-only port When an external bus is used, this port functions as an address latch signal output. Circuit type A Crystal oscillator pins Function
56 to 49
49 to 42
48 to 41 P00/AD0 to P07/AD7 40 to 33 P10/A08 to P17/A15 32 P20/BUFC
D
48 to 41
41 to 34
D
40
33
F
39
32
31
P21/HAK
F
38
31
30
P22/HRQ
D
37
30
29
P23/RDY
D
36
29
28
P24/CLK
F
35
28
27
P25/WR
F
34
27
26
P26/RD
F
33
26
25
P27/ALE
F
(Continued)
*1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01 *2: MDP-64C-P02 *5: FPT-64P-M03 *3: FPT-64P-M06 *6: FPT-64P-M09 9
MB89620R Series
(Continued)
Pin no. SH-DIP MDIP*2 58
*1
QFP1*3 MQFP*4 51
LQFP*5 QFP2*6 50
Pin name P30/ADST
Circuit type E
Function General-purpose I/O port Also serves as an A/D converter external activation. This port is a hysteresis input type. General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the data input for the 8-bit serial I/O 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the external clock input for the 16-bit timer/counter. This port is a hysteresis input type. General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width count timer. This port is a hysteresis input type. General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width count timer. This port is a hysteresis input type. General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. This port is a hysteresis input type. N-ch open-drain I/O ports These ports are a hysteresis input type. N-ch open-drain I/O port Also serves as a buzzer output. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the clock I/O for the 8-bit serial I/O 2. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the data output for the 8-bit serial I/O 2. This port is a hysteresis input type. N-ch open-drain I/O port Also serves as the data input for the 8-bit serial I/O 2. This port is a hysteresis input type.
59
52
51
P31/SCK1
E
60
53
52
P32/SO1
E
61
54
53
P33/SI1
E
62
55
54
P34/EC
E
63
56
55
P35/PWC
E
1
58
57
P36/WTO
E
2
59
58
P37/PTO
E
3 to 6 7
60 to 63 64
59 to 62 P40 to P43 63 P44/BZ
G G
8
1
64
P45/SCK2
G
9
2
1
P46/SO2
G
10
3
2
P47/SI2
G
(Continued)
*1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01 *2: MDP-64C-P02 *5: FPT-64P-M03 *3: FPT-64P-M06 *6: FPT-64P-M09
10
MB89620R Series
(Continued)
Pin no. SH-DIP*1 MDIP*2 11 to 18 22 to 25 QFP1*3 MQFP*4 4 to 11 15 to 18 LQFP*5 QFP2*6 3 to 10 Pin name P50/AN0 to P57/AN7 Circuit type H I Function N-ch open-drain output-only ports Also serve as the analog input for the A/D converter. General-purpose input-only ports Also serve as an external interrupt input. These ports are a hysteresis input type. General-purpose input-only port This port is a hysteresis input type. Power supply pin Power supply (GND) pins A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply (GND) pin Use this pin at the same voltage as VSS. *3: FPT-64P-M06 *6: FPT-64P-M09
14 to 17 P60/INT0 to P63/INT3 18 56 24, 49 11 12 13 P64 VCC VSS AVCC AVR AVSS
26 64 32, 57 19 20 21
19 57 25, 50 12 13 14
I -- -- -- -- --
*1: DIP-64P-M01, DIP-64C-A06 *4: MQP-64C-P01
*2: MDP-64C-P02 *5: FPT-64P-M03
11
MB89620R Series
* External EPROM pins (MB89PV620 only) Pin no. MDIP 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 --
*1
MQFP*2 66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 65 76 81 90
Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC N.C.
I/O O O "H" level output pin Address output pins
Function
I
Data input pins
O I
Power supply (GND) pin Data input pins
O O O O
ROM chip enable pin Outputs "H" during standby. Address output pin ROM output enable pin Outputs "L" at all times. Address output pins
O O O -- EPROM power supply pin Internally connected pins Be sure to leave them open.
*1: MDP-64C-P02 *2: MQP-64C-P01
12
MB89620R Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * At an oscillation feedback resistor of approximately 1 M/5.0 V
X0
Standby control signal
B
C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input
N-ch
D
R P-ch
* CMOS output * CMOS input
N-ch
* Pull-up resistor optional (except P22 and P23) E
R P-ch
* CMOS output * Hysteresis input
N-ch
* Pull-up resistor optional F
P-ch
* CMOS output
N-ch
(Continued)
13
MB89620R Series
(Continued)
Type G
R
Circuit
Remarks * N-ch open-drain output * Hysteresis input
N-ch
* Pull-up resistor optional (MB89623R, MB89625R, MB89626R, and MB89627R only) * N-ch open-drain output * Analog input
H
R
N-ch Analog input
* Pull-up resistor optional * Hysteresis input * Pull-up resistor optional
I
R
14
MB89620R Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
15
MB89620R Series
s PROGRAMMING TO THE EPROM ON THE MB89P625
The MB89P625 is an OTPROM version of the MB89620R series.
1. Features
* 16-Kbyte PROM on chip * Options can be set using the EPROM programmer. * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below.
Single chip Address
0000H I/O 0080H RAM 0280H External area BFF0H External area BFF6H External area C000H PROM 16 KB FFFFH
EPROM mode (Corresponding addresses on the EPROM programmer)
3FF0H Option area 3FF6H Vacancy (Read value: FFH) 4000H EPROM 16 KB 7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P625 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed as follows: * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see "4. Setting OTPROM Options.") (3) Program to 3FF0H to 7FFFH with the EPROM programmer.
16
MB89620R Series
4. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: * OTPROM option bit map (MB89P625) Address Bit 7 Vacancy 3FF0H Readable and writable P07 Pull-up 1: No 0: Yes P17 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P57 Pull-up 1: No 0: Yes Vacancy 3FF5H Readable and writable Bit 6 Vacancy Readable and writable P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P56 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 5 Vacancy Readable and writable P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 4 Vacancy Readable and writable P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes Bit 3 Vacancy Readable and writable P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes Bit 2 Reset pin output 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes Bit 1 Oscillation
stabilization
Bit 0 Power-on reset 1: Yes 0: No P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes
time 1: Crystal 0: Ceramic P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes
3FF1H
3FF2H
3FF3H
3FF4H
Note: Each bit is set to `1' as the initialized value, therefore the pull-up option is not selected.
17
MB89620R Series
s PROGRAMMING TO THE EPROM ON THE MB89P627
The MB89P627 is an OTPROM version of the MB89620R series.
1. Features
* 32-Kbyte PROM on chip * Options can be set using the EPROM programmer. * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Single chip Address
0000H I/O 0080H RAM 0480H External area 8000H External area 8007HH
EPROM mode (Corresponding addresses on the EPROM programmer)
0000H Option area 0007H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P627 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed as follows: * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as a single chip assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see "4. Setting OTPROM Options.") (3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89620R Series
4. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: * OTPROM option bit map (MB89P627) Address Bit 7 Vacancy 0000H Readable and writable P07 Pull-up 1: No 0: Yes P17 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P57 Pull-up 1: No 0: Yes Vacancy 0005H Readable and writable Vacancy 0006H Readable and writable Bit 6 Vacancy Readable and writable P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P56 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Bit 5 Vacancy Readable and writable P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P55 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Bit 4 Vacancy Readable and writable P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P54 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 3 Vacancy Readable and writable P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 2 Reset pin output 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 1 Oscillation
stabilization
Bit 0 Power-on reset 1: Yes 0: No P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes Vacancy Readable and writable
time 1: Crystal 0: Ceramic P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes Vacancy Readable and writable
0001H
0002H
0003H
0004H
Note: Each bit is set to `1' as the initialized value, therefore the pull-up option is not selected.
19
MB89620R Series
s HANDLING THE MB89P625/P627
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 h
Data verification
Assembly
2. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
3. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 Ws/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (A)) with intensity of 12000 W/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000A. Although erasure time will be much longer than with UV source at 2537A, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
20
MB89620R Series
4. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufacturer and programmer name Data I/O Co., Ltd. UNISITE MB89P625P-SH MB89P625PF MB89P625PFM SH-DIP-64 QFP-64 QFP-64 ROM-64SD-28DP-8L ROM-64QF-28DP-8L ROM-64QF2-28DP-8L 3900 2900 -- Advantest Corp. R4945A Recommended Recommended Recommended
Part number
Package
Compatible socket adapter Sun Hayato Co., Ltd.
Recommended Recommended Recommended --
*: It is required to connect a capacitor of approximately 0.1 F between VPP and GND, and VCC and GND. Inquiry:Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Data I/O Co., Ltd.: TEL:USA/ASIA(1)-206-881-6444 EUROPE(49)-8-985-8580 Advantest Corp.:TEL:Except JAPAN (81)-3-3930-4111
21
MB89620R Series
s PROGRAMMING TO THE EPROM PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
3. Memory Space
Memory space in 32-Kbyte PROM is diagrammed below.
Single chip Address
0000H I/O 0080H RAM 0480H Not available 8000H Not available 8006H PROM 32 KB FFFFH
Corresponding addresses on the EPROM programmer
0000H Not available 0006H EPROM 32 KB 7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
22
MB89620R Series
s BLOCK DIAGRAM
X0 X1
Oscillator
20-bit timebase timer
Clock controller 8-bit PWM timer RST Reset circuit (WDT) 8-bit pulse width count timer Port 3 P37/PTO
P36/WTO P35/PWC
P00/AD0 to P07/AD7 P10/A08 to P17/A15 MOD0 MOD1 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC
8
Ports 0 and 1
Internal bus
CMOS I/O port
16-bit timer/counter
P34/EC
8
8-bit serial I/O 1 External bus interface CMOS I/O port
P33/SI1 P32/SO1 P31/SCK1 P30/ADST
8-bit serial I/O 2 Port 4
P47/SI2 P46/SO2 P45/SCK2 P44/BZ 4 P40 to P43
Port 2 CMOS output port
Buzzer output
N-ch open-drain I/O port N-ch open-drain output port Port 5
RAM
8 F2MC-8L CPU 8-bit A/D converter
8
P50/AN0 to P57/AN7 AVR AVCC AVSS
ROM Port 6 External interrupt 4 4
P60/INT0 to P63/INT3 P64
The other pins VCC, VSS x 2
Input port
23
MB89620R Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89620R series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89620R series is structured as illustrated below. * Memory Space
MB89627R MB89P627 MB89T627R MB89W627 I/O 0080H RAM 768 B 0100H Register 0200H 0280H 0380H 0480H 8000H 8006H External area *2 External area External area 0480H 8000H A000H C000H *3 E000H FFFFH ROM* 1 8 KB FFFFH C000H ROM*1 16 KB FFFFH ROM 24 KB *3 External area *3 0480H 8000H 8006H External area *2 0200H Register 0200H 0100H Register RAM 1 KB
0000H
MB89PV620 I/O
0000H
MB89623R I/O
0000H
MB89625R MB89P625 MB89W625 I/O
0000H
MB89626R I/O
0000H
0080H RAM 1 KB 0100H Register
0080H RAM 256 B 0100H Register 0180H *3 0280H
0080H RAM 512 B 0100H
0080H
0200H
External ROM 32 KB
ROM 32 KB
FFFFH
FFFFH
*1: The ROM area is an external area depending on the mode. *2: Since addresses 8000H to 8005H for the MB89P627 and MB89W627 comprise an option area, do not use this area for the MB89PV620 and MB89627R. *3: Access to this area is prohibited when using external bus mode.
24
MB89620R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:
Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) * Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
25
MB89620R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt.
H-flag:Set to `1' when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to `1'. Interrupt is disabled when the flag is cleared to `0'. Cleared to `0' at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low High-low High
N-flag: Set to `1' if the MSB becomes `1' as the result of an arithmetic operation. Cleared to `0' when the bit is cleared to `0'. Z-flag: Set to `1' when an arithmetic operation results in 0. Cleared to `0' otherwise. V-flag: Set to `1' if the complement on 2 overflows as a result of an arithmetic operation. Cleared to `0' if the overflow does not occur. C-flag: Set to `1' when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. Set to the shift-out value in the case of a shift instruction.
26
MB89620R Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89620R. In the MB89623R, there are 16 banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to addresses 0180H to 01FFH using an external circuit. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. * Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
27
MB89620R Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) (R/W) (R/W) SMR1 SDR1 SMR2 SDR2 (R/W) (R/W) (R/W) TMCR TCHR TCLR (R/W) (W) (R/W) (R/W) (R/W) (R) (R/W) (W) (R/W) (R/W) (R/W) PDR3 DDR3 PDR4 BZCR PDR5 PDR6 CNTR COMR PCR1 PCR2 RLBR (R/W) (R/W) (R/W) STBC WDTC TBTC Read/write (R/W) (W) (R/W) (W) (R/W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 BCTR Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register External bus pin control register Vacancy Vacancy Standby control register Watchdog timer control register Timebase timer control register Vacancy Port 3 data register Port 3 data direction register Port 4 data register Buzzer register Port 5 data register Port 6 data register PWM control register PWM compare register PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register Vacancy 16-bit timer control register 16-bit timer count register (H) 16-bit timer count register (L) Vacancy Serial I/O 1 mode register Serial I/O 1 data register Serial I/O 2 mode register Serial I/O 2 data register
(Continued)
28
MB89620R Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) EIC1 EIC2 Read/write (R/W) (R/W) (R/W) Register name ADC1 ADC2 ADCD Register description A/D converter control register 1 A/D converter control register 2 A/D converter data register Vacancy External interrupt 1 control register 1 External interrupt 1 control register 2 Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy
29
MB89620R Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter Power supply voltage A/D converter reference input voltage Input voltage
Symbol VCC AVCC AVR VI VI2 VO VO2 IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 100 40 -20 -4 -50 -20 300 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *1
Remarks
AVR must not exceed AVCC + 0.3 V. Except P40 to P47*2 P40 to P47 Except P40 to P47*2 P40 to P47
Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
Average value (operating current x operating rate)
Average value (operating current x operating rate)
Average value (operating current x operating rate)
Average value (operating current x operating rate)
*1: Use AVCC and VCC set to the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB89620R Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value Min. Max. 2.2* 6.0* 6.0* 6.0 AVCC +85
Unit V V V V C
Remarks Normal operation assurance range* (MB89623R/625R/626R/627R) Normal operation assurance range*
(MB89P625/W625/P627/T627R/W627/PV620)
Power supply voltage
VCC AVCC
2.7* 1.5
Retains the RAM state in stop mode
A/D converter reference input voltage Operating temperature
AVR TA
0.0 -40
*: These values vary with the operating frequency and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics." Figure 1 Operating Voltage vs. Clock Operating Frequency
6
5 Operation assurance range Operating voltage (V) 4
Analog accuracy assured in the AVCC = VCC = 3.5 V to 6.0 V range
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Clock operating frequency (MHz) Note: The shaded area is assured only for the MB89623R/625R/626R/627R.
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 31
MB89620R Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol VIH
Pin name P00 to P07, P10 to P17, P22, P23 RST, MOD0, MOD1, P30 to P37, P60 to P64 P40 to P47 P00 to P07, P10 to P17, P22, P23 RST, MOD0, MOD1, P30 to P37, P40 to P47, P60 to P64 P50 to P57 P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57 RST
Condition
Value Min.
0.7 VCC
Typ.
Max.
VCC + 0.3
Unit
Remarks
V
"H" level input voltage
VIHS VIHS2 VIL

0.8 VCC
VCC + 0.3
V V V
0.8 VCC VSS - 0.3

VCC + 0.3
0.3 VCC
"L" level input voltage VILS
VSS - 0.3
0.2 VCC
V
Open-drain output pin application voltage "H" level output voltage
VD VD2

VSS - 0.3 VSS - 0.3

VCC + 0.3
V V
VSS + 6.0
VOH
IOH = -2.0 mA
4.0
V
"L" level output voltage
VOL
IOL = +4.0 mA
0.4
V
VOL2 Input leakage current ILI1 (Hi-z output leakage current)
0.4
V
P00 to P07, P10 to P17, P20 to P27, 0.0 V < VI < P30 to P37, VCC P40 to P47, P60 to P64, MOD0, MOD1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64, RST
5
A
Without pull-up resistor
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
k
(Continued)
32
MB89620R Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Condition
Value Min. -- Typ. 9 Max. 15
Unit
Remarks
ICC VCC
FC = 10 MHz Normal operating mode tinst*2 = 0.4 s
MB89623R/ 625R/626R/ mA 627R/T627R/ PV620 MB89P625/ W625 mA MB89P627/ W627 mA A mA
--
10
18
Power supply current*1
ICCS ICCH IA AVCC IAH Other than AVCC, AVSS, VCC, and VSS
FC = 10 MHz Sleep mode tinst*2 = 0.4 s Stop mode TA = +25C FC = 10 MHz, when starting A/D conversion FC = 10 MHz, TA = +25C, when stopping A/D conversion f = 1 MHz
-- -- --
3 -- 1
4 1 3
--
--
1
A
Input capacitance
CIN
--
10
pF
*1: In the case of the MB89PV620, the current consumed by the connected EPROM and ICE is not included. The power supply current is measured at the external clock. *2: For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
33
MB89620R Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RST "L" pulse width
Symbol tZLZH
Condition --
Value Min. 16 tXCYL Max. --
Unit ns
Remarks
Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH RST 0.2 VCC 0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V VCC 0.2 V
tOFF
0.2 V
0.2 V
34
MB89620R Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time
Symbol FC tXYCL PWH PWL tCR tCF
Pin name X0, X1 X0, X1 X0 X0
Condition
Value Min. 1 100 Max. 10 1000 -- 10
Unit MHz ns ns ns
Remarks
--
20 --
External clock External clock
* X0 and X1 Timing and Conditions
tXCYL PW tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
* Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1
X0
X1 Open
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit s Remarks tinst = 0.4 s when operating at FC = 10 MHz
35
MB89620R Series
(5) Clock Output Timing
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Cycle time CLK CLK
Symbol tCYC
Pin name
Condition
Value Min. 200 Max. -- 100
Unit ns ns
Remarks tXCYL x 2 at 10 MHz oscillation Approx. tCYC/2 at 10 MHz oscillation
CLK tCHCL
-- 30
tCYC tCHC 2.4 V CLK 0.8 V 2.4 V
36
MB89620R Series
(6) Bus Read Timing
(VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter
Valid address RD time
Symbol tAVRL tRLRH tAVDV tRLDV tRHDX tRHLH tRHAX tRLCH tCLRH tRLBL
Pin name
RD, A15 to A08, AD7 to AD0 RD AD7 to AD0, A15 to A08 RD, AD7 to AD0 AD7 to AD0, RD RD, ALE RD, A15 to A08 RD, CLK
Condition
Value Min.
1/4 tinst*- 64 ns 1/4 tinst*- 20 ns -- -- 0
Max.
-- -- 1/2 tinst* 1/2 tinst*- 80 ns -- -- -- -- -- -- --
Unit Remarks s s s s s s s s ns s s
In the case of no wait In the case of no wait
RD pulse width
Valid address data read time
RD data read time RD data hold time RD ALE time RD address invalid time RD CLK time CLK RD time RD BUFC time
--
1/4 tinst*- 40 ns 1/4 tinst*- 40 ns 1/4 tinst*- 40 ns 0
RD, BUFC A15 to A08, AD7 to AD0, BUFC
-5 5
BUFC valid address time tBHAV
*: For information on tinst, see "(4) Instruction Cycle."
CLK
2.4 V 0.8 V
tRHL
ALE
0.8 V
AD
2.4 V 0.8 V tAVD
0.7 VCC 0.3 VCC
0.7 VCC 0.3 VCC tRHDX
2.4 V 0.8 V
A
2.4 V 0.8 V tAVRL
tRLC tRLDV tRLR
2.4 V tCLRH 0.8 V tRHA
2.4 V 0.8 V
RD
0.8 V tRLBL
2.4 V tBHAV 2.4 V
BUFC
0.8 V
37
MB89620R Series
(7) Bus Write Timing
(VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Valid address ALE time ALE time address invalid time Valid address WR time WR pulse width Write data WR time WR data hold time WR ALE time WR CLK time CLK WR time ALE pulse width ALE CLK time
Symbol tAVLL tLLAX tAVWL tWLWH tDVWH tWHDX tWHLH tWLCH tCLWH tLHLL tLLCH
Pin name
AD7 to AD0, ALE, A15 to A08 AD7 to AD0, ALE, A15 to A08 WR, ALE WR AD7 to AD0, WR WR, A15 to A08 AD7 to AD0, WR WR, ALE WR, CLK
Condition
Value Min.
1/4 tinst*1- 64 ns 5 1/4 tinst*1- 60 ns 1/2 tinst* - 20 ns 1/2 tinst* - 60 ns
1 1
Max. -- -- -- -- -- -- -- -- -- -- -- --
Unit Remarks s ns s s s ns s s s ns s s
WR address invalid time tWHAX
--
1/4 tinst*1- 40 ns 1/4 tinst*1- 40 ns 1/4 tinst* - 40 ns 1/4 tinst* - 40 ns 0
1 1
ALE ALE,CLK
1/4 tinst*1- 35 ns*2 1/4 tinst* - 30 ns*
1 2
*1: For information on tinst, see "(4) Instruction Cycle." *2: These characteristics are also applicable to the bus read timing.
CLK
tLHLL tLLC
2.4 V 0.8 V
ALE
2.4 V 0.8 V tAVL tLLAX 2.4 V 0.8 V tDVW 2.4 V 0.8 V tAVW tWLW
tWHL 0.8 V
AD
2.4 V 2.4 V 0.8 V 0.8 V
2.4 V 0.8 V tWHD 2.4 V tCLWH 0.8 V tWHA
A
tWLC
WR
0.8 V
2.4 V
38
MB89620R Series
(8) Ready Input Timing
(VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter RDY valid CLK time CLK RDY invalid time
Symbol tYVCH tCHYX
Pin name RDY, CLK
Condition --
Value Min. 60 0 Max. -- --
Unit Remarks ns ns * *
*: These characteristics are also applicable to the read cycle.
CLK
2.4 V
2.4 V
ALE
AD
Address
Data
A
WR
tYVCH tCHYX
RDY
tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner.
39
MB89620R Series
(9) Serial I/O Timing
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time
Symbol tSCYC
Pin name SCK1, SCK2 SCK1, SO1 SCK2, SO2 SI1, SCK1 SI2, SCK2 SCK1, SI1 SCK2, SI2 SCK1, SCK2 SCK1, SCK2 SCK1, SO1 SCK2, SO2 SI1, SCK1 SI2, SCK2 SCK1, SI1 SCK2, SI2
Condition
Value Min. 2 tinst* Max. --
Unit Remarks s
SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time Serial clock "H" pulse width Serial clock "L" pulse width
tSLOV
-200 Internal shift clock mode 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst*
200
ns
tIVSH tSHIX tSHSL tSLSH
-- -- -- --
s s s s
SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time
tSLOV
External shift clock mode
0
200
ns
tIVSH tSHIX
1/2 tinst* 1/2 tinst*
-- --
s s
*: For information on tinst, see "(4) Instruction Cycle."
40
MB89620R Series
* Internal Shift Clock Mode
tSCYC SCK1 SCK2 0.8 V
2.4 V 0.8 V
tSLOV SO1 SO2 2.4 V 0.8 V
tIVSH SI1 SI2 0.8 VCC 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
* External Shift Clock Mode
tSLSH SCK1 SCK2 0.2 VCC 0.2 VCC tSHSL
0.8 VCC
0.8 VCC
tSLOV SO1 SO2 2.4 V 0.8 V
tIVSH 0.8 VCC SI1 SI2 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
41
MB89620R Series
(10) Peripheral Input Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2
Symbol Pin name tILIH1 tIHIL1 tILIH2 tIHIL2 tILIH2 tIHIL2 ADST PWC, EC, INT0 to INT3
Condition
Value Min. 2 tinst* Max. -- -- -- -- -- --
Unit s s s s s s
Remarks
--
2 tinst* 32 tinst* 32 tinst* 8 tinst* 8 tinst*
A/D mode Sense mode
*: For information on tinst, see "(4) Instruction Cycle."
tIHIL1
tILIH1
PWC EC INT0 to INT3
0.8 VCC 0.2 VCC 0.2 VCC
0.8 VCC
tIHIL2
tILIH2
ADST
0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
42
MB89620R Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage
Symbol Pin name
Condition --
Value Min. -- -- -- -- Typ. -- -- -- -- Max. 8 1.5 1.0 0.9
Unit Remarks bit LSB LSB LSB mV mV LSB s s A V V A
--
VOT -- VFST
AVR=AVCC
AVSS -1.0LSB AVSS +0.5LSB AVSS +2.0LSB AVR-3.0LSB AVR-1.5LSB AVR
-- -- -- -- -- IAIN -- -- IR
AVR = 5.0 V, when starting A/D conversion AVR = 5.0 V, when stopping A/D conversion
-- 44 tinst* 12 tinst* -- -- -- 100
0.5 -- -- 10 AVR AVCC
AN0 to AN7
-- 0.0 0.0 --
Reference voltage supply current IRH
AVR
--
--
1
A
*: For information on tinst, see "(4) Instruction Cycle" in "4 AC Characteristics."
6. A/D Converter Glossary
* Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("0000 0000" "0000 0001") with the full-scale transition point ("1111 1111" "1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values 43
MB89620R Series
Digital output Digital output 1111 1111 1111 1111 1111 * * 1110 1111 1110
** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **
Theoretical conversion value Theoretical conversion value Actual conversion value Actual conversion value (1 LSB x N + VOT) (1 LSB x N + VOT) 1 LSB = 1 LSB = AVR AVR 256 256 VNT - (1 LSB x N + VOT) VNT - (1 LSB x N + VOT) 1 LSB 1 LSB
Linearity error = Linearity error =
Linearity error Linearity error
V ( N + 1 ) T - VNT Differential linearity error = V ( N + 1 ) T - VNT- 1 Differential linearity error = -1 1 LSB 1 LSB Total error = Total error = VNT - (1 LSB x N + 1 LSB) VNT - (1 LSB x N + 1 LSB) 1 LSB 1 LSB
0000 0010 0000 0010 0000 0001 0000 0001 0000 0000 0000 0000 VOT VOT VNT V (N ++I)T VNT V (N I)T VFST VFST Analog input Analog input
7. Notes on Using A/D Converter
* Input impedance of the analog input pins The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. * Analog Input Equivalent Circiut
Sample hold circuit . C = 33 pF . Analog input pin Comparator If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. . R = 6 k . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector
* Error The smaller the | AVR - AVSS |, the greater the error would become relatively.
44
MB89620R Series
s EXAMPLE CHARACTERISTICS
(1) "L" Level Output Voltage (2) "H" Level Output Voltage
VOL vs. IOL
VOL (V) 0.5 VCC = 5.0 V 0.4 0.3 0.2 0.1 VCC = 6.0 V VCC = 3.0 V TA = +25C VCC = 4.0 V VCC - VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 0.0 0.0 -0.5
VCC - VOH vs. IOH
TA = +25C VCC = 2.5 V
VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
-1.0
-1.5
-2.0
-2.5
-3.0 IOH (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
VIN vs. VCC
TA = +25C
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN vs. VCC
TA = +25C VIHS
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
VILS
3
4
5
6
7 VCC (V)
0
1
2
3
4
5
6
7 VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
45
MB89620R Series
(5) Power Supply Current (External Clock)
ICC vs. VCC
TA = +25C 14 12 10 8 6 4 2 FC = 1 MHz 0 1 2 3 4 5 6 7 VCC (V) FC = 1 MHz 0 1 2 3 4 5 6 7 VCC (V) FC = 4 MHz FC = 10 MHz FC = 8 MHz 3 2 FC = 4 MHz 1 FC = 8 MHz 4
ICC (mA) 16
ICCS (mA) 5
ICCS vs. VCC
TA = +25C FC = 10 MHz
IA (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5
IA vs. AVCC
FC = 10 MHz TA = +25C
IR (A) 200 180 160 140 120 100 80 60 40 20
IR vs. AVR
TA = +25C
4.0
4.5
5.0
5.5
6.0
6.5
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
AVCC (V)
6.5 AVR (V)
(6) Pull-up Resistance
RPULL vs. VCC
TA = +25C
RPULL (k) 1000
100
10 1 2 3 4 5 6 VCC (V)
46
MB89620R Series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: * Transfer * Arithmetic operation * Branch * Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri x (x) (( x )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH prior to the instruction executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 47
MB89620R Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Note: During byte transfer to A, T A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
48
MB89620R Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
49
MB89620R Series
(Continued) Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP
~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3
# 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1
Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4
TL - - - - - - - - - - - - - - -
TH - - - - - - - - - - - - - - -
AH - - - - - - - - - - - - - - -
NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ----
OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI
~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6
# 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
50
H
3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F
L
0
1
2
0
NOP
SWAP
RET
1
MULU
DIVU
A SUBC A A A, T A A A XCH XOR AND OR
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP
2
ROLC
CMP
ADDC
s INSTRUCTION MAP
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
3
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
A
ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP
6
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel CALLV BNZ #4 rel CALLV BZ #5
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MB89620R Series
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
51
MB89620R Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P64 Power-on reset selection With power-on reset Without power-on reset Oscillation stabilization time selection Crystal oscillator: 218/FC(s) Ceramic oscillator: 214/FC(s) Reset pin output With reset output Without reset output MB89623R MB89625R MB89626R MB89627R Specify when ordering masking Selectable per pin. (P50 to P57 must be set to without a pull-up resistor when an A/D converter is used.) Selectable MB89P625 MB89W625 MB89P627 MB89W627 Set with EPROM programmer Can be set per pin. (P40 to P47 are available only for without a pull-up resistor.) Setting possible MB89PV620 MB89T627R Setting not possible
1
Fixed to without pull-up resistor
2
Fixed to with power-on reset Crystal oscillator (218/FC(s))
3
Selectable
Setting possible
4
Selectable
Setting possible
With reset output
52
MB89620R Series
s ORDERING INFORMATION
Part number MB89623RP-SH MB89625RP-SH MB89626RP-SH MB89627RP-SH MB89P625P-SH MB89P627-SH MB89T627RP-SH MB89623RPFV MB89625RPFV MB89623RPF MB89625RPF MB89626RPF MB89627RPF MB89P625PF MB89P627PF MB89T623RPF MB89T625RPF MB89T627RPF MB89623RPFM MB89625RPFM MB89626RPFM MB89627RPFM MB89P625PFM MB89P627PFM MB89T627RPFM MB89W625C-SH MB89W627C-SH MB89PV620CF MB89PV620C-SH Package Remarks
64-pin Plastic SH-DIP (DIP-64P-M01)
64-pin Plastic LQFP (FPT-64P-M03)
Lead pitch: 0.5 mm
64-pin Plastic QFP (FPT-64P-M06)
Lead pitch: 1.0 mm
64-pin Plastic QFP (FPT-64P-M09)
Lead pitch: 0.65 mm
64-pin Ceramic SH-DIP (DIP-64C-A06) 64-pin Ceramic MQFP (MQP-64C-P01) 64-pin Ceramic MDIP (MDP-64C-P02)
53
MB89620R Series
s PACKAGE DIMENSIONS
64-pin Plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 2.283 -.022
+0.22 +.008
INDEX-1
17.000.25 (.669.010)
INDEX-2
5.65(.222)MAX 3.00(.118)MIN 1.00 -0 .039 -0
+0.50 +.020
0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP
1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm(inches).
(Continued)
54
MB89620R Series
(Continued)
64-pin Plastic LQFP (FPT-64P-M03)
12.000.20(.472.008)SQ 10.000.10(.394.004)SQ
48 33
49
32
0.08(.003)
Details of "A" part
INDEX
1.50 -0.10 .059 -.004
17
+0.20 +.008
(Mounting height)
64
"A" LEAD No.
1 16
0~8
+0.08 -0.03 +.003 -.001
0.500.08 (.020.003)
0.18 .007
0.08(.003)
M
0.1450.055 (.006.002) 0.500.20 (.020.008) 0.45/0.75 (.018/.030)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
1998 FUJITSU LIMITED F64009S-3C-6
Dimensions in mm (inches).
(Continued)
55
MB89620R Series
(Continued)
64-pin Plastic QFP (FPT-64P-M06)
24.700.40(.972.016)
51
20.000.20(.787.008)
33
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
52
32
14.000.20 (.551.008) INDEX
64 20
18.700.40 (.736.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 19
1.00(.0394) TYP
0.400.10 (.016.004)
0.150.05(.006.002) 0.20(.008)
M
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details of "B" part
0
10
1.200.20 (.047.008)
C
2000 FUJITSU LIMITED F64013S-3C-3
Dimensions in mm (inches).
(Continued)
56
MB89620R Series
(Continued)
64-pin Plastic QFP (FPT-64P-M09)
14.000.20(.551.008)SQ
48
12.000.10(.472.004)SQ
33
1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 .005 -.001
+0.05 +.002
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
2000 FUJITSU LIMITED F64018S-1C-3
Dimensions in mm (inches).
(Continued)
57
MB89620R Series
(Continued)
64-pin Ceramic SH-DIP (DIP-64C-A06)
56.900.56 (2.240.022)
R1.27(.050) REF
8.89(.350) DIA TYP 18.750.25 (.738.010)
INDEX AREA
1.270.25 (.050.010) 5.84(.230)MAX 0.250.05 (.010.004) 3.400.36 (.134.014) 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 55.118(2.170)REF 0.46 -0.08 .018 -.003
+0.13 +.005
19.050.25 (.750.010)
0~9
1.45(.057) MAX
C
1994 FUJITSU LIMITED D64006SC-1-2
Dimensions in mm (inches).
(Continued)
58
MB89620R Series
(Continued)
64-pin Ceramic MQFP (MQP-64C-P01)
18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.00(.472)TYP
+0.40 +.016 -.008
INDEX AREA
1.20 -0.20 .047
1.000.25 (.039.010)
1.000.25 (.039.010)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.00(.709) TYP
1.270.13 (.050.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.400.10 (.016.004)
0.400.10 (.016.004)
1.20 -0.20 .047 -.008
+0.40 +.016
0.50(.020)TYP
10.82(.426) 0.150.05 MAX (.006.002)
C
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches).
(Continued)
59
MB89620R Series
(Continued)
64-pin Ceramic MDIP (MDP-64C-P02)
56.900.64 (2.240.025) 0~9
15.24(.600) TYP
18.750.30 (.738.012)
19.050.30 (.750.012)
INDEX AREA
2.540.25 (.100.010) 33.02(1.300)REF
0.250.05 (.010.002)
10.16(.400)MAX
1.270.25 (.050.010)
1.7780.25 (.070.010)
0.46 -0.08 +.005 .018 -.003 55.12(2.170)REF
+0.13
0.900.13 (.035.005)
3.430.38 (.135.015)
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches).
60
MB89620R Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0012 (c) FUJITSU LIMITED Printed in Japan

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