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TSA1204
DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER
s 0.5Msps to 20Msps sampling frequency s Adaptive power consumption: 120mW @ s Single supply voltage: 2.5V s s s s s s s
Independent supply for CMOS output stage with 2.5V/3.3V capability ENOB=11.2 @ Nyquist SFDR= -81.5 dBc @ Nyquist 1GHz analog bandwidth Track-and-Hold Common clocking between channels Dual simultaneous Sample and Hold inputs Multiplexed outputs Built-in reference voltage with external bias capability. 20Msps, 95mW@10Msps PIN CONNECTIONS (top view)
GNDBE D0(LSB) VCCBE REFPI VCCBI REFMI VCCBI INCMI AVCC AVCC OEB D1
index corner
48 AGND 1 INI 2
47 46 45
44 43 42
41 40 39 38 37 36 D2 35 D3 34 D4 33 D5 32 D6 31 D7
AGND 3 INIB 4 AGND 5 IPOL 6 AVCCB 7 AGND 8 INQ 9 AGND 10 INBQ 11 AGND 12 13 14 15 16 17 18 19 20 21 22 23 24
TSA1204
30 D8 29 D9 28 D10 27 D11(MSB) 26 VCCBE 25 GNDBE
DESCRIPTION The TSA1204 is a new generation of high speed, dual-channel Analog to Digital converter processed in a mainstream 0.25m CMOS technology yielding high performances and very low power consumption. The TSA1204 is specifically designed for applications requiring very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction to provide excellent static linearity and over 11.2 effective bits at Fs=20Msps, and Fin=10MHz. For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. Each ADC outputs are multiplexed in a common bus with small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially driven. The TSA1204 is available in extended (-40 to +85C) temperature range, in a small 48 pins TQFP package. APPLICATIONS
BLOCK DIAGRAM
+2.5V/3.3V
CLK
SELECT OEB
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
Timing
VINI VINBI VINCMI VREFPI VREFMI IPOL VREFPQ VREFMQ VINCMQ VINQ VINBQ
REF Q
DGND
CLK
SELECT
DGND
DVCC
GNDBI
VCCBE
AD 12 I channel
12
common mode
REF I
Polar.
M U X
12
12
Buffers
D0 TO D11
common mode AD 12 Q channel 12
s s s s s
Medical imaging and ultrasound 3G base station I/Q signal processing applications High speed data acquisition system Portable instrumentation
GND
GNDBE
PACKAGE
ORDER CODE
Part Number TSA1204IF TSA1204IFT EVAL1204/BA Temperature Range -40C to +85C -40C to +85C Package TQFP48 TQFP48 Conditioning Tray Tape & Reel Marking SA1204I SA1204I
7 x 7 mm TQFP48
Evaluation board
February 2003
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TSA1204
CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25C (unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol SFDR SNR THD SINAD ENOB Parameter Spurious Free Dynamic Range Signal to Noise Ratio Total Harmonics Distortion Signal to Noise and Distortion Ratio Effective Number of Bits 64.8 10.6 66.9 Test conditions Min Typ -81.5 68.5 -80 68 11.2 -70 Max -71.0 Unit dBc dB dBc dB bits
TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd I Tpd Q Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Data Output Delay (Clock edge to Data Valid) Data Pipeline delay for I channel Data Pipeline delay for Q channel Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state 10pF load capacitance Test conditions Min 0.5 45 22.5 22.5 50 25 25 9 7 7.5 1 1 Typ Max 20 55 Unit MHz % ns ns ns cycles cycles ns ns
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TSA1204
TIMING DIAGRAM
Simultaneous sampling on I/Q channels
N+3
N+4
N+5 N+6 N+12
N+13
I N+2 N-1 N Q N+1
N+7 N+8 N+9 N+10
N+11
CLK
Tpd I + Tod Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
OEB
sample N-8 I channel
sample N-6 Q channel
sample N Q channel
sample N+1 Q channel
sample N+2 Q channel
DATA OUTPUT sample N-9 I channel
sample N-7 Q channel
sample N+1 sample N+2 I channel I channel
sample N+3 I channel
PIN CONNECTIONS (top view)
GNDBE D0(LSB) VCCBE REFPI VCCBI REFMI VCCBI INCMI AVCC AVCC OEB
D1
index corner
48 AGND 1 INI 2
47 46
45
44 43
42
41
40
39
38 37 36 D2 35 D3 34 D4 33 D5 32 D6 31 D7
AGND 3 INIB 4 AGND 5 IPOL 6 AVCCB 7 AGND 8 INQ 9 AGND 10 INBQ 11
TSA1204
30 D8 29 D9 28 D10 27 D11(MSB) 26 VCCBE 25 GNDBE
AGND 12 13 14 15 16 17 18 19 20 21 22 23 24
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
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TSA1204
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI Description Analog ground I channel analog input Analog ground I channel inverted analog input Analog ground Analog bias current input Analog power supply Analog ground Q channel analog input Analog ground Q channel inverted analog input Analog ground Q channel top reference voltage Q channel bottom reference voltage Q channel input common mode Analog ground Analog power supply Digital power supply Digital ground Clock input Channel selection Digital ground Digital power supply Digital buffer ground 0V 2.5V 2.5V 0V 2.5V CMOS input 2.5V CMOS input 0V 2.5V 0V 0V 0V 0V 2.5V 0V 0V 0V 0V Observation Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name GNDBE VCCBE Description Digital buffer ground Digital Buffer power supply 0V 2.5V/3.3V CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) 2.5V/3.3V - See Application Note 0V 2.5V 2.5V 2.5V/3.3V CMOS input 2.5V 2.5V Observation
D11(MSB) Most Significant Bit output D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) VCCBE GNDBE VCCBI DVCC OEB AVCC AVCC INCMI REFMI REFPI Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Digital Buffer power supply Digital buffer ground Digital Buffer power supply Digital Buffer power supply Output Enable input Analog power supply Analog power supply I channel input common mode
I channel bottom reference voltage 0V I channel top reference voltage
ABSOLUTE MAXIMUM RATINGS
Symbol AVCC DVCC VCCBE VCCBI IDout Tstg ESD Analog Supply voltage Digital Supply voltage
1)
Parameter
Values 0 to 3.3 0 to 3.3
Unit V V V V mA C kV
1) 1)
Digital buffer Supply voltage
0 to 3.6 0 to 3.3 -100 to 100 +150 2 1.5 A
Digital buffer Supply voltage 1) Digital output current Storage temperature HBM: Human Body Model2) CDM: Charged Device Model3)
Latch-up Class4)
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5k 3). Discharge to Ground of a device that has been previously charged. 4). Corporate ST Microelectronics procedure number 0018695
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
OPERATING CONDITIONS
Symbol AVCC DVCC VCCBE VCCBI Parameter Analog Supply voltage Digital Supply voltage External Digital buffer Supply voltage Internal Digital buffer Supply voltage Min 2.25 2.25 1.8 2.25 Typ 2.5 2.5 2.5 2.5 Max 2.7 2.7 3.5 2.7 Unit V V V V
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TSA1204
Symbol VREFPI VREFPQ VREFMI VREFMQ INCMI INCMQ
1)
Parameter Forced top voltage reference 1) Forced bottom reference voltage 1) Forced input common mode voltage
Min 0.96 0 0.2
Typ
Max 1.4 0.4 1
Unit V V V
Condition VRefP-VRefM>0.3V
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25C (unless otherwise specified) ANALOG INPUTS
Symbol Parameter Test conditions Differential inputs mandatory Min 1.1 Typ 2.0 7.0 3 Vin@Full Scale, Fs=20Msps 1000 70 Max 2.8 Unit Vpp pF K MHz MHz
VIN-VINB Full scale reference voltage Cin Req BW ERB Input capacitance Equivalent input resistor Analog Input Bandwidth Effective Resolution Bandwidth
DIGITAL INPUTS AND OUTPUTS
Symbol Parameter Test conditions Min Typ Max Unit
Clock and Select inputs VIL VIH OEB input VIL VIH Logic "0" voltage Logic "1" voltage 0 0.75 x VCCBE VCCBE 0.25 x VCCBE V V Logic "0" voltage Logic "1" voltage 2.0 0 2.5 0.8 V V
Digital Outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage Iol=10A Ioh=10A 0 0.9 x VCCBE VCCBE -1.7 1.7 15 0.1 x VCCBE V V A pF
High Impedance leakage current OEB set to VIH Output Load Capacitance
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TSA1204
ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25C (unless otherwise specified) REFERENCE VOLTAGE
Symbol VREFPI VREFPQ VINCMI VINCMQ Parameter Top internal reference voltage Test conditions Min 0.807 Typ 0.89 Max 0.963 Unit V
Input common mode voltage
0.40
0.46
0.52
V
POWER CONSUMPTION
Symbol ICCA ICCD ICCBE ICCBI Pd Rthja Parameter Analog Supply current Digital Supply Current Digital Buffer Supply Current (10pF load) Digital Buffer Supply Current Power consumption in normal operation mode Thermal resistance (TQFP48) Min Typ 40 2 6.2 73 120 80 Max 49.5 3 9 221 155 Unit mA mA mA A mW C/W
ACCURACY
Symbol OE GE DNL INL Offset Error Gain Error Differential Non Linearity Integral Non Linearity Mono tonicity and no missing codes Parameter Min -1.8 -0.1 -0.93 -1.8 Typ -0.5 0 0.4 0.8 Max 1.8 0.1 +0.93 +1.8 Unit LSB % LSB LSB
Guaranteed
MATCHING BETWEEN CHANNELS
Symbol GM OM PHM XTLK Gain match Offset match Phase match Crosstalk rejection Parameter Min Typ 0.033 0.4 1 87 Max 0.1 2.5 Unit % LSB dg dB
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TSA1204
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 20Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 20Msps. The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Spurious Free Dynamic Range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao =SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao =6.02 x ENOB + 1.76 dB + 20 log (2A 0/ FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.
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TSA1204
Static parameter: Integral Non Linearity Fs=20MSPS; Icca=40mA; Fin=2MHz
0.8 0.6
INL (LSBs)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 3000 3500 4000
Output Code
Static parameter: Differential Non Linearity Fs=20MSPS; Icca=40mA; Fin=2MHz
0.4 0.3
DNL (LSBs)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 500 1000 1500 2000 2500 3000 3500 4000
Output Code
Linearity vs. Fs Fin=5MHz; Rpol adjustment
100 12
Distortion vs. Fs Fin=5MHz; Rpol adjustment
-20
Dynamic parameters (dBc)
Dynamic parameters (dB)
ENOB Q
90 ENOB I 80 SNR_Q 70 SINAD_Q
11 10 ENOB (bits) 9 8
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 15 20 25 SFDR_Q THD_Q SFDR_I THD_I
60 SNR_I 50 40 10 15 20 25 SINAD_I
7 6 5
Fs (MHz)
Fs (MHz)
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TSA1204
Linearity vs. Fin Fs=20MSPS; Icca=40mA
100 12
Distortion vs. Fin Fs=20MSPS; Icca=40mA
-30
Dynamic parameters (dBc)
Dynamic parameters (dB)
ENOB_Q
ENOB_I
90 80
SNR_Q SINAD_Q
11
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50
THD_I SFDR_Q THD_Q SFDR_I
70 60
SNR_I
9 8
SINAD_I
50 40 30 0
7 6 5
10
20
30
40
50
Fin (MHz)
ENOB (bits)
10
Fin (MHz)
Linearity vs. Temperature Fs=20MSPS; Icca=40mA; Fin=2MHz
100 12 11.5 11
Distortion vs. Temperature Fs=20MSPS; Icca=40mA; Fin=2MHz
120
Dynamic parameters (dBc)
Dynamic parameters (dB)
ENOB_I
90 80 70 60 50 40 -40 10 60
ENOB_Q SNR_I SINAD_I
110 100 90 80 70 60 50 40 -40 10 60
SFDR_I THD_I SFDR_Q THD_Q
10 9.5 9
SNR_Q
SINAD_Q
8.5 8 7.5 7
ENOB (bits)
10.5
Temperature (C)
Temperature (C)
Linearity vs. AVCC Fs=20MSPS; Icca=40mA; Fin=5MHz
100 12
ENOB_Q
Distortion vs. AVCC Fs=20MSPS; Icca=40mA; Fin=5MHz
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 2.25 2.35 2.45 2.55 2.65
THD_Q SFDR_Q THD_I SFDR_I
Dynamic parameters (dB)
95 90 85 80 75 70 65 60 55 50 2.25
11 10
SNR_Q SINAD_Q
9 8
SINAD_I
SNR_I
7 6
2.35
2.45
2.55
2.65
ENOB (bits)
ENOB_I
Dynamic Parameters (dBc)
AVCC (V)
AVCC (V)
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TSA1204
Linearity vs. DVCC Fs=20MSPS; Icca=40mA; Fin=5MHz
100 12
ENOB_Q
Distortion vs. DVCC Fs=20MSPS; Icca=40mA; Fin=5MHz
-40 -50 -60
THD_I SFDR_I
Dynamic parameters (dB)
90
ENOB_I
11 10
SNR_Q SNR_I
80 70 60 50 40 2.25
SINAD_I SINAD_Q
Dynamic Parameters (dBc)
ENOB (bits)
-70 -80 -90 -100 -110 -120 2.25
THD_Q SFDR_Q
9 8 7 6 2.35 2.45 2.55 2.65
2.35
2.45
2.55
2.65
DVCC (V)
DVCC (V)
Linearity vs. VCCBI Fs=20MSPS; Icca=40mA; Fin=5MHz
90 12
ENOB_I
Distortion vs. VCCBI Fs=20MSPS; Icca=40mA; Fin=5MHz
-40 -50 -60 -70 -80 -90 -100 -110 -120 2.25
THD_Q SFDR_Q THD_I SFDR_I
Dynamic parameters (dB)
85 80
11.5 11
ENOB_Q
75 70 65 60 55 50 2.25
SINAD_I SNR_I
SNR_Q
10.5 10 9.5
SINAD_Q
9 8.5 8
Dynamic Parameters (dBc)
ENOB (bits)
2.35
2.45
2.55
2.65
2.35
2.45
2.55
2.65
VCCBI (V)
VCCBI (V)
Linearity vs. VCCBE Fs=20MSPS; Icca=40mA; Fin=5MHz
90 12
ENOB_I
Distortion vs. VCCBE Fs=20MSPS; Icca=40mA; Fin=5MHz
-40 -50 -60
SFDR_Q THD_I
Dynamic parameters (dB)
85 80 75
SNR_I ENOB_Q SINAD_I
11.5 11 10.5 10 9.5 9
Dynamic Parameters (dBc)
ENOB (bits)
-70 -80 -90 -100 -110 -120 2.25
THD_Q SFDR_I
70 65 60 55 50 2.25
SNR_Q
SINAD_Q
8.5 8 7.5 7
2.75
3.25
2.75
3.25
VCCBE (V)
VCCBE (V)
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TSA1204
Linearity vs. Duty Cycle Fs=20MSPS; Icca=40mA; Fin=5MHz
100 12
ENOB_I
Distortion vs. Duty Cycle Fs=20MSPS; Icca=40mA; Fin=5MHz
-40
11.5 11
Dynamic parameters (dBc)
Dynamic parameters (dB)
90 80 70 60
SNR_Q ENOB_Q SNR_I SINAD_I
-50 -60
SFDR_Q
ENOB (bits)
10.5 10 9.5 9
SINAD_Q
-70 -80 -90 -100 -110 -120 45 47
THD_Q
8.5 8 7.5
SFDR_I THD_I
50 40 45 47 49 51 53 55
7
49
51
53
55
Positive Duty Cycle (%)
Positive Duty Cycle (%)
Single-tone 8K FFT at 20Msps - I Channel Fin=5MHz; Icca=40mA, Vin@-1dBFS
0
Power spectrum (dB)
-20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10
Frequency (MHz) Dual-tone 8K FFT at 20Msps - I Channel Fin1=9.7MHz; Fin2=10.7MHz; Icca=40mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-76dBc
0
Power spectrum (dB)
-20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10
Frequency (MHz)
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TSA1204 APPLICATION NOTE
DETAILED INFORMATION The TSA1204 is a dual-channel, 12-bit resolution analog to digital converter based on a pipeline structure and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. Each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled on both channels on the rising edge of the clock. The output data is valid on the rising edge of the clock for I channel and on the falling edge of the clock for Q channel. The digital data out from the different stages must be time delayed depending on their order of conversion. Then a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The structure has been specifically designed to accept differential signals only. COMPLEMENTARY FUNCTIONS Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described as followed. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality. In order to remain in the normal operating mode, this pin should be grounded through a low value of resistor. SELECT The digital data out from each ADC cores are multiplexed together to share the same output bus. This prevents from increasing the number of pins and enables to keep the same package as single channel ADC like TSA1201. The selection of the channel information is done through the "SELECT" pin. When set to high level (VIH), the I channel data are present on the bus D0-D11. When set to low level (VIL), the Q channel data are on the output bus D0-D11. Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D11; I channel on the rising edge of the clock and Q channel on the falling edge of the clock. (see timing diagram page 2). REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pins are connected externally to the Analog Ground while VREFP (respectively INCM) are set to their internal voltage of 0.89V (respectively 0.46V). It is recommended to decouple the VREFP and INCM pins in order to minimize low and high frequency noise (refer to Figure 1) Figure 1 : Internal reference and common mode setting
1.03V
330pF 10nF 4.7uF
VIN
VREFP 0.57V
330pF 10nF 4.7uF
TSA1204
VINB INCM VREFM
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TSA1204
External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (Refer to table' OPERATING CONDITIONS' page 4 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). Using internal VREFP, the dynamic range is 1.8V. The best linearity and distortion performances are achieved with a dynamic range above 2Vpp and by increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. Figure 2 : External reference setting node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1.4Vpp amplitude input signal, so the resultant differential amplitude is 2.8Vpp. Figure 3 : Differential input configuration with transformer
Analog source ADT1-1 1:1 VIN
50 33pF
VINB
TSA1204 I or Q ch.
INCM
330pF
10nF
470nF
1k
330pF 10nF 4.7uF
Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. Figure 4 : AC-coupled differential input
VCCA VREFP VIN
TSA1204
VINB VREFM
TS821 TS4041 external reference
50 common mode 10nF 100k 33pF 100k 10nF
VIN INCM
TSA1204
VINB
DRIVING THE DIFFERENTIAL ANALOG INPUTS The TSA1204 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. As being an high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this
50
Figure 5 shows a DC-coupled configuration with forced VREFP and INCM to the 1V DC analog input while VREFM is connected to ground; we achieve a 2Vpp differential amplitude.
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TSA1204
Figure 5 : DC-coupled 2Vpp differential analog input
analog DC analog DC
330pF 10nF
VREFP-VREFM = 1 V 4.7uF
Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is mandatory to prevent noise from coupling onto the input signal. The best compromise is to connect from one part AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the power supplies AVCC, DVCC and VCCBI must be separated from the VCCBE one. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). APPLICATION Digital Interface application Thanks to its wide external buffer power supply range, the TSA1204 is perfectly suitable to plug in to 2.5V low voltage DSPs or digital interfaces as well as to 3.3V ones. Medical Imaging application Driven by the demand of the applications requiring nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs. As a typical system diagram shows figure 7, a narrow input beam of acoustic energy is sent into a living body via the transducer and the energy reflected back is analyzed.
AC+DC VIN
VREFP
TSA1204
VINB
VREFM
INCM
Clock input The TSA1204 performance is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption So as to optimize both performance and power consumption of the TSA1204 according the sampling frequency, a resistor is placed between IPOL and the analog Ground pins. Therefore, the total dissipation is adjustable from 10Msps up to 20Msps. The TSA1204 will combine highest performances and lowest consumption at 20Msps when Rpol is equal to 54k. At lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. The table below sums up the relevant data. Figure 6 : Total power consumption optimization depending on Rpol value
Fs (Msps) Rpol (k) Optimized power (mW) 10 120 95 20 54 120
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TSA1204
Figure 7 : Medical imaging application noise and very high linearity are mandatory factors. These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues. The input signal is in the range of 2 to 20MHz (mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization. The next RX beam former and processing blocks enable the analysis of the outputs channels versus the input beam. EVAL1204/BA evaluation board The EVAL1204/BA is a 4 layer board with high decoupling and grounding level. The schematic of the evaluation board is reported figure 11 and its top overlay view figure 10. The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 8. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=1dB for static parameters.
HV TX amps TX beam former
Mux and T/R switches TGC amplifier
ADC
RX beam former
Processing and display
The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver. To compensate for skin and tissues attenuation effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the amplification of low voltage signals to the ADC input range. Differential output structure with low
Figure 8 : Analog to Digital Converter characterization bench
HP8644 Sine Wave Generator Vin ADC evaluation board
Data Logic Analyzer Clk Clk HP8133 Pulse Generator PC
HP8644
Sine Wave Generator
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TSA1204
Operating conditions of the evaluation board: Find below the connections to the board for the power supplies and other pins:
board notation AV AG RPI RMI CMI RPQ RMQ CMQ DV DG GB1 VB1 GB2 VB2 GB3 VB3 connection AVCC AGND REFPI REFMI INCMI REFPQ REFMQ INCMQ DVCC DGND GNDBI VCCBI GNDBE VCCBE GNDB3 VCCB3
0.46 0.46 0.89 0.89 internal voltage (V) external voltage (V) 2.5 0 <1.4 <0.4 <1 <1.4 <0.4 <1 2.5 0 0 2.5 0 1.8/2.5/3.3 0
Grounding consideration So as to better reject noise on the board, connect on the bottom overlay AG (AGND), DG(DGND), GB1(GNDBI) together from one part, and GB2(GNDBE) with GB3(GNDB3) from the other part. Mode select So as to evaluate a single channel or the dual ones, you have to connect on the board the relevant position for the SELECT pin. With the strap connected - to the upper connectors, the I channel at the output is selected. - horizontally, the Q channel at the output is selected - to the lower connectors, both channels are selected, relative to the clock edge. Figure 9 : mode select
SELECT
I channel SELECT Q channel I/Q channels
CLK DGND DVCC
2.5
Care should be taken for the evaluation board as the outputs of the converter are 2.5V/3.3V (VCCB2) tolerant whereas the 74LCX573 external buffers are operating up to 2.5V. Single and Differential Inputs: The ADC board components are mounted to test the TSA1204 with single analog input; the ADT1-1WT transformer enables the differential drive into the converter; in this configuration, the resistors RSI6, RSI7, RSI8 for I channel (respectively RSQ6, RSQ7, RSQ8 for Q one) are connected as short circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9) are open circuits. The other way is to test it via JI1 and JI1B differential inputs. So, the resistances RSI5, RSI9 for I channel (respectively RSQ5, RSQ9 for Q one) are connected as short circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q one) are open circuits.
schematic Consumption adjustment
board
Before any characterization, care should be taken to adjust the Rpol (Raj1) and therefore Ipol value in function of your sampling frequency.
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TSA1204
Figure 10 : Printed circuit of evaluation board.
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REFP REFM INCM
JI2 VREFI VCCB1 VCCB2 VCCB3 VCCB1 VCCB2 Switch S4 Open Short OEB Mode Normal mode High Impedance output mode R12 S4 SW-SPST R11 47K STG719 VCCB1 C44 47F
+
GndB1 VccB1 GndB2 VccB2 GndB3 VccB3
48 47 46 45 44 43 42 41 40 39 38 37
REFPI REFMI INCMI AVCC AVCC OEB VCCBI VCCBI GNDBE VCCBE D0(LSB) D1
REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI
13 14 15 16 17 18 19 20 21 22 23 24
REFP REFM INCM
C32 47F
+
VCC GND
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J17 BUFPOW analog input with transformer (default) single input differential input RS5 RS6 RS7 RS8 RS9 C C C C C C C 47K S5 SW-SPST J26 2 1 R5 50 Switch S5 Open Short Normal mode Test mode CON2 VCCB2 U1 J25 CKDATA IN S2 Vcc D GNDS1 C28 VCCB2 C16 470nF AVCC C53 470nF C34 47F VCCB3
+
TSA1204
NM: non soude
R21
R22
R23
R24
0NM
0NM
0NM
0NM
C43 10F J6 470nF C27 C37 C39 C51 330pF 10nF 330pF 470nF DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CLK 74LCX573 C38 C18 10nF C40 CD3 330pF C35
+
RSI5 C15 10nF C14 330pF C52 10nF
RI1 50 CI8 330pF C26 CI13 330pF 470nF 10nF 330pF 470nF 10nF 330pF CI12 CI11 CI32 CI31 CI30
RSI6 1 0 10nF C25
0 NC TI2 6
RSI7
2
0
D0 GND D1 GND D2 GND D3 GND D4 GND D5 GND D6 GND D7 GND D8 GND D9 GND D10 GND D11 GND CLK GND
3
4 RSI8 T2-AT1-1WT 0
CI10
CI9
JI1B InIB J9 CI6 NM R2 C2 Raj1 47K ADC DUAL12B 330pF 1K 8-14bits ADC 74LCX573
470nF 10nF
RSI9
RI19 50
0 NC
CI1
Figure 11 : TSA1204 Evaluation board schematic
33pF
1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE
20 19 18 17 16 15 14 13 12 11
AVCC
JA
C41
C3
C4
VCC GND
+
C42 47F 10F
470nF 10nF
ANALOGIC
1 2 3 4 5 6 7 8 9 10 11 12 AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND D2 D3 D4 D5 D6 D7 D8 D9 D10 D11(MSB) VCCBE GNDBE
36 35 34 33 32 31 30 29 28 27 26 25
RSQ5 CQ6 C29 10F
+
1 Q NM DVcc C17 330pF CQ13 CD1 470nF CD2 10nF CQ8 470nF 10nF 330pF 470nF 10nF 330pF C19 470nF 330pF CQ32 CQ31 CQ30 CQ12 CQ11
CQ1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11
RQ1 50
RSQ61 0
0 NC RSQ7 TQ2 6 0 2
33pF
3
4 RSQ8 T2-AT1-1WT 0
470nF 10nF C33 330pF
CQ10
CQ9
JQ1B InQB
RSQ9
470nF 10nF
RQ19 50 C20 330pF SW1 C10 330pF C21 10nF DVCC C11 10nF J27 2 1 CON2 C31 10F C36 47F
+
0 NC 47F VCCB2
C22 470nF C23 10F JQ2 VREFQ AVCC C13 470nF C5
DVCC
100nF J4 50 CLK DIGITAL JD
R3
TSA1204
Figure 12 : Printed circuit board - List of components
Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC 0NC R24 0NC R23 R21 0NC R22 0NC 1K R2 47K R12 47K R11 Raj1 200K C23 C41 C29 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 trimmer CQ11 330pF 10F 1210 CI8 330pF 10F 1210 C14 330pF 10F 1210 CI30 330pF Footprint 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 Name C26 C20 C33 C25 CI1 CQ1 C34 C42 C35 C44 C36 C32 C37 CQ10 C28 CI10 CQ32 CQ13 CI32 C13 C53 C16 C3 C22 CI13 C38 CD1 C19 Part Type 330pF 330pF 330pF 330pF 33pF 33pF 47F 47F 47F 47F 47F 47F 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 connector 805 805 805 NC: non soldered 805
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TSA1204
PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
12 13 24
25
E3 E1 E
D3 D1 D
L1
L
K
Millimeters Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20
0,25 mm .010 inch GAGE PLANE
Min. 0.002 0.053 0.007 0.004
B
c
Inches Typ. Max. 0.063 0.006 0.057 0.011 0.008 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.45 0.75 0.018
0.030
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com
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