 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TC55NEM208AFPN/AFTN55,70 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 A standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range of -40 to 85C, the TC55NEM208AFPN/AFTN can be used in environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin thin-small-outline package (TSOP). FEATURES * * * * * * * Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 5 V 10% Power down features using CE . Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum):20 A * Access Times (maximum): TC55NEM208AFPN/AFTN 55 Access Time 55 ns 55 ns 30 ns 70 70 ns 70 ns 35 ns CE Access Time OE Access Time * Package: SOP32-P-525-1.27 (AFPN) (Weight: TSOP II32-P-400-1.27 (AFTN) (Weight: g typ) g typ) PIN ASSIGNMENT (TOP VIEW) 32 PIN SOP & TSOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 A17 R/W A13 A8 A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 PIN NAMES A0~A18 R/W Address Inputs Read/Write Control OE CE I/O1~I/O8 VDD GND Output Enable Chip Enable Data Inputs/Outputs Power (+5 V) Ground (AFPN/AFTN) 2002-09-18 1/10 TC55NEM208AFPN/AFTN55,70 BLOCK DIAGRAM CE A4 A5 A6 A7 A8 A9 A11 A14 A15 A16 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER VDD GND MEMORY CELL ARRAY 2,048 x 256 x 8 (4,194,304) 8 DATA CONTROL SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A10 A12A13 A17 OE R/W CE CE OPERATING MODE MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low CE L L L H OE L * R/W H L H * I/O1~I/O8 Output Input High-Z High-Z POWER IDDO IDDO IDDO IDDS H * MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~7.0 -0.3*~7.0 -0.5~VDD + 0.5 UNIT V V V W C C C 0.6 260 -55~150 -40~85 *: -2.0 V when measured at a pulse width of 20ns 2002-09-18 2/10 TC55NEM208AFPN/AFTN55,70 DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C) SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage MIN 4.5 2.2 -0.3* TYP 5.0 MAX 5.5 VDD + 0.3 0.6 5.5 UNIT V V V V 2.0 *: -2.0 V when measured at a pulse width of 20 ns DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 5 V 10%) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = 2.4 V VOL = 0.4 V TEST CONDITION MIN -1.0 TYP MAX 1.0 1.0 UNIT A mA mA A 2.1 CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL CE = 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V CE = VIH Ta = 25C MIN 1 s tcycle MIN 1 s 35 mA lDDO1 Operating Current lDDO2 8 30 mA 3 IDDS1 Standby Current IDDS2 3 mA 1 CE = VDD - 0.2 V, VDD = 2.0 V~5.5 V Ta = -40~40C Ta = -40~85C 3 20 A CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2002-09-18 3/10 TC55NEM208AFPN/AFTN55,70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40 to 85C, VDD = 5 V 10%) READ CYCLE TC55NEM208AFPN/AFTN SYMBOL PARAMETER MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 55 55 MAX 70 MIN 70 UNIT MAX 55 55 30 70 70 35 5 0 5 0 ns 25 25 30 30 10 10 WRITE CYCLE TC55NEM208AFPN/AFTN SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 40 45 0 0 55 MAX 70 MIN 70 50 55 0 0 UNIT MAX ns 25 30 0 25 0 0 30 0 AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF TEST CONDITION 100 pF + 1 TTL Gate 0.4 V, 2.4 V 1.5 V 1.5 V 5 ns 2002-09-18 4/10 TC55NEM208AFPN/AFTN55,70 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address A0~A18 tACC tCO tOH CE tOE tOD OE tOEE tCOE DOUT I/O1~8 Hi-Z VALID DATA OUT tODO Hi-Z WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW tWP tWR CE tODW DOUT I/O1~8 (See Note 2) Hi-Z tDS DIN I/O1~8 (See Note 5) tDH (See Note 5) tOEW (See Note 3) VALID DATA IN 2002-09-18 5/10 TC55NEM208AFPN/AFTN55,70 WRITE CYCLE 2 (CE CONTROLLED) (See Note 4) tWC Address A0~A18 tAS R/W tCW tWP tWR CE tCOE DOUT I/O1~8 Hi-Z tDS DIN I/O1~8 (See Note 5) tDH (See Note 5) tODW Hi-Z VALID DATA IN Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2002-09-18 6/10 TC55NEM208AFPN/AFTN55,70 DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C) SYMBOL VDH IDDS2 tCDR tR PARAMETER Data Retention Supply Voltage Ta = -40~40C Standby Current Ta = -40~85C MIN 2.0 TYP MAX 5.5 3 20 UNIT V A Chip Deselect to Data Retention Mode Time Recovery Time 0 5 ns ms CE CONTROLLED DATA RETENTION MODE VDD DATA RETENTION MODE 4.5 V (See Note) VIH tCDR VDD - 0.2 V (See Note) tR CE GND Note: When CE is operating at the VIH level (2.2V), the standby current is given by IDDS1 during the transition of VDD from 4.5 to 2.4V. 2002-09-18 7/10 TC55NEM208AFPN/AFTN55,70 PACKAGE DIMENSIONS Weight: g (typ) 2002-09-18 8/10 TC55NEM208AFPN/AFTN55,70 PACKAGE DIMENSIONS Weight: g (typ) 2002-09-18 9/10 TC55NEM208AFPN/AFTN55,70 RESTRICTIONS ON PRODUCT USE 000707EBA * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2002-09-18 10/10 |
Price & Availability of TC55NEM208AFTN70
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |