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 STP55NF03L
N-CHANNEL 30V - 0.01 - 55A TO-220 STripFETTM POWER MOSFET
TYPE STP55NF03L
s s
VDSS 30 V
RDS(on) <0.013
ID 55 A
s s
TYPICAL RDS(on) = 0.01 OPTIMIMIZED FOR HIGH SWITCHING OPERATIONS LOW GATE CHARGE LOGIC LEVEL GATE DRIVE
1 2
3
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM " strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
TO-220
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s LOW VOLTAGE DC-DC CONVERTERS s HIGH CURRENT, HIGH SPEED SWITCHING s HIGH EFFICIENCY SWITCHING CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR VGS ID ID IDM(*) Ptot Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Storage Temperature Max. Operating Junction Temperature Value 30 30 15 55 39 220 80 0.53 -60 to 175 175 Unit V V V A A A W W/C C C
(*)Pulse width limited by safe operating area.
February 2001
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STP55NF03L
THERMAL DATA
R thj-case R thj-amb Rthc-sink Tj Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead Temperature For Soldering Purpose Max Max Typ 1.875 62.5 0.5 300 C/W C/W C/W C
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (V GS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A VGS = 0 Min. 30 1 10 100 Typ. Max. Unit V A A nA
VDS = Max Rating VDS = Max Rating TC = 125 C VGS = 15 V
ON (*)
Symbol VGS(th) R DS(on) ID(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance On State Drain Current Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 27.5 A ID = 27.5 A 55 Min. 1 0.01 0.013 0.013 0.020 Typ. Max. Unit V A
VDS > ID(on) x RDS(on)max VGS = 10 V
DYNAMIC
Symbol gfs
(*)
Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitances
Test Conditions VDS>ID(on) x RDS(on)max ID=27.5 A VDS = 25V f = 1 MHz VGS = 0
Min.
Typ. 30 1265 435 115
Max.
Unit S pF pF pF
C iss Coss Crss
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STP55NF03L
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Q gd Parameter Test Conditions Min. Typ. 28 400 20 7 10 27 Max. Unit ns ns nC nC nC Turn-on Delay Time Rise Time VDD = 15 V I D = 27.5 A VGS = 4.5 V RG = 4.7 (see test circuit, Figure 3) Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=24V I D=55A VGS=4.5V
SWITCHING OFF
Symbol td(off) tf Parameter turn-off Delay Time Fall Time Test Conditions VDD = 15 V ID = 27.5 A VGS = 4.5 V RG = 4.7 (see test circuit, Figure 3) Min. Typ. 25 50 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 55 A VGS = 0 70 160 4.5 Test Conditions Min. Typ. Max. 55 220 1.3 Unit A A V ns nC A
IRRM
di/dt = 100 A/s ISD = 55 A Tj = 150 C VDD = 30 V (see test circuit, Figure 5)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limit ed by safe operating area.
Safe Operating Area
Thermal Impedance
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STP55NF03L
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STP55NF03L
Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
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STP55NF03L
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STP55NF03L
TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147
E
mm TYP. MAX. 4.60 1.32 2.72 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 MIN. 0.173 0.048 0.094 4.40 1.23 2.40
inch TYP. MAX. 0.181 0.051 0.107 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 0.645 0.551 0.116 0.620 0.260 0.154 0.151
A
C
D1
L2 F1
D
G1
Dia. F2 F
L5 L7 L6
L9
L4
G
H2
P011C
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STP55NF03L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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