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ST7554
V.90 USB WORLD MODEM CONTROLLER
SUMMARY DATA
. . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL USB HOT PLUG & PLAY INTERFACE DIRECT INTERFACE TO ST MAFE+DAA CHIP-SET ST75951/ST952 FOR WORLDWIDE DAA DESIGN OR TO STLC7550 FOR TRADITIONAL DAA DESIGN WINDOWS(R) 98 AND NT 5.0 SUPPORT TAPI 2.0 COMPLIANT SOFTWARE UPGRADABLE MINIMUM SYSTEM REQUIREMENTS: USB MOTHERBOARD, 166MHz PENTIUM(R) PROCESSOR WITH MMXTM TECHNOLOGY, WINDOWS(R) 98 AND 16MBYTES RAM OR WINDOWS(R) NT 5.0 AND 32MBYTES RAM DEVICE FEATURES SINGLE 9.216MHz CRYSTAL OSCILLATOR INTEGRATED ANALOG AND DIGITAL 3.3V REGULATORS DEDICATED PINS FOR RING, OFF-HOOK, CLID, LOOP CURRENT SENSE 0.5m CMOS PROCESS TQFP48 (7 x 7 mm) PACKAGE DATA MODEM / FAX / VOICE V.90 V.34BIS, V.34, V.32BIS, V.32, V.22BIS, V.22, V.23, V.21 BELL 103 AND BELL 212A V.17, V.27TER, V.29, FAX CLASS 1 SUPPORT V.42, V.42BIS, MNP 2, 3, 4, 5 V.80 V.8 AND AUTO MODE VOICE / FAX / MODEM DISTINCTION ADPCM VOICE COMPRESSION/DECOMPRESSION VOICE DETECTION (SILENCE DETECTION) OTHER FEATURES VIRTUAL UART (460.8Kbps) AT HAYES COMMAND COMPATIBLE TIME INDEPENDENT ESCAPE SEQUENCE (TIES) COMMAND CALLER ID
TQFP48 (7 x 7 x 1.40mm) (Full Plastic Quad Flat Pack) ORDER CODE : ST7554TQF7
. . . . . . . . .
DTMF DETECTION AND GENERATION WAKE UP ON RING WORLD-WIDE PROGRAMMABLE SILICON DAA SUPPORT FOR ST75951/ST952 MAFE+DAA CHIP-SET
UNIVERSAL SERIAL BUS SPECIFICATION 1.0, 12MBps FULL SPEED ON-CHIP USB TRANSCEIVER WITH DIGITAL PLL COMMUNICATION DEVICE CLASS AND VENDOR REQUESTS BUS OR SELF POWERED APPLICATION (PIN-PROGRAMMABLE) ONNOW POWER MANAGEMENT (D0, D2, D3) LOW POWER CONSUMPTION (SUSPEND MODE D2), WHOLE APPLICATION BELOW 500A DESCRIPTION The ST7554 is a single chip host signal processing Modem/fax/voice controller that supports data rates up to 56Kbps. All data pump and protocol functions are executed on the host PC's processor. This product has been developed in cooperation with Smart Link Ltd, who ported "USB-Modio", its host based Modem and system software into ST system and hardware platform. The ST7554 directly connects to ST high performance Modem analog frontend (MAFE) STLC7550 or to the highly integrated MAFE+DAA chip-set ST75951/ST952. The ST7554 also features an Universal Serial Bus (USB) interface for direct connection to the host PC for maximum flexibility and real plug & play operation.
1/11
January 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RESERVED
36
35
34
33
32
31
30
29
28
27
26
25
RESERVED
DAASEL
PDOWN
DGND
DOUT
MCLK
TRxD
HC1
DIN
DC
FS
BUZEN PULSE DISHS RFC LED CD CLID RESERVED HO 45 46 47 48 HSDT RESERVED RI 44 43 42 41 40 39 38
37
24 23 22 21 20 19 18 17 16 15 14 13
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
10
11
GNDBUS
PSM
PIN CONNECTIONS
ST7554
XTALOUT
FLTPLL
VREGD
XTALIN
VREGA
RESET
D+
D-
AGND
VBUS
12
1
2
3
4
5
6
7
8
9
2/11
7554S-01.EPS
ST7554
PIN LIST
Name XTALIN XTALOUT RESET VBUS GNDBUS VREGA VREGD PSM D+ DTRxD DC BUZEN PULSE DISHS RFC LED CD CLID HO HSDT RI HC1 PDOWN MCLK DAASEL FS DOUT DIN FLTPLL DGND AGND RESERVED RESERVED Pin 9 10 12 5 3 6 4 8 2 1 35 36 37 38 39 40 41 42 43 45 46 48 27 26 29 34 28 31 30 11 32 7 13 to 25-33-44 47 Type I O I I I I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I O I OA I I Crystal Input Crystal Output Reset Function to initialise the device (active low) Positive Voltage Regulator Input, connected to USB VBUS Regulator Ground, connected to USB Ground (0V) (see Note 1) Positive Regulated Analog Input/Output Power Supply Positive Regulated Digital Input/Output Power Supply Power Supply Mode (Bus-powered or Self-powered) Positive Data Signal of Differential Data Bus conforming to USB Standard Specification 1.0 Negative Data Signal of Differential Data Bus conforming to USB Standard Specification 1.0 Transmit/Receive Data Led DC mask Buzzer Amplifier Enable/Mute Pulse dialing Disconnect external phone Refresh LED control Carrier Detect Led Caller ID Hook Control Current sense Ring Indicator Modem Codec Hardware Control mode selection SSI Powerdown bit output (active low) SSI Master Clock Output Select Silicon or Discrete DAA Configuration Mode SSI Frame Synchronisation Input SSI Serial Data Output SSI Serial Data Input PLL filter analog output. Must be connected to analog ground AGND with 33pF capacitor Digital Ground (0V) (see Note 1) Analog Ground (0V) (see Note 1) Not connected Connect to digital ground DGND
7554S-01.TBL
Description
Note 1 : Analog and digital ground pins must be tied together to USB ground GNDBUS.
3/11
ST7554
PIN DESCRIPTION 1 - Power Supply (7 pins) 1.1 - Regulator Input Power Supply (VBUS) This pin must be connected to USB VBUS (+5V). It supplies the integrated analog USB transceiver. It is also the positive regulator power supply input (5V) when ST7554 is in bus-powered mode (PSM = 1) and it is used to internally generate the 3.3V supply for the digital and analog circuitry. 1.2 - Regulated Analog VDD Supply (VREGA) This pin is the analog power supply input (PSM = 0) or analog 3.3V power supply output (PSM = 1). This pin is the positive analog power supply for the external Codec and DAA. It is recommended to add a 1F capacitor between VREGA and GNDA as close as possible to the IC pins. 1.3 - Regulated VDD Supply (VREGD) This pin is the digital power supply input (PSM = 0) or digital 3.3V power supply output (PSM = 1). This pin is the positive digital power supply for the external Codec and DAA. It is recommended to add a 1F capacitor between VREGA and GNDA as close as possible to the IC pins. 1.4 - Power Supply Mode (PSM) This pin controls the VREGD and VREGA power supply mode. When PSM = 1, the application is bus-powered. The 3.3V power supply is generated internally from VBUS. In this case VREGD and VREGA are outputs which can be used to supply 3.3V to external devices (see Figure 1). When PSM = 0, the application is self-powered. VBUS must be still connected to the VBUS Pin of the USB connector in order to supply the integrated USB transceiver. Anyway in this case VREGD and VREGA must be fed by a 3.3V externally regulated digital and analog power supplies (see Figure 2). 1.5 - Ground (DGND, AGND and GNDBUS) DGND, AGND and GNDBUS are the digital, analog and USB ground return pins respectively. They should be connected together outside the chip to the GND pin of the USB plug. Figure 1 : ST7554 in Bus-Powered mode (PSM = 1)
ST7554
8 PSM 5 VBUS from USB 3 GNDBUS 4 VREGD to other digital ICs 32 DGND 6 VREGA
7554S-02.EPS 7554S-03.EPS
to other analog ICs 7 AGND
Figure 2 :
ST7554 in Self Powered mode (PSM = 0)
ST7554
8 PSM 5 VBUS from USB 3 GNDBUS 4 VREGD from 3.3V externally regulated supplies
32 DGND 6 VREGA
7 AGND
2 - USB Interface (D+ , D-) These pins are the positive and negative USB differential data lines. They shall be both connected to the USB plug or USB protection circuit via 27 series resistors for line impedance matching.
4/11
ST7554
PIN DESCRIPTION (continued) 3 - Reset, Powerdown (RESET, PDOWN) RESET Pin initialises the internal counters and control registers to their default value. A minimum low pulse of 1ms is required to reset the chip. In a typical application RESET is connected to VBUS through a R, C network. This ensures that the chip is reset at each connection / disconnection to the USB bus (see Figure 3). PDOWN Pin shall be connected to the powerdown inputs of the external codec used on the SSI. When ST7554 is in Suspend mode, PDOWN is forced low so that the external codec is in powerdown. Figure 3 : RC network for RESET
VBUS
based on ST75951 + ST952. Connect to DGND when using STLC7550 with discrete interface. 5 - DAA Control Pins (IMP, DC, BUZEN, PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI) These pins control the World Wide software programmable DAA through ST75951/ST952. 6 - Crystal (XTALIN, XTALOUT) These pins must be tied to the 9.216MHz external crystal. It is recommended to use a 50ppm fundamental parallel resonator crystal. It is recommended to insert a 1.8k resistor between XTALOUT and the crystal to limit its energy to 100W for a 20 resonator (see Figure 4). For a SMD crystal the load capacitor is typically CLOAD = 12pF and this leads to an ideal value of C = 24pF for the capacitors between the crystal and analog ground (AGND). Anyway, in practice these capacitors shall be reduced down to C = 18pF each by considering parasitic capacitors on PCB and package (see Figure 4). After a reset or when leaving the suspend state, the 9.216MHz is asserted inside ST7554 only 3.5ms later in order to wait for it to be stable. Figure 4 : Application schematic for the 9.216MHz external crystal
XTAL IN 9 XTAL OUT 10 R 1.8kW
R 220kW 12 RESET C 10nF
7554S-04.EPS
4 - Serial Synchronous Interface ST7554 has a Serial Syncronous Interface (SSI) dedicated to the connection of the STLC7550 or ST75951, ST high performance Modem Analog Front-End (MAFE). 4.1 - Data (DIN, DOUT) Digital data word input/output of SSI, to be connected to the data word pins of STLC7550 or ST75951. 4.2 - Master Clock (MCLK) This pin is the master clock output. 4.3 - Frame Synchronization (FS) The frame synchronization is used to synchronize data transfer between ST7554 and the external Codec. 4.4 - Hardware Control (HC1) HC1 must be connected to the corresponding pin of STLC7550 or ST75951, while their HC0 Pin shall be tied to the 3.3V VREGD digital supply. This pin selects data or control modes for the Modem Codec. 4.5 - DAA Selection (DAASEL) Connect to VREGD when using silicon DAA chipset
AGND
AGND
7 - PLL Output Filter (FLTPLL) This pin must be connected to the analog ground (AGND) through a 33pF capacitor. 8 - Reserved Pins (18 pins) These pins must be left not connected except Pin 47 which should be connected to the digital ground DGND.
5/11
7554S-05.EPS
C 18pF
C 18pF
ST7554
ELECTRICAL SPECIFICATIONS Unless otherwise stated, electrical characteristics are specified over the operating range. Typical values are given for VBUS = +5V, VREGA = 3.3V, VREGD = 3.3V, Tamb = 25C. Absolute Maximum Rating (AGND = DGND = USB GND = 0V, all voltages with respect to 0V)
Symbol DVDD II IO VIA VID Toper Tstg Ptot Digital Power Supply Input Current per Pin Output Current per Pin Analog Input Voltage Digital Input Voltage Operating Temperature Storage Temperature Maximum Power Dissipation Parameter Value -0.3, 6.0 -10, +10 -20, +20 -0.3, AVDD + 0.3 -0.3, DVDD + 0.3 0, +70 -55, +150 200 Unit V mA mA V V C C mW
Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes.
Nominal DC Characteristics (Tamb = 0 to 70C unless otherwise specified)
Symbol VBUS IVBUS IVBUSS VREGA VREGD IVREGA IVREGD PDLP PD PD VIH VIL VOH VOL ILEAK IOL IOH VHYST CIN VIH VIL ILEAK VHYST VIH VIL IIH IIL 6/11 Parameter Supply Voltage Supply Current Supply Current in Suspend Mode (PSM = 1) Analog regulated Output Power Supply (PSM =1) Analog regulated Input Power Supply (PSM =0) Digital regulated Output Power Supply (PSM =1) Digital regulated Input Power Supply (PSM =0) Analog regulated Output Current (PSM =1) Analog regulated Input Current (PSM =0) Digital regulated Output Current (PSM =1) Digital regulated Input Current (PSM =0) Low Power Mode (Suspend mode D2, wake-up on ring enabled) Operating Power (SSI in power-down) Operating Power (D0 power state) High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Level Output Current (0 < VOL < VOLMax.) Low Level Output Current (VOHMin. < VOH < VREGD) Schmitt Trigger Hysteresis Input Capacitance High Level Input Voltage Low Level Input Voltage Input Leakage Current Schmitt Trigger Hysteresis High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Min. 4 Typ. 5 TBD TBD 3.4 3.3 3.4 3.3 TBD 20 20 TBD TBD TBD 0.8 x VREGD 0.2 x VREGD 0.85 x VREGD 0.4 1 2 -2 0.8 3 0.7 x VBUS 0.3 x VBUS 1 1 1.3 0.8 x VREGA 0.2 x VREGA 20 -20 Max. 5.25 Unit V mA A V V V V mA mA mA mA mW mW mW V V V V A mA mA V pF V V A V V V A A POWER SUPPLY AND COMMON MODE VOLTAGE
3.4-10% 3.3-10% 3.4-10% 3.3-10%
3.4+10% 3.3+10% 3.4+10% 3.3+10% 40
DIGITAL INTERFACE (except XTALIN, XTALOUT, PSM and RESET) (these inputs have hysteresis)
PSM, RESET (these inputs have hysteresis)
CRYSTAL OSCILLATOR (XTALIN, XTALOUT)
ST7554
UNIVERSAL SERIAL BUS INTERFACE (see Chapter 7 of USB rev 1.0 for complete Electrical Specification) Nominal DC Characteristics (D+, D-)
Symbol VDI VCM VSE VOH VOL ILO CIN RD (2)
Note 2 :
Parameter Differential Input Sensitivity [(D+) - (D-)] Differential Common Mode Range Single Ended Receiver Threshold High Level Output Static Voltage (RL of 15k to GND) Low Level Output Static Voltage (RL of 1.5k to 3.6V) Hi-Z State Data Line Leakage Current (0V < VIN < 3.3V) Transceiver Capacitance (Pin to GND) Driver Output Resistance (steady state drive)
Min. 0.2 0.8 0.8 2.8
Typ.
Max. 2.5 2 3.6 0.3 10 20
Unit V V V V V A pF
TBD
TBD
Excludes external resistor. In order to comply with USB Specifications 1.0, external series resistors of 27 1% each on D+ and Dare recommended
AC Characteristics (D+, D-) (see Figure 5 for test scheme)
Symbol tDR tR tF VCRS Parameter Average bit rate (12 M/s 0.05%) Rise Time between 10% and 90% (see Figure 6) Fall Time 10% and 90% (see Figure 6) Output Signal Crossover Voltage Min. 11.97 4 4 1.3 Typ. Max. 12.03 20 20 2 Unit Mbps ns ns V
Figure 5 : Test Scheme for D+/DVREGD
Figure 6 : Rise and Fall Time Measures
1.5kW 27W D+ 2 Test 27W D1
Test
tR 90% 90%
tF
7554S-06.EPS
7/11
7554S-07.EPS
50pF
15kW
50pF
15kW
10%
10%
ST7554
TYPICAL APPLICATIONS Figure 7 : ST7554 Typical Application Diagram with ST75951/ST952
USB ST7554 ST75951 ST952 POTS
7554S-08.EPS
Figure 8 : ST7554 Typical Application Diagram with STLC7550
USB ST7554 STLC7550 DAA POTS
7554S-09.EPS
8/11
AVDD D4 R17 C31 C15 DVDD C26 C27 C30 C14 R18
Note : This is an example schematic. Details may change without notice. Refer to ST USB Dongle Modem documentation.
USB6
10 L3 VBUS R19 DC29 D+ C28 GNDBUS DGND 32 AGND 7 L4 GND 3 R20 4 U5 2 3 6 3 1 2 7 2 5 1 8 1 6 12 4 8
USB Plug
PSM
VREGA
VREGD
RESET
R19 41 LED LED 10 XTALOUT C12 9 XTALIN R14 K1 IC1 C11 R16
FLTPLL
ST7554
5
4 U4
RESERVED
RESERVED
RESERVED
CLID
PDOWN
DAASEL
DOUT
MCLK
HC1
C13
DIN RI
HO
FS
TYPICAL APPLICATIONS (continued)
R15 DVDD 14 U1 43 10 42 7 8 2 3 11 9 16 4 44
29
28
26
27
34
17
18
47
31
30
43
45
48
R0
FS
TS
HM
GPI
M/S
L1 C5 Q1 8 D2 31 GPIO0 20 R5 U2 24 GAIN GPIO1 19 D3 Q2 D4 U3 D5 D6 5 26 D6 4 27 D5 2 30 D4 11 OHC 1 31 D3 GPIO2 18 34 D2 DOUT 47 R4 LIM1 23 LINI D1 30 35 D1 DIN 46
C3
IC3 ST952
HC0 HC1 MCM SCLK RESET XTALIN XTALOUT PWRDWN
Line Plug
T1
R2
B1
L2
R1
R3
Q3
R9 10 COM 17 TER1 9 16 TER2 3 RIN IDC
Figure 9 : ST7554 Schematic Diagram with ST75951/ST952
C4
IC2 ST75951
GPIO3 17 RING 15 TSTA1 28 TSTA2 33 AUXIN 41 TSTD1 45
Q4
Q5
D1
AGND1
AGND2
DGND
VREFP
VREFN
DVDD
AVDD
VCM
VCMS
VCMP
C9 R10 22 IDI D2 R11 21 IDG C10 AIN 26 19 VDR 15 VDREF 14 IREF 18 SET 25 LCOM C7 32 LCOM 6 TOFF AGND R8 C8 C20 C21 C18 C19 C17 C16 AOUT 27 23 38 22 32 39
20 LINE
29 G2 G1 C22
21
40
6
5
R6
C24
R12
R7
C23
C25
DVDD
C6
ST7554
9/11
7554S-10.EPS
10/11
DVDD AVDD L1 R3 C25 C7 C2 C3 C6 C5 C23 C24 L4 R2
ST7554
Note : This is an example schematic. Details may change without notice. Refer to ST USB Dongle Modem documentation.
USB6
R10 41 LED VBUS R6 DC12 D+ C13 GNDBUS DGND 32 AGND 7 G1 G2 L3 GND 3 2 R7 3 4 U1 6 1 2 7 D1 10 XTALOUT C21 9 XTALIN IC1 48 RI 45 HO K1 C22 R9 10 L2 5 1 8 6 12 4 8
USB Plug
1 2 3
PSM
VREGA
VREGD
RESET
FLTPLL
D2
D4
DVDD
R14
R32
ST7554
6
5
4 U4
TYPICAL APPLICATIONS (continued)
D5
3
C27
DAASEL
PDOWN
5
DOUT
HC1
RESERVED
RESERVED
RESERVED
MCLK
4
DIN
FS
8 R11 AGND C1 R1 12 U3 8 9 3 4 17 15 43 7 42 R15 13 C30 14 R8 44 45 29 28 26 27 34 17 18 47 31 30 R19
R12
T2
1
7
2
L5
FS
TS
DIN
HC1
MCM
SCLK
DOUT
R21 R13 R18 6 7 R23 R16 39 OUT+ C35 40 OUTR28 30 IN21 R33 R26 9 U3 10 R27 R4 AGND C4 C11 AGND C10 C16 C14 8 C15 C8 R31 C37 R29 2 R24 C38 C17 C9 29 IN+ 5 C32 VCM 3 1 U3 U3 R17 C39
TSTD1
XTALIN
XTALOUT
PWRDWN
Line Plug
DVDD M/S 18 HC0 16 R5 RESET 41 C20
L6
C28
B1
T1
IC2 STLC7550
R20
C31
DVDD
AVDD
VREFP
VCM
DGND
VREFN
AUXIN+
AGND1
AGND2
AUXIN-
D3
R22
33
20
27
32
28
19
31
6
5
Q1
C36
Q2
Figure 10 : ST7554 Schematic Diagram with STLC7550 (in TQFP48 package)
R25
C19
R30
C18
DVDD
7554S-11.EPS
ST7554
PACKAGE MECHANICAL DATA 48 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
B
12 13 24
25
E3 E1 E
c
D3 D1 D
L1
L
K
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Min. 0.05 1.35 0.17 0.09
Millimeters Typ.
1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00
Max. 1.60 0.15 1.45 0.27 0.20
Min. 0.002 0.053 0.007 0.004
Inches Typ.
0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039
Max. 0.063 0.006 0.057 0.011 0.008
0.45
0.75
0.018
0.030
5B.TBL
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
11/11
PM-5B.EPS
0,25 mm .010 inch GAGE PLANE

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