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| DATA SHEET BIPOLAR DIGITAL INTEGRATED CIRCUITS PB1502GR, 1502GR(1) 1.7 GHz/ 2.0 GHz LOW-POWER TWO-MODULUS PRESCALER DIVIDED-BY-64/65, 128/129 FEATURES * * * * * * High toggle frequency - 2.0 GHz: PB1502GR(1), 1.7 GHz: PB1502GR Low power consumption - 6.7 mA TYP. at 3 V Operating supply voltage - 2.7 V to 3.3 V High input sensitivity - 130 to 220 mVP-P: PB1502GR(1), 100 to 320 mVP-P: PB1502GR (@50 ) Equipped with power-save function: 5 A (standard) on power-save mode. Packaged in 8 pins plastic SOP suitable for surface mounting. DESCRIPTION PB1502GR and PB1502GR(1) are two-modulus prescaler divided by 64/65 or 128/129. This device is designed for mobile communication applications for example 0.8-1.9 GHz cellular and cordless telephones. The ICs operate on low power and therefore are suitable for hand-held, battery-operated systems. These products are manufactured using NEC's 20 GHz fT NESATTM III silicon bipolar process. This process uses silicon nitride passivation film and gold metallization wirings. These materials can protect the chips from external pollution and prevent corrosion and migration. Thus, these products have excellent performance, uniformity and reliability. ORDER INFORMATION ORDER NUMBER PACKAGE 8 pin plastic SOP (225 mil) SUPPLYING FORM Embossed tape 12 mm wide. QTY 2.5 k/reel Pin1 is in tape pull-out direction. fin MAX. 1.7 GHz 2.0 GHz PB1502GR-E1 PB1502GR(1)-E1 Remarks To order evaluation samples, please contact your local NEC sales office. (Order number: PB1502GR, PB1502GR(1)) Caution electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10871EJ3V0DS00 (3rd edition) Date Published October 1999 N CP(K) Printed in Japan The mark shows major revised points. (c) 1996, 1999 PB1502GR, 1502GR(1) PIN ASSIGNMENT (Top View) IN VCC SW OUT IN VPS M GND INTERNAL BLOCK DIAGRAM (2) VCC (7) VPS (5) GND D CK CK (8)IN (1)IN DFF1 Q D CK CK DFF2 Q D CK CK DFF3 Q Q Q Q M(6) T Q T Q T Q T Q T SW Q OR TFF1 TFF2 TFF3 TFF4 TFF5 OUT(4) AMP SW(3) : pin ( ) : pin No. 2 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Total power dissipation Operating temperature Storage temperature SYMBOL VCC VIN PD Topt Tstg RATINGS -0.5 to +6 -0.5 to VCC +0.5 250 -40 to +85 -65 to +150 UNIT V V mW C C TA = +25 C TA = +25 C Mounted on double sided copper clad 50 x 50 x 1.6 mm epoxy glass PWB (TA = +85 C) CONDITION RECOMMENDED OPERATING RANGE PARAMETER Supply voltage Operating temperature SYMBOL VCC Topt MIN. 2.7 -40 TYP. 3.0 +25 MAX. 3.3 +85 UNIT V C ELECTRICAL CHARACTERISTICS (TA = - 40 to +85 C, VCC = 2.7 to 3.3 V) PB1502GR PARAMETER Response frequency Circuit current Input power sensitivity 1 Input power sensitivity 2 Input power sensitivity 3 Input power sensitivity 4 Modulus control input high (M) Modulus control input low (M) Divide ratio control input high (SW) Divide ratio control input low (SW) Output voltage swing Modulus set up time Power-save input high Power-save input low Circuit current on power-save mode SYMBOL MIN. fin ICC Pin1 Pin2 Pin3 Pin4 VIH1 VIL1 VIH2 VIL2 VOUT tset VPSH VinL IPS 0.5 3.2 -11 -15 -15 -- 2.5 -- VCC 6.7 -- -- -- -- -- -- VCC TYP. MAX. 1.7 11.0 0 0 -6 -- -- 0.8 VCC MIN. 0.5 3.2 -11 -15 -15 -14 2.5 -- VCC 6.7 -- -- -- -- -- -- VCC TYP. MAX. 2.0 11.0 0 0 -1 -9 -- 0.8 VCC GHz mA dBm dBm dBm dBm V V V V VP-P ns V V VPSL level VPSL level * * CL = 8 pF finMAX. Pin = -10 dBm VPSH level, No input signal fin = 0.5 to 0.8 GHz fin = 0.8 to 1.5 GHz fin = 1.5 to 1.7 GHz fin = 1.7 to 2.0 GHz PB1502GR(1) UNIT CONDITION OPEN OPEN OPEN OPEN OPEN OPEN 0.8 -- VCC -- -- -- 11 VCC -- 5 -- -- VCC 0.8 20 0.8 -- VCC -- -- -- 11 VCC -- 5 -- -- VCC 0.8 20 A * Standard reference value on power-save mode. Data Sheet P10871EJ3V0DS00 3 PB1502GR, 1502GR(1) PIN DESCRIPTIONS Pin No. 1 Symbol IN Assignment Frequency input pin Functions and Explanation Input frequency from an external VCO output. Must be coupled with capacitor (e.g. 1 000 pF) for DC cut. Supply voltage 3.0 0.3 V for operation. Must be connected bypass capacitor (e.g. 1 000 pF) to minimize ground impedance. Divided ratio and modulus control can be governed by following input data to these pins. M H H SW L 1/128 1/129 1/64 L 1/65 2 VCC Power supply pin 3 SW Divided ratio control input pin Modulus control input pin 6 M 4 OUT Divided frequency output pin Ground pin This frequency output can be interfaced to CMOS PLL. Must be coupled with capacitor (e.g. 1 000 pF) for DC cut. Must be connected to the system ground with minimum inductance. Ground pattern on the board should be formed as wide as possible. (Track length should be kept as short as possible). ON/OFF-operation control can be governed by following input data to this pin. Operation H VPS L OFF ON 5 GND 7 VPS Power-save function pin 8 IN Frequency-input bypass pin Must be connected bypass capacitor (e.g. 1 000 pF) to minimize ground impedance. 4 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) TEST CIRCUIT 1 000 pF IN 50 S.G. 50 C1 C2 C3 VCC SW OUT C4 VPS M GND C7 C6 1 000 pF 3.0 to 0 V IN C8 1 000 pF 2.7 to 3.0 V 1 000 pF 1 000 pF 2.7 to 3.0 V 1 000 pF 3.0 to 0 V 1 000 pF 1 M OscilloScope 3 pF C5 5 pF M H H SW L 1/128 1/129 1/64 L 1/65 APPLICATION CIRCUIT FOR REFERENCE 1 000 pF MIX 1 000 pF 1 000 pF (PB1502GR) IN IN 1 000 pF 1 000 pF VCO 1 000 pF VT 1 000 pF 1 000 pF 1 000 pF VCC VPS SW M OUT GND Buffer Amp. 2SC4093 ( PC2745T) LPF 1 000 pF 1 000 pF fIN CP PLL TCXO REF M EN DATA CLOCK VCC CPU GND 1 000 pF The application circuits and their parameters are for references only and are not intended for use in actual design-in's. To know the real application circuits, please refer to PLL synthesizer LSI's documentations (e.g.PD3160GS). Data Sheet P10871EJ3V0DS00 5 PB1502GR, 1502GR(1) TIMING DIAGRAM Divided by 64/65 SW 'H' (Divided by 128/129 SW 'L') 64 clocks (128) IN 65 clocks (129) 32 clocks (64) OUT 32 clocks (64) 32 clocks (64) 33 clocks (65) 32 (64) 32 (64) 32 (64) 32 (64) 32 (64) 32 (64) 32 (64) 32 (64) 33 (65) 32 (64) 33 (65) 33 (65) Hi M LO tset = The minimum time required between `Modulus Control' going low and next output rising edge, in order to ensure a P+1 modulus change. tset 6 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) ILLUSTRATION OF THE TEST CIRCUIT ASSEMBLED ON EVALUATION BOARD IN C 1 C8 VCC SW 1pin C2 C3 IN C7 VPS M GND C C 5 4 OUT Component List No. C1 to 4 C5 C6 to 8 Value 1 000 pF 8 pF 1 000 pF Note (1) 50 x 50 x 0.4 mm double copper clad polyimide board. (2) Back side: GND pattern (3) Solder plated on pattern (4) : Through holes C6 Data Sheet P10871EJ3V0DS00 7 PB1502GR, 1502GR(1) TYPICAL CHARACTERISTICS (TA = +25 C) -- PB1502GR, PB1502GR(1) in common -- CIRCUIT CURRENT vs. SUPPLY VOLTAGE 14 12 PB1502GR PB1502GR(1) : TA = +85 C : TA = +25 C : TA = -40 C Circuit Current ICC (mA) 10 8 6 4 2 0 2 4 Supply Voltage VCC (V) OUTPUT VOLTAGE SWING vs. SUPPLY VOLTAGE 1.4 1.2 6 Output Swing Vout (VP-P) 1.0 0.8 0.6 0.4 0.2 0 2.4 PB1502GR PB1502GR(1) : TA = +85 C : TA = +25 C : TA = -40 C 2.6 2.8 3.0 3.2 3.4 Supply Voltage VCC (V) 3.6 S11 vs. f VCC = 3.0 V, ICC = 6.7 mA, ZO = 50 W 0.5 GHz 2.0 GHz 1.0 GHz 8 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) -- PB1502GR -- INPUT POWER vs. FREQUENCY +60 +40 -- PB1502GR(1) -- INPUT POWER vs. FREQUENCY +60 +40 Input Power Pin (dBm) +20 0 * -20 -40 -60 Input Power Pin (dBm) PB1502GR TA = +25 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V PB1502GR(1) TA = +25 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V +20 0 * -20 -40 -60 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 INPUT POWER vs. FREQUENCY +60 +40 INPUT POWER vs. FREQUENCY +60 +40 Input Power Pin (dBm) +20 0 * -20 -40 -60 Input Power Pin (dBm) PB1502GR TA = +85 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V PB1502GR(1) TA = +85 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V +20 0 * -20 -40 -60 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 INPUT POWER vs. FREQUENCY +60 +40 INPUT POWER vs. FREQUENCY +60 +40 Input Power Pin (dBm) +20 0 * -20 -40 -60 Input Power Pin (dBm) PB1502GR TA = -40 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V PB1502GR(1) TA = -40 C : VCC = 2.7 V : VCC = 3.0 V : VCC = 3.3 V +20 0 * -20 -40 -60 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 0.2 0.6 1.2 1.6 Input Frequency f (GHz) 2.0 2.4 * Guaranteed Operating Window Data Sheet P10871EJ3V0DS00 9 PB1502GR, 1502GR(1) TYPICAL SYSTEM APPLICATION Digital Cellular System Block Diagram Low Noise Tr RX Downconverter DEMO. I Q PD3160 VCC SW /N PB1502 PLL PLL I 0 TX PA Driver 90 Q Other applicable systems 1.9 GHz digital cordless telephone, hand-held radio. 10 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) PACKAGE DIMENSIONS 8 PIN PLASTIC SOP (225 mil) (UNIT: mm) 8 5 detail of lead end 3-3 +7 1 5.2 0.2 4 6.5 0.3 1.57 0.2 1.49 4.4 0.15 1.1 0.2 0.85 MAX. 1.27 0.42 -0.07 0.1 0.1 +0.08 0.6 0.2 0.17 -0.07 +0.08 0.10 0.12 M NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. Data Sheet P10871EJ3V0DS00 11 PB1502GR, 1502GR(1) NOTE ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as wide as possible to minimize ground impedance (to prevent abnormal operation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor (e.g. 1 000 pF) to the VCC pin. RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. PB1502GR, 1502GR(1) Recommended condition symbol Soldering method Infrared ray reflow Soldering conditions Package peak temperature: 235 C, Hour: within 30 s. (more than 210 C), Time: 3 times, Limited days: no.* Package peak temperature: 215 C, Hour: within 40 s. (more than 200 C), Time: 3 times, Limited days: no.* Soldering tub temperature: less than 260 C, Hour: within 10 s. Time: 1 time, Limited days: no. Pin area temperature: less than 300 C, Hour: within 3 s./pin Limited days: no.* IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Pin part heating *: It is the storage days after opening a dry pack, the storage conditions are 25 C, less than 65 % RH. Note 1. The combined use of soldering method is to be avoided (However, except the pin area heating method). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 12 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) [MEMO] Data Sheet P10871EJ3V0DS00 13 PB1502GR, 1502GR(1) [MEMO] 14 Data Sheet P10871EJ3V0DS00 PB1502GR, 1502GR(1) [MEMO] Data Sheet P10871EJ3V0DS00 15 PB1502GR, 1502GR(1) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8 |
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