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Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V208A is a family of low voltage 2-Mbit static RAMs organized as 262,144-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25m CMOS technology. The M5M5V208A is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The M5M5V208A is packaged in 32-pin 8mm x 13.4mm STSOP packages. Two types of STSOPs are available, M5M5V208AKV (normal-lead-bend STSOP) and M5M5V208AKR (reverse-lead-bend STSOP). These two types STSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below.
FEATURES
* Single 2.7 ~ 3.6V power supply * No clocks, No refresh * All inputs and outputs are TTL compatible. * Easy memory expansion and power down by S1 & S2 * Data retention supply voltage=2.0V * Three-state outputs: OR-tie capability * OE prevents data contention in the I/O bus * Common Data I/O * Battery backup capability * Small stand-by current * * * * * * * * * * 0.3A(typ.)
PACKAGE
M5M5V208AKV,KR : 32pin 8 X 13.4 mm TSOP Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 25C 40C 25C 40C 70C ----------------85C ----Active current Icc1 (3.0V, typ.)
PART NAME TABLE
Version, Operating temperature Part name (## stands for"KV"or"KR")
Power Supply
Access time
max.
Standard 0 ~ +70C
W-version -20 ~ +85C
I-version -40 ~ +85C
M5M5V208A## -55L 2.7 M5M5V208A## -70L M5M5V208A## -55H 2.7 M5M5V208A## -70H M5M5V208A## -55LW M5M5V208A## -70LW 2.7 M5M5V208A## -55HW M5M5V208A## -70HW 2.7 M5M5V208A## -55LI M5M5V208A## -70LI 2.7 M5M5V208A## -55HI M5M5V208A## -70HI 2.7
55ns --~ 3.6V 70ns ~ 3.6V 55ns 0.3A 70ns 55ns --~ 3.6V 70ns 55ns ~ 3.6V 70ns 0.3A 55ns --~ 3.6V 70ns 55ns ~ 3.6V 70ns 0.3A
20A
1A 3A 8A
-----
20mA
(f=10MHz)
20A 50A 3mA
(f=1MHz)
1A 3A 8A 24A
-----
20A 50A
1A 3A 8A 24A
* "typical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW) A11 A9 A8 A13 W S2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
M5M5V208AKV
OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3
S2 W
A4 A5 A6 A7 A12 A14 A16 A17 Vcc A15 A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
M5M5V208AKR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8
S1
A10
OE
Outline 32P3K-B(KV)
Outline 32P3K-C(KR)
MITSUBISHI ELECTRIC
1
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208A is determined by a combination of the device control inputs S1, S2, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable OE directly controls the output stage. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state (S1 = L ,S2 = H). When setting S1 at a high level or S2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S1 or S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode.
FUNCTION TABLE
S1 X H L L L S2 L X H H H W X X L H H OE X X X L H Mode Non selection Non selection Write Read DQ High-impedance High-impedance D IN D OUT High-impedance Icc Standby Standby Active Active Active
BLOCK DIAGRAM
* A4 A5 A6 A7 A12 A14 A16 A17 A15
8 7 6 5 4 3 2 1 31 16 15 14 13 12 11 10 9 7 262144 WORDS X 8 BITS 512 ROWS X 128 COLUMNS X 32 BLOCKS 21 22 23 25 26 27 28 29 13 14 15 17 18 19 20 21
* DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
A0 A1 A2 A3 A10 A11 A9 A8 A13
12 11 10 9 23 25 26 27 28
20 19 18 17 5 31 1 2 3 4 8 32 30 6 32 29 22 30 24 CLOCK GENERATOR
W S1 S2 OE VCC
(3V)
24
16
GND
(0V)
*Pin numbers inside dotted line show reverse-lead-bend sTSOP.
MITSUBISHI ELECTRIC
2
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Vcc VI VO Pd Topr Tstr
Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions
With respect to GND Ta=25C
Ratings - 0.5*~4.6 - 0.5* ~ Vcc + 0.5
(Max 4.6)
Unit V V V mW
0 ~ Vcc 700
Standard W - Version I - Version
* - 3.0V in case of AC ( Pulse width 30ns )
0 ~ 70 - 20 ~ 85 - 40 ~ 85 - 65 ~150
C C C C
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH1 VOH2 VOL II IO Icc1 Parameter High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current Output current in off-state Active supply current
(CMOS-level Input)
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Limits Test conditions Min 2.0 IOH= - 0.5mA IOH= - 0.05mA IOL=2mA VI=0 ~ Vcc
S1=VIH or S2=VIL or OE=VIH VI/O=0 ~ Vcc
Typ
- 0.3* 2.4 Vcc -0.5V
Max Vcc +0.3V 0.6
Unit V V V V
0.4 1 1
f= 10MHz f= 5MHz f= 1MHz f= 10MHz f= 5MHz f= 1MHz
V A A
S1 0.2V, S2 Vcc-0.2V, other inputs 0.2V or Vcc-0.2V,output-open S1=VIL,S2=VIH,
other inputs=VIH or VIL
Icc2
Active supply current
(TTL-level Input)
output-open 1) S2 0.2V, Icc3
other inputs=0 ~ Vcc or 2) S1 Vcc-0.2V, S2 Vcc-0.2V other inputs=0 ~ Vcc
20 10 3 22 12 3 0.3
-L
Stand-by current
~+25C -H ~+40C -HW -HI ~+70C -HW / I ~+85C
Icc4
Stand-by current
S1=VIH or S2=VIL,other inputs=0 ~ Vcc
25 13 5 27 15 5 60 2 5 10 30 0.33
mA
mA
A
mA
* - 3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE
Symbol CI CO Parameter
Input capacitance Output capacitance
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Test conditions
VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Min
Limits Typ
Max
Unit
pF pF
8 10
Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is for Vcc = 3V, Ta = 25C
MITSUBISHI ELECTRIC
3
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) MEASUREMENT CONDITIONS
................................. Vcc Input pulse level ............. Input rise and fall time ..... Reference level ............... Output loads ...................
( Vcc= 2.7 ~ 3.6V, unless otherwise noted) 1TTL DQ CL including scope and JIG Fig.1 Output load
2.7 ~ 3.6V VIH=2.2V,VIL=0.4V 5ns VOH=VOL=1.5V Fig.1,CL=30pF CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
(2) READ CYCLE
Limits Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address
-55L,H
Min Max
-70L,H
Min Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns
55 55 55 55 30 20 20 20 10 10 5 10
70 70 70 70 35 25 25 25 10 10 5 10
(3) WRITE CYCLE
Limits Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low
-55L,H
Min Max
-55L,H
Min Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
55 45 0 50 50 50 25 0 0 5 5
20 20
70 55 0 65 65 65 30 0 0 5 5
25 25
MITSUBISHI ELECTRIC
4
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
A0~17 ta(A) ta (S1) S1
(Note 3)
tCR
tv (A)
tdis (S1)
(Note 3)
S2
(Note 3)
ta (S2) ta (OE) ten (OE) tdis (S2)
(Note 3)
OE
(Note 3)
tdis (OE) ten (S1) ten (S2)
(Note 3)
DQ1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
A0~17
tCW
tsu (S1) S1
(Note 3) (Note 3)
S2
(Note 3)
tsu (S2)
(Note 3)
tsu (A-WH) OE tsu (A) W tdis (W) tdis (OE) DQ1~8 ten (W) ten(OE) tw (W) trec (W)
DATA IN STABLE
tsu (D)
th (D)
MITSUBISHI ELECTRIC
5
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW A0~17 tsu (A) S1 tsu (S1) trec (W)
S2
(Note 3) (Note 5) (Note 3)
W
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ1~8
DATA IN STABLE
Write cycle (S2 control mode)
tCW A0~17
S1
(Note 3) tsu (A) (Note 3)
tsu (S2)
trec (W)
S2
(Note 5)
W
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ1~8
DATA IN STABLE Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S2 high overlaps S1 and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI ELECTRIC
6
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol
Vcc (PD) VI (S1) VI (S2)
Parameter
Power down supply voltage Chip select input S1 Chip select input S2
Test conditions
Limits Min Typ Max
Unit
V V
2 2.0
-L
Icc (PD)
Vcc=3.0V 1) S2 0.2V,other inputs=0 ~ Vcc or Power down supply current 2) S1 Vcc-0.2V,S2 Vcc-0.2V other inputs=0 ~ Vcc
~+25C -H -HW ~+40C -HI ~+70C -HW / I ~+85C
0.2 50 0.3 1 3 8 24
V
A
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time tsu (PD) Power down recovery time trec (PD) Test conditions Min
0 5
Limits Typ Max
Unit
ns ms
(3) POWER DOWN CHARACTERISTICS S1 control mode
Vcc t su (PD)
2.2V 2.7V
2.7V
t rec (PD)
2.2V
S1
S1 Vcc - 0.2V
S2 control mode
Vcc S2
0.2V S2 0.2V
t su (PD)
2.7V
2.7V
trec (PD)
0.2V
MITSUBISHI ELECTRIC
7
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Revision History Revision No. A0.1E A0.2E
History The first edition The second edition
Date 09.Nov.'98 29.Nov.'99 Preliminary Preliminary
MITSUBISHI ELECTRIC
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