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HY62K(U,V)T08081E Series
32Kx8bit CMOS SRAM
Document Title
32K x8 bit 2.7~3.3V / 3.0~3.6V / 2.7~3.6V Low Power Slow SRAM
Revision History
Revision No 00 History Initial Merged 3.0V/3.3V SPEC Revised - Marking Information Change : SOP Type - Voh Limit Change : 2.4V => 2.2V @2.7~3.6V Changed Logo - HYUNDAI -> hynix - Marking Information Change Draft Date Jan.20.2000 Remark Final
01
Feb.21.2001
Final
02
Apr.30.2001
Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 02 / Apr. 2001 Hynix Semiconductor
HY62K(U,V)T08081E Series
DESCRIPTION
The HY62K(U,V)T08081E is a high-speed, low power and 32,786 X 8-bits CMOS Static Random Access Memory fabricated using Hynix's high performance CMOS process technology. It is suitable for use in low voltage operation and battery back-up application. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0 volt.
FEATURES
* * * * Fully static operation and Tri-state output TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min.) data retention * Standard pin configuration - 28 pin 600mil PDIP - 28 pin 330mil SOP - 28 pin 8x13.4 mm TSOP-I (Standard) Standby Current(uA) LL-Part 5 8 8 5 8 8 5 8 8 Temperature (C) 0~70(Normal) -25~85(Extended) -40~85(Extended) 0~70(Normal) -25~85(Extended) -40~85(Extended) 0~70(Normal) -25~85(Extended) -40~85(Extended)
Product Voltage Speed No. (V) (ns) HY62KT08081E-C 2.7~3.6 70*/85/100 HY62KT08081E-E HY62KT08081E-I HY62VT08081E-C 70/85/100 3.0~3.6 HY62VT08081E-E HY62VT08081E-I HY62UT08081E-C 2.7~3.3 70*/85/100 HY62UT08081E-E HY62UT08081E-I Note *. Measured at 30pF test load.
Operation Current(mA) 2
2
2
PIN CONNECTION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss Vcc /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4
/OE A11 A9 A8 A13 /WE Vcc A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
PDIP
SOP
TSOP-I(Standard)
PIN DESCRIPTION
Pin Name /CS /WE /OE A0 ~ A14 I/O1 ~ I/O8 Vcc Vss Pin Function Chip Select Write Enable Output Enable Address Inputs Data Input/Output Power(+5.0V) Ground
A0
BLOCK DIAGRAM
SENSE AMP ROW DECODER ADD INPUT BUFFER I/O1 OUTPUT BUFFER I/O8
COLUMN DECODER
A14 /CS /OE /WE
Rev 02 / Apr. 2001
CONTROL LOGIC
WRITE DRIVER
MEMORY ARRAY 512x512
2
HY62K(U,V)T08081E Series
ORDERING INFORMATION
Part No. Vcc HY62KT08081E-DPC HY62KT08081E-DPE HY62KT08081E-DPI HY62KT08081E-DGC HY62KT08081E-DGE 2.7~3.6V HY62KT08081E-DGI HY62KT08081E-DTC HY62KT08081E-DTE HY62KT08081E-DTI HY62VT08081E-DPC HY62VT08081E-DPE HY62VT08081E-DPI HY62VT08081E-DGC 3.0~3.6V HY62VT08081E-DGE HY62VT08081E-DGI HY62VT08081E-DTC HY62VT08081E-DTE HY62VT08081E-DTI HY62UT08081E-DPC HY62UT08081E-DPE HY62UT08081E-DPI HY62UT08081E-DGC HY62UT08081E-DGE 2.7~3.3V HY62UT08081E-DGI HY62UT08081E-DTC HY62UT08081E-DTE HY62UT08081E-DTI Note *. Measured at 30pF test load. Speed Power Temp 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C 0 to 70C -25 to 85C -40 to 85C Package PDIP
70*/85/100ns
LL-part
SOP
TSOP-I Standard
PDIP
70/85/100ns
LL-part
SOP
TSOP-I Standard
PDIP
70*/85/100ns
LL-part
SOP
TSOP-I Standard
ABSOLUTE MAXIMUM RATING (1)
Symbol Vcc, VIN, VOUT TA Parameter Power Supply, Input/Output Voltage Operating Temperature HY62K(U,V)T08081E-C HY62K(U,V)T08081E-E HY62K(U,V)T08081E-I Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.3 to 4.6 0 to 70 -25 to 85 -40 to 85 -65 to 150 1.0 50 260 *10 Unit V C C C C W mA C*sec
TSTG PD IOUT TSOLDER Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Rev 02 / Apr. 2001
2
HY62K(U,V)T08081E Series
RECOMMENDED DC OPERATING CONDITIONS
Symbol Vcc Power Supply Voltage Parameter HY62KT08081E HY62VT08081E HY62UT08081E Min. 2.7 3.0 2.7 0 2.2 -0.3(1) Typ. 3.0/3.3 3.3 3.0 0 Max. 3.6 3.6 3.3 0 Vcc+0.3 0.4 Unit V V V V V V
Vss Ground VIH Input High Voltage VIL Input Low Voltage Note 1. VIL = -1.5V for pulse width less than 50ns
TRUTH TABLE
/CS /WE /OE Mode H X X Standby L H H Output Disabled L H L Read L L X Write Note 1. H=VIH, L=VIL, X=Don't Care I/O Operation High-Z High-Z Data Out Data In
DC CHARACTERISTICS
Vcc = 2.7~3.6V, TA = 0C to 70C (Normal)/-25C to 85C (Extended) /-40C to 85C (Industrial), unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. ILI Input Leakage Current Vss < VIN < Vcc -1 1 ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or -1 1 /OE = VIH or /WE = VIL Icc Operating Power Supply /CS = VIL, 2 Current VIN = VIH or VIL, II/O = 0mA ICC1 Average Operating Current /CS = VIL, VIN = VIH or VIL, 30 Min. Duty Cycle = 100%, II/O = 0mA ICC2 Average Operating Current /CS = VIL, VIN = VIH or VIL 5 Cycle = 1us , II/O = 0mA ISB TTL Standby Current /CS= VIH, 0.3 (TTL Inputs) VIN = VIH or VIL ISB1 CMOS Standby Current /CS > Vcc - 0.2V, 5 0~70 C (CMOS Inputs) VIN > Vcc - 0.2V or -25~85 C or 8 VIN < Vss + 0.2V -40~85 C VOL Output Low Voltage IOL = 2.1mA 0.4 VOH Output High Voltage IOH = -1.0mA 2.2 Note : Typical values are at Vcc =3.0/3.3V, TA = 25C
Unit uA uA mA mA mA mA uA uA V V
Rev 02 / Apr. 2001
3
HY62K(U,V)T08081E Series
AC CHARACTERISTICS
Vcc = 2.7~3.6V , TA = 0C to 70C (Normal)/-25C to 85C (Extended) /-40C to 85C (Industrial), unless otherwise specified. -70 -85 -10 # Symbol Parameter Min. Max. Min. Max. Min Max. READ CYCLE 1 tRC Read Cycle Time 70 85 100 2 tAA Address Access Time 70 85 100 3 tACS Chip Select Access Time 70 85 100 4 tOE Output Enable to Output Valid 35 40 50 5 tCLZ Chip Select to Output in Low Z 10 10 10 6 tOLZ Output Enable to Output in Low Z 5 5 5 7 tCHZ Chip Deselection to Output in High Z 0 30 0 30 0 30 8 tOHZ Out Disable to Output in High Z 0 30 0 30 0 30 9 tOH Output Hold from Address Change 10 10 15 WRITE CYCLE 10 tWC Write Cycle Time 70 85 100 11 tCW Chip Selection to End of Write 60 70 80 12 tAW Address Valid to End of Write 60 70 80 13 tAS Address Set-up Time 0 0 0 14 tWP Write Pulse Width 50 60 70 15 tWR Write Recovery Time 0 0 0 16 tWHZ Write to Output in High Z 0 25 0 30 0 35 17 tDW Data to Write Time Overlap 30 40 40 18 tDH Data Hold from Write Time 0 0 0 19 tOW Output Active from End of Write 5 5 10 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev 02 / Apr. 2001
4
HY62K(U,V)T08081E Series
AC TEST CONDITIONS
Vcc = 2.7~3.6V, TA = 0C to 70C (Normal)/-25C to 85C (Extended) /-40C to 85C (Industrial), unless otherwise specified. Parameter Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW CL = 5pF + 1TTL Load Others CL = 100pF + 1TTL Load CL* = 30pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
TA = 25C, f = 1.0MHz Symbol Parameter CIN Input Capacitance CI/O Input /Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF
Note : These parameters are sampled and not 100% tested
Rev 02 / Apr. 2001
5
HY62K(U,V)T08081E Series
TIMING DIAGRAM
READ CYCLE 1
tRC ADDR tAA OE tOE tOLZ CS tACS tCLZ Data Out High-Z Data Valid tOHZ tCHZ tOH
Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle.
READ CYCLE 2
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
Note(READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS= VIL. 3. /OE =VIL.
Rev 02 / Apr. 2001
6
HY62K(U,V)T08081E Series
WRITE CYCLE 1(/OE Clocked)
tWC ADDR
OE tAW tCW CS tAS WE tDW Data In tOHZ
Data Out
tWP
tWR
tDH Data Valid
WRITE CYCLE 2 (/OE Low Fixed)
tWC ADDR tAW tCW CS tAS WE tDW Data In tWHZ Data Out tDH Data Valid tOW (7) (8) tWP tWR
Rev 02 / Apr. 2001
7
HY62K(U,V)T08081E Series
Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS, or /WE going high. 5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state, input of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of the new address.
DATA RETENTION CHARACTERISTIC
Vcc = 2.7~3.6V, TA = 0C to 70C (Normal)/-25C to 85C (Extended) /-40C to 85C (Industrial), unless otherwise specified. Symbol Parameter Test Condition Min Typ Max VDR Vcc for Data Retention CS>Vcc-0.2V, 2.0 3.6 VIN>Vcc-0.2V or VINVcc - 0.2V, VIN>Vcc - 0.2V or 0.5 8 -25~85C or VINUnit V uA uA ns ns
DATA RETENTION TIMING DIAGRAM
VCC 2.7V/3.0V tCDR DATA RETENTION MODE tR
2.2V VDR CS>VCC-0.2V CS VSS
Rev 02 / Apr. 2001
8
HY62K(U,V)T08081E Series
PACKAGE INFORMATION
28pin 600mil Dual In-Line Package(Blank) *
UNIT : INCH(mm)
MAX. MIN.
1.467(37.262) 1.447(36.754) 0.600(15.240)BSC 0.090(2.286) 0.070(1.778) 0.065(1.650) 0.050(1.270) 0.155(3.937) 0.145(3.683) 0.035(0.889) 0.020(0.508) 0.550(13.970) 0.530(13.462)
0.140(3.556) 0.021(0.533) 0.100(2.54)BSC 0.015(0.381) 0.120(3.048)
3 deg 11 deg
0.014(0.356) 0.008(0.200)
28pin 330mil Small O utline Package(FW)
0.346(8.788) 0.338(8.585) 0.480(12.192) 0.460(11.684)
UNIT : INCH(mm)
MAX . MIN.
0.728(18.491) 0.720(18.288)
0.110(2.794) 0.094(2.388) 0.014(0.356) 0.002(0.051) 0.012(0.305) 0.008(0.203) 0.050(1.270) 0.030(0.762)
0.050(1.270)BSC
0.020(0.508) 0.014(0.356)
Rev 02 / Apr. 2001
9
HY62K(U,V)T08081E Series
28pin 8x13.4mm Thin Small Outline Package Standard(T)
UNIT : INCH(mm)
MAX. MIN.
0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2)
0.319(8.1) 0.311(7.9)
0.040(1.02) 0.036(0.91) 0.008(0.20) 0.002(0.05)
0.027(0.7) 0.012(0.3)
0.008(0.2) 0.004(0.1)
0.022(0.55 BSC)
Rev 02 / Apr. 2001
10
HY62K(U,V)T08081E Series
MARKING INFORMATION
Package
h y Y O n 6 R i
Marking Example
x v A T 0 x 8 x 1 x y E x y c x w s x w s x p t x
PDIP
H K
2 E
h
y Y O
n 6 R
i 2 E
x v A T 0 8 1
y E
y c
w s
w s
p t
SOP
H K
h
y Y O
n 6 R
i 2 E
x v A T 0 8 1
y E
y c
w s
w s
p t
TSOP-I
H K
Index
* hynix * KOREA * HY62vT081E : hynix Logo : Origin Country : Part Name - HY62KT081E : 2.7~3.6V - HY62VT081E : 3.0~3.6V - HY62UT081E : 2.7~3.3V : Year ( ex : 00 = year 2000, 01 = year 2001 ) : Work Week ( ex : 12 = ww12 ) : Process Code : Power Consumption -L : Low Power -D : Low Low Power : Speed - 70 : 70ns - 85 : 85ns : Temperature -C : Commercial ( 0 ~ 70 C ) -E : Extended ( -25 ~ 85 C ) -I : Industrial ( -40 ~ 85 C ) : Lot Number
* yy * ww *p *c
* ss
*t
* xxxxxxxx Note - Capital Letter - Small Letter
: Fixed Item : Non-fixed Item ( Except hynix )
Rev 02 / Apr. 2001
11

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