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YTD439
ISTU
ISDN BRI controller for Terminal Equipment with built-in DSU
Abstract
YTD439 is a LSI that integrates in a single chip all the communication functions that are necessary for constructing an ISDN terminal with a built-in DSU. The functions of both the DSU (U reference point) and terminal (S/T reference point) are packed into the 100-pin SQFP chip allowing miniaturization of the terminal equipment. YTD439 has a built-in TD switch function that is necessary for controlling the connection of the B-channel data. By connecting an external CPU, memory, and CODEC, a terminal with a built-in DSU can be configured. In addition, YTD439 has a function that reduces the power consumption by stopping the functions of unused blocks. This is effective for battery-driven terminals.
Features
DSU block * Conforms to TTC Standards JT-I430 and JT-G961. * LT (line termination) function and CT (circuit termination) function. * DSU can be disconnected. S/T reference point driver/receiver block * Transition to the sleep state possible by setting an I/O register. CPU interface block * 8-bit or 16-bit data bus selectable. * I/O access through registers.
YTD439 CATALOG CATALOG No.:4TD439A2 2001.1
Layer 1 control block * Frame assembling and disassembling function. * I430 TTL output pin Layer 2 control block * Built-in LAPD protocol (supports four links). * Call control and D-channel packet function. Layer 3 interface block * Message exchange through I/O access (large 1088-byte FIFO). B channel HDLC controller * Supports CRC-CCITT and CRC-32. * 128k/64k/56k rate adaption B channel transparent * Supports PIAFS 64k/32k. * Flexible rate adaption function. B channel DATA FIFO * Transmission and reception: 128-byte FIFO x 2 channels. TD switch * Switch circuit for 8 channels of B channel data. * 512 k to 2,048 kHz PCM highway. Others * Terminal block can be disconnected. Power can be cut off. * Terminal block sleep mode. * Power supply to the analog block: +5 V. Power supply to the digital block: +5 V or 3.3 V. * 5 V tolerant I/O pin * 100-pin SQFP.
Applications
* Terminal adapter * Remote router * ISDN telephone * ISDN home telephone * ISDN Facsimile
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Functional Comparison of YAMAHA ISDN LSIs
Function DSU Function Layer 1 Layer 2 TTC Standard TTC Standard TTC Standard JT-G961 JT-I430 JT-Q920 JT-Q921 1993 edition YTD421 YTD428 1997 edition 1993 edition 1993 edition 1993 edition 1997 edition 1993 edition 1998 edition YTD423 YTD436 YTD439 1997 edition 1997 edition 1993 edition 1998 edition
ETSI ETS 300 012, ETS 300 125 North American Switches National ISDN-1/2, AT&T 5ESS, Nortel DMS-100 S/T Ref. Point Analog Driver/Receiver Circuit switching Maximum D Channel Links Dch Packet Switching (Teleaction communication) D Channel Layer 3 Data Transfer Method HDLC Controller for B Channel Data

External [YTD421] 2 2

2 2 (2)
or
2 2 (2) I/O Transfer
DMA Transfer DMA Transfer
or
I/O Transfer
I/O Transfer External DMA Transfer
or
DMA Transfer
or
I/O Transfer
B Channel Data Transfer Method
I/O Transfer B Channel Internal Clock Mode (kHz) B Channel External Clock Mode TD Switch Clock Output Function for CPU Signal Output Function for Testing +5 Power Supply (V) 5-V Tolerant I/O pin Package Note 1: DMA transfer: Request function only I/O transfer: 4-byte FIFO Note 2: Digital power supply only
or
I/O Transfer (Note 1) 32, 56, 64
32, 56, 64

+5 +5

+5
or

+5
or
+3.3 (Note 2)
+3.3 (Note 2) +3.3 (Note 2)
20-pin SSOP 100-pin SQFP 100-pin SQFP 100-pin SQFP 100-pin SQFP
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Block Diagram
User-Network Interface Block Diagram
YTD439 is best-suited for applications in terminal equipment with built-in DSU (TA, TE1) such as terminal adapters and remote routers with built-in DSUs. YTD439 contains a DSU function, which is necessary between the ISDN switch and the usernetwork interface, and layer 1 and layer 2 functions, which are required of ISDN system equipment. By adding minimal peripheral parts such as microprocessor and CODEC, terminal equipment can be optimally configured.
R
TE2 S/T
TE1 S T
TA with built-in DSU
U ISDN
Network
TE1 (ISDN terminal) R S NT2 (PBX, etc.) NT1 (DSU)
TE2 (Non-ISDN terminal)
TA (Terminal adapter) S/T
TE1 R YTD439 S/T U YTD436 or YTD423 + YTD421 TE1 User's premises
TE2
TA with built-in DSU
YTD428 (DSU)
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B channel PCM highway I/F (CODEC, etc) (512 k to 2,048 kHz )
Terminal block
Internal bus B channel connection section TD switch (8ch) Control I/O register
Internal Block Diagram
64k x 2 HDLC controller Rate adaption block B channel data FIFO (128 byte x 2)
B1/B2 channel
Transparent PIAFS Layer 1 control block B channel data control block (CH-A) B channel data control block (CH-B)
CPU I/F Programmable I/O
S/T ref. point
16k D channel Layer 2 control block (LAPD)
Layer 3 I/F block FIFO (1088 byte)
S/T ref. point driver/ receiver block
Circuit termination block
T ref. point connection control block
Line termination block
DSU block
U ref. point I/F
U ref. point
Clock generator
15.36 MHz
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Pin Assignments
CL512K CL8K CL4K DVSS CLKOUT /WAKEUP DVDD2 CL400,RM INF4 PDOWN PDET VDSEL LTD_TE HTD_TE POWM DVDD1 X2 X1 DVSS TSMP LPSEL NTSEL /TEST2 /TEST1 AVDD2
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
D12 DVDD2 D11 D10 D9 D8 DVSS D7 D6 D5 D4 D3 D2 D1 D0 /CS /WR,R/W /RD,/AS /INT DVSS HW_OUT HW_IN SYNC_OUT SYNC_IN EXTCLK 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
YTD439-S 100pin SQFP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
D13 D14 D15 /UBE /LBE A1 A2 A3 80/68 /RST_TE DVSS /RST_NT REV NOR DVDD1 CRD DVSS CNL LPM3 LP2A LPSW UDP1 UDP0 UDM1 UDM0
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ATEI ATEO VRB VRT RUC AVDD1 AVSS1 RXU1 SGR RXU2 SGA AVDD1 RXS SGB SGBP AVSS1 LI1 CX2 LI2 LICT CX1 AVSS2 LO1 LO2 RX
Overview of Functions
DSU Block
The DSU section achieves DSU functions of subscriber line interface (two-wire time compression multiplexing operation) and the user-network interface (digital four-wire time division full-duplex operation) for ISDN. The electrical characteristics conforming to TTC Standard JT-G961 is achieved. Line Termination Block (LT Block) The line termination section provides the f equalization that compensates for the line loss and amplitude distortion and the bridged tap equalization that compensates for signal distortion. Circuit Termination Block (CT Block) The circuit termination provides the following functions: * U/T reference point rate adaption and frame assembling and disassembling * State transition control * U reference point driver circuit control * T reference point reception timing control * Loopback control (loopback 2 and loopback C for maintenance and testing)
S/T Reference Point Driver/Receiver Block
By connecting S/T reference point transformers, the electrical characteristics conforming to TTC Standard JT-I430 is achieved. YTD439 normally operates in the DSU mode. However, if the DSU function is disconnected, YTD439 switches to the terminal mode and operates as a S/T reference point terminal LSI.
T Reference Point Connection Control Block
When the DSU block is disconnected or when the driver/receiver functions are disabled, the input/output signal of JT-I430 is switched within this control block. In addition, when disconnecting the power to the terminal block or the S/T reference point driver/receiver block, this block disconnects the signal between the DSU block and the block that is disabled.
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Terminal Block
Layer 1 control block The Layer 1 control block provides the Layer 1 functions conforming to JT-I430. It automatically controls the Layer 1 state according to (1) the phantom power detection from the network, (2) the instruction from the host processor and (3) the transaction of INFO signals and notifies the state change to the host processor. The priority/collision control block monitors the collision conditions and puts priority on D channel data access so that each terminal can access the data fairly. Layer 2 control block The Layer 2 control block provides the Layer 2 functions (LAP-D protocol) conforming to JT-Q920 and JT-Q921. YTD439 can establish total of four data links, two data links for circuit switching and two data links for D channel packet switching/teleaction communications. It supports the LAP-D frame assembly and disassembly, the SAPI and TEI address control, the LAP-D sequence control and flow control for each data link. More specifically, when the YTD439 accepts the data link establishment request from the host processor (Layer 3) in order to initiate a call or accept an incoming call, the YTD439 activates Layer 1, initiates the TEI assignment procedure (if necessary), and establishes the data link, thereby enabling the exchange of layer 3 messages. Later, the YTD439 releases the data link according to the data link release request from the host processor or the network. Since both automatic and non-automatic TEI assignment are supported, VC/PVC can be implemented for packet switching. Layer 3 Interface Block The interface between Layer 2 (YTD439) and Layer 3 (host processor) is a logic interface supporting primitives. The command/status primitives consisting of data up to 8 bytes are exchanged by writing to or reading from the YTD439 I/O registers to control the data link. I frames or UI frames containing Layer 3 messages are transferred using I/O transfer through the large dedicated FIFO. B Channel Data Control Block The B channel data control block consists of two control blocks with the same functionality for CH-A and CH-B to support the two B channels, B1 and B2. Each B channel data control block has a HDLC controller block and a transparent block, and the B channel data FIFO connects to one of the blocks. You can select the speeds of 128 k, 64 k, or 56 kHz for the HDLC controller block. The HDLC block supports CRC-CCITT, CRC-32, and no CRC. By activating the HDLC controller block, protocols such as PPP is also supported. The transparent block carries out serial-to-parallel conversion on the B channel data and expands the data in the FIFO. This allows the host processor to check the B channel data that is received from the line. It also allows transmission of DTMF signals, voice messages, and other signals to the line by the host processor writing parallel data to the FIFO. This block also has a flexible rate adaption function that allows the use of protocols such as V110. In addition, the transparent block also supports PIAFS64k and PIAFS32k. By following the commands from the host processor, this block carries out necessary tasks for PIAFS such as I460 rate adaption, SYNC pattern detection, automatic bit adjustment of 8-bit boundaries.
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TD Switch Block The TD switch block consists of the time-division switch. It allows the replacement of data of each channel on the PCM highway. By using the TD switch, the switch control of B channel data can be facilitated on terminals with multi-functionality such as extensions, three-way calls, and holding tone. YTD439 supports 512 kHz to 2,048 kHz PCM highway and can perform switching on 8 channels. You can specify which output channels to connect the 8 channels of input through the I/O register. One-to-one connection and one-to-multi-point connections are supported. The B channel data control block and the layer 1 control block (B channel data) are connected to the PCM highway internally in the YTD439, and two channels are used by each. The remaining four channels are connected to the PCM highway pins and allows connection to arbitrary channels such as an external CODEC.
Input PCM Highway
SYNC_IN pin (8 kHz) HW_IN pin (512 k - 2,048 kHz)
Time slot 0 Time slot 1 Time slot 2 Time slot 3 Time slot 4 Time slot n-1 Time slot n n:7 (Min.) - 31 (Max.)
B-ch data control block (CH-A) (CH-B)
Layer 1 control block (B1) (B2)
REG1
TD switch block
TDSW input CHI_0 CHI_1 CHI_2 CHI_3 CHI_4 CHI_5 CHI_6 CHI_7
REGX5a-h
TDSW output
CHO_0
CHO_1
CHO_2
CHO_3
CHO_4
CHO_5
CHO_6
CHO_7
REG1
B-ch data control block (CH-A) (CH-B)
Layer 1 control block (B1) (B2)
Output PCM Highway
HW_OUT pin (512 k - 2,048 kHz) SYNC_OUT pin (8 kHz)
Time slot 0 Time slot 1 Time slot 2 Time slot 3 Time slot 4 Time slot n-1 Time slot n n:7 (Min.) - 31 (Max.)
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The data path in the TD Switch Block diagram is set assuming the following application example. Voice call and voice monitor using the B1 channel B1 channel (downward) Output PCM highway time slot 0 B1 channel (upward)
: CHI_6 CHO_0
B channel data control block (CH-A) : CHI_6 CHO_4 Input PCM highway time slot 0 : CHO_6 CHI_0
Data communication using the B2 channel B2 channel (downward) B channel data control block (CH-B) : CHI_7 CHO_5 B2 channel (upward) B channel data control block (CH-B) : CHO_7 CHI_5
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Electrical Characteristics
Absolute Maximum Ratings
Parameter Symbol AVDD1 Supply voltage AVDD2 DVDD1 DVDD2 AVIN1 Input voltage AVIN2 DVIN1 DVIN2 Storage temperature Tstg Min. - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 50 Max. 6.0 6.0 5.7 5.7 AVDD1 + 0.3 AVDD2 + 0.3 5.75 5.75 125 Unit V V V V V V V V C
(Based on AVSS1 = AVSS2 = DVSS = 0.0 V)
Recommended Operating Conditions
Parameter Symbol AVDD1 AVDD2 Supply voltage DVDD1 DVDD2 DVDD2 Operating Temperature Top Note Note VDSEL = "H" VDSEL = "L" Condition Min. 4.75 4.75 3.0 4.75 4.75 3.0 0 Max. 5.25 5.25 3.6 5.25 5.25 3.6 70 Unit V V V V V V C
(Based on AVSS1 = AVSS2 = DVSS = 0.0 V)
Note: Select either a 5 V system or a 3.3 V system.
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DC Characteristics
U Reference Point Receiver (AVDD1= 5.0 V, Top = 25 C)
Parameter Allowable load impedance at output Receive buffer input impedance Analog signal reference voltage ADC self-bias Symbol ZO Zi1 VSG VRT VRB Condition Note 1 Note 2 Note 3 Note 4 Note 5 Min. 30 10 2.45 0.7AVDD1 - 0.1 0.3AVDD1 - 0.1 2.50 0.7AVDD1 0.3AVDD1 2.55 0.7AVDD1 + 0.1 0.3AVDD1 + 0.1 Typ. Max. Unit k M V V V
Note 1: Applies to the SGR pin. Note 2: Applies to the RXU1 and RXU2 pins. Note 3: Applies to the SGR pin (open). Note 4: Applies to the VRT pin. Note 5: Applies to the VRB pin.
DSU Digital Block (DVDD1 = 3.3 0.3 V or 5 V 5%, Top = 0 to 70 C)
Parameter High-level input voltage Symbol Condition VIH Note 1 Note 2 Low-level input voltage VIL Note 1 Note 2 High-level output voltage VOH Note 3 Note 4 Low-level output voltage VOL Note 3 Note 4 Leakage current Off-state leak current IL ILZ - 10 - 10 DVDD1 - 0.4 AVDD1 - 0.4 0.4 0.4 10 10 Min. 0.8DVDD1 0.9DVDD1 0.2DVDD1 0.1DVDD1 Typ. Max. Unit V V V V V V V V A A
Note 1: Applies to NOR, REV, /RST_NT, POWM, TSMP, LPSEL, NTSEL, /TEST1, /TEST2 pins. Note 2: Applies to the X1 pin. Note 3: Applies to LPSW, LP2A, LPM3, CNL, and CRD pins. Condition: IOH = - 0.4 mA, IOL = 1.2 mA Note 4: Applies to UDM0, UDM1, UDP0, and UDP1 pins. Condition: AVDD1 = 4.75 to 5.25 V, Top = 25 C, IOH = - 0.4 mA, and IOL = 1.2 mA
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Terminal Digital Block a. When DVDD2 = 5 V 5% (VDSEL pin = "H" and Top = 0 to 70 C)
Parameter High-level TTL input Low-level TTL input High-level CMOS input Low-level CMOS input High-level output Low-level output Open drain output Leakage current Off-state leakage current Symbol VIH VIL VIH VIL VOH VOL VOL IL ILZ Note 5 Condition Note 1 Note 1 Note 2 Note 2 Note 3 Note 3 Note 4 - 10 - 10 2.7 0.4 0.4 10 10 0.8DVDD2 0.2DVDD2 Min. 2.2 0.8 Typ. Max. Unit V V V V V V V A A
Note 1: Applies to EXTCLK, SYNC_IN, SYNC_OUT, HW_IN, /RD, /WR, /CS, D15 to D0, /UBE, /LBE, A3 to A1 pins. Note 2: Applies to /RST_TE, 80/68, /WAKEUP, PDET, and VDSEL pins. Note 3: IOH = -0.4 mA, IOL = 1.2 mA Note 4: When HW_OUT pin is set to open drain. Condition: RL = 500 Note 5: When pins D15 to D0 are in the input condition (when word access (16 bits) is specified) and when pins D7 to D0 are in the input condition (before issuing the SYSTEM- CONFIGURATION-REQUEST command or when byte access is (8 bits) is specified).
b. When DVDD2 = 3.3 V 0.3 V (VDSEL pin = "L", Top = 0 to 70 C)
Parameter High-level input Low-level input High-level output Low-level output Open drain output Leakage current Off-state leakage current Symbol VIH VIL VOH VOL VOL IL ILZ Note 4 Condition Note 1 Note 1 Note 2 Note 2 Note 3 - 10 - 10 DVDD2- 0.4 0.4 0.4 10 10 Min. 0.8DVDD2 0.2DVDD2 Typ. Max. Unit V V V V V A A
Note 1: Applies to EXTCLK, SYNC_IN, SYNC_OUT, HW_IN, /RD, /WR, /CS, D15 to D0, /UBE, /LBE, A3 to A1, /RST_TE, 80/68, /WAKEUP, PDET, and VDSEL pins. Note 2: IOH = -0.4 mA, IOL = 1.2 mA Note 3: When HW_OUT pin is set to open drain. Condition: RL = 500 Note 4: When pins D15 to D0 are in the input condition (when word access (16 bits) is specified) and when pins D7 to D0 are in the input condition (before issuing the SYSTEM- CONFIGURATION-REQUEST command or when byte access is (8 bits) is specified).
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Package Outline
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IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental , consequential, or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title.
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to: Semiconductor Sales & Marketing Department Head Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Tel. 81-539-62-4918 Fax. 81-539-62-5054 Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. 81-3-5488-5431 Fax. 81-3-5488-5088 Osaka Office Namba Tsujimoto Nissei Bldg, 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. 81-6-6633-3690 Fax. 81-6-6633-3691
All rights reserved 2001

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