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WM8739 / WM8739L
Stereo Audio ADC
DESCRIPTION
The WM8739 is a stereo audio ADC. The WM8739 is designed specifically for portable MP3 audio and speech players and recorders. The WM8739 is also ideal for MD, CD-RW machines and DAT recorders. Stereo line-level audio inputs are provided, along with a mute and volume function, and master or slave mode clocking schemes. The device also has a programmable high pass filter to remove residual DC offsets. Stereo 24-bit multi-bit sigma delta ADCs are used with oversampling digital interpolation and digital filters. Digital audio output word lengths from 16-32 bits and sampling rates from 8KHz to 96KHz are supported. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in a small 20pin SSOP package.
FEATURES
* * 90dB SNR (`A' weighted @ 48kHz) ADC Low Power - 12mW all-on, 1.4mW standby (`L' version) - 41mW all-on, 5.3mW standby (standard version) Low Supply Voltages - 1.8 - 3.6V Analogue Supply (`L' version) - 2.7 - 3.6V Analogue Supply (standard version) - 1.42 - 3.6V Digital Supply (both versions) Input Volume and Mute Controls ADC Sampling Frequency: 8KHz - 96KHz Selectable ADC High Pass Filter 2 or 3-Wire MPU Serial Control Interface Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths - Master or Slave Clocking Mode 20-Pin SSOP or 5x5mm QFN Package Options
*
* * * * *
*
APPLICATIONS
* * CD, Minidisc and DAT Recorders General Purpose Audio Digitisation
BLOCK DIAGRAM
SDIN CSB MODE SCLK
AVDD CONTROL INTERFACE VMID
WM8739
AGND DIGTAL AUDIO INTERFACE
RLINEIN
VOL/ MUTE
ADC
+12 to -34.5dB, 1.5dB Steps
ADCDAT ADCLRC
DIGITAL FILTERS
LLINEIN
VOL/ MUTE
ADC
BCLK
+12 to -34.5dB, 1.5dB Steps
OSC
DIV2
WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com
XTI/MCLK XTO
DCVDD
DBVDD
DGND
Advanced Information, September 2001, Rev 2.2 Copyright 2001 Wolfson Microelectronics Ltd.
WM8739 / WM8739L
Advanced Information
PIN CONFIGURATION (SSOP)
SDIN SCLK XTI/MCLK XTO DCVDD DGND DBVDD BCLK DNC DNC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CSB MODE LLINEIN RLINEIN VMID AGND AVDD NC ADCLRC ADCDAT
ORDERING INFORMATION (SSOP)
DEVICE XWM8739EDS XWM8739LEDS AVDD RANGE 2.7 to 3.6V 1.8 to 3.6V PACKAGE 20-pin SSOP 20-pin SSOP
PIN DESCRIPTION (SSOP PACKAGE)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME SDIN SCLK XTI/MCLK XTO DCVDD DGND DBVDD BCLK DNC DNC ADCDAT ADCLRC NC AVDD AGND VMID RLINEIN LLINEIN MODE CSB Supply Ground Analogue Output Analogue Input Analogue Input Digital Input Digital Input TYPE Digital Input Digital Input Digital Input Digital Output Supply Ground Supply Digital Input/Output Test pin Test pin Digital Output Digital Input/Output DESCRIPTION 3-Wire MPU Data Input / 2-Wire MPU Data Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input Crystal Input or Master Clock Input (MCLK) Crystal Output Digital Core VDD Digital GND Digital Buffers VDD Digital Audio Port Clock Do not connect (leave this pin floating) Do not connect (leave this pin floating) ADC Digital Audio Data Output ADC Sample Rate Clock No Internal Connection Analogue VDD Analogue GND Mid-rail reference decoupling point Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull up (on power up only) 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection
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WM8739 / WM8739L
Advanced Information
PIN CONFIGURATION (QFN)
AGND AVDD VMID
ORDERING INFORMATION (QFN)
DEVICE AVDD RANGE 2.7 to 3.6V 1.8 to 3.6V PACKAGE 28-pin QFN (5x5x0.9 mm)
NC
NC
NC
21 20 19 18 17 NC 22 RLINEIN 23 LLINEIN 24 MODE 25 CSB 26 SDIN 27 SCLK 28 1 XTI/MCLK 2 XTO 3 DCVDD 4 DGND 5 DBVDD
16 15 14 NC 13 NC 12 NC 11 ADCLRC 10 ADCDAT 9 DNC 8 6 NC 7 BCLK DNC
NC
XWM8739EFL XWM8739LEFL
PIN DESCRIPTION (QFN PACKAGE)
PIN 1 2 3 4 5 6 7 8, 9 10 11 12 - 17 18 19 20 21, 22 23 24 25 26 NAME XTI/MCLK XTO DCVDD DGND DBVDD NC BCLK DNC ADCDAT ADCLRC NC AVDD AGND VMID NC RLINEIN LLINEIN MODE CSB Analogue Input Analogue Input Digital Input Digital Input Supply Ground Analogue Output Digital Input/Output Test pin Digital Output Digital Input/Output TYPE Digital Input Digital Output Supply Ground Supply Crystal Output Digital Core VDD Digital GND Digital Buffers VDD No Internal Connection Digital Audio Port Clock Do not connect (leave this pin floating) ADC Digital Audio Data Output ADC Sample Rate Clock No Internal Connection Analogue VDD Analogue GND Mid-rail reference decoupling point No Internal Connection Right Channel Line Input (AC coupled) Left Channel Line Input (AC coupled) Control Interface Selection, Pull up (on power up only) 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection DESCRIPTION Crystal Input or Master Clock Input (MCLK)
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WM8739 / WM8739L ABSOLUTE MAXIMUM RATINGS
Advanced Information
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes 1. 2. 3. Analogue and digital grounds must always be within 0.3V of each other.
MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -10C -65C
MAX +3.63V +3.63 DVDD +0.3V AVDD +0.3V 18.432MHz +70C +150C +240C +183C
30C max / 85% RH max
The digital supply core voltage must always be less than or equal to the analogue supply voltage or digital supply buffer voltage. The digital supply buffer voltage must always be less than or equal to the analogue supply voltage.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply range Ground Standby Current Consumption SYMBOL DCVDD DBVDD AVDD DGND,AGND WM8739 WM8739L TEST CONDITIONS MIN 1.42 2.7 2.7 1.8 TYP 3.3 3.3 3.3 3.3 0 5 MAX 3.6 3.6 3.6 3.6 UNIT V V V V V uA
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WM8739 / WM8739L ELECTRICAL CHARACTERISTICS
Advanced Information
Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance Input to ADC Input Signal Level (0dB) VINLINE AVDD = 3.3V AVDD = 1.8V (WM8739 only) Signal to Noise Ratio (Note 1,2) SNR A-weighted, 0dB gain A-weighted, 0dB gain @ fs = 96kHz A-weighted, 0dB gain, AVDD = 2.7V A-weighted, 0dB gain, AVDD = 1.8V (WM8739L only) Dynamic Range (Note 2) Total Harmonic Distortion DNR THD A-weighted, -60dBV -1dBV input, 0dB gain -10dBV, 0dB gain ADC channel separation Programmable Gain Programmable Gain Step Size Mute attenuation Input Resistance Input Capacitance RINLINE CINLINE 0dB, 1kHz input 0dB gain 12dB gain 20k 10k 1kHz input 1kHz input Rsource < 50 Ohms -34.5 85 85 1.0 0 0.316 -10 90 90 88 76 0.545 -5.27 Vrms dB Vrms dBV dB dB dB dB VVMID RVMID AVDD/2 50K V Ohms VIL VIH VOL VOH 0.9 x VDD 0.7 x VDD 0.1 x VDD 0.3 x VDD V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
90 -84 0.006 -74 0.02 90 0 1.5 80 30k 15k 10 +12 -74 0.02
dB dB % dB % dB dB dB dB Ohms Ohms pF
Notes 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zero's into the digital input over a 20Hz to 20kHz bandwidth using an Audio analyser. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
3.
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WM8739 / WM8739L TERMINOLOGY
1. 2.
Advanced Information
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with a zero signal applied. (No `Auto-zero' or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the r.m.s. values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
3. 4.
POWER CONSUMPTION
POWEROFF LINEINPD OSCPD ADCPD MODE DESCRIPTION TYP. SUPPLY CURRENTS (MILLIAMPS)
IAVDD
IDBVDD
IDCVDD
POWER (mW) 41.12 5.31 5.30 0.097
WM8739 (AVDD = 3.3V, DBVDD = 3.3V, DCVDD = 1.5V) ADC Running Standby Power Down Power Down, Oscillator disabled ADC Running Standby Power Down Power Down, Oscillator disabled 0 0 1 1 0 0 0 1 0 1 X X 0 1 X X 9.79 0.014 0.001 0.001 1.58 1.56 1.57 0.003 2.40 0.074 0.074 0.056
WM8739L (AVDD = 1.8V, DBVDD = 1.8V, DCVDD = 1.42V) 0 0 1 1 0 0 0 1 0 1 X X 0 1 X X 3.93 0.007 0.001 0.001 0.875 0.755 0.755 <1A 2.35 0.018 0.018 <1A 11.99 1.397 1.386 0.002
Table 1 Powerdown Mode Current Consumption Examples
Notes 1. 2. TA = +25oC. Slave Mode, fs = 48kHz, XTI/MCLK = 256fs (12.288MHz). All figures are quiescent, with no signal.
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WM8739 / WM8739L DIGITAL AUDIO INTERFACE TIMING
tXTIL XTI/MCLK tXTIH tXTIY
Advanced Information
Figure 1 System Clock Timing Requirements Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
XTI/MCLK System clock pulse width high XTI/MCLK System clock pulse width low XTI/MCLK System clock cycle time
SYMBOL TXTIH TXTIL TXTIY
TEST CONDITIONS
MIN 20 20 50
TYP
MAX
UNIT ns ns ns
BCLK DSP ENCODER
WM8739 ADCLRC ADC
ADCDAT
Figure 2 Master Mode Connection
BCLK (Output) tDL ADCLRC (Output) tDDA ADCDAT
Figure 3 Digital Audio Data Timing - Master Mode
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WM8739 / WM8739L
Test Conditions
Advanced Information
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER ADCLRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge SYMBOL tDL tDDA TEST CONDITIONS MIN 0 0 TYP MAX 10 10 UNIT ns ns
Audio Data Input Timing Information
BCLK
WM8739 ADCLRC ADC
DSP ENCODER
ADCDAT
Figure 4 Slave Mode Connection
tBCH BCLK tBCY
tBCL
ADCLRC tDD ADCDAT tLRH tLRSU
Figure 5 Digital Audio Data Timing - Slave Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low ADCLRC set-up time to BCLK rising edge ADCLRC hold time from BCLK rising edge ADCDAT propagation delay from BCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDD TEST CONDITIONS MIN 50 20 20 10 10 0 10 TYP MAX UNIT ns ns ns ns ns ns
Audio Data Input Timing Information
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WM8739 / WM8739L MPU INTERFACE TIMING
tCSL CSB tSCY tSCH SCLK tSCL tSCS tCSS
Advanced Information
tCSH
SDIN tDSU tDHO
LSB
Figure 6 Program Register Input Timing - 3-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS TEST CONDITIONS MIN 500 80 20 20 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Program Register Input Information
t3 SDIN
t5 t4 t6 t2
t3
t8
SCLK t1 t9 t7
Figure 7 Program Register Input Timing - 2-Wire MPU Serial Control Mode
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WM8739 / WM8739L
Test Conditions
Advanced Information
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time t1 t2 t3 t4 t5 t6 t7 t8 t9 600 900 SYMBOL TEST CONDITIONS MIN 0 600 1.3 600 600 100 300 300 TYP MAX 400 UNIT kHz ns us ns ns ns ns ns ns ns
Program Register Input Information
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WM8739 / WM8739L DEVICE DESCRIPTION
INTRODUCTION
Advanced Information
The WM8739 is a low power analogue to digital converter (ADC) designed for audio recording. Its features, performance and low power consumption make it ideal for recordable CD players, MP3 players and portable mini-disc players. The device includes programmable level line inputs, a crystal oscillator, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The WM8739 has low noise line inputs with programmable +12dB to -34.5dB logarithmic volume adjustments and mute. The ADC is of a high quality using a multi-bit high-order oversampling architecture delivering optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes a digital high pass filter to remove unwanted dc components from the audio signal. The design of the WM8739 has given much attention to power consumption without compromising performance. It includes the ability to power off parts of the circuitry under software control, including a standby and power off mode. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. There are two unique schemes featured within the programmable sample rates of the WM8739: Normal industry standard 256/384 fs sampling mode may be used. A special USB sampling mode is also included, whereby all audio sampling rates can be generated from a 12.00MHZ USB clock. The WM8739's unique sample rate converter thus allows the user to generate the required sampling rate clocks from the 12MHz USB clock. The digital filters used for recording are optimised for each sampling rate used. The digitised output is available in a number of audio data formats I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The WM8739 can generate the system master clock using an on-chip crystal oscillator, or alternatively it can accept an external master clock from the audio system. All features are software controlled using either a 2 or 3-wire MPU interface.
LINE INPUTS
The WM8739 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external Hi-Fi and other audio equipment. Both line inputs include independent programmable volume level adjustments and mutes. The scheme is illustrated in Figure 8. Passive RF and active Anti-Alias filters are also incorporated within the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading performance.
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WM8739 / WM8739L
Advanced Information
LINEIN
12.5K
VMID
To ADC
Figure 8 Line Input Schematic
LINE INPUT SCHEMATIC
The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to -34.5dB in 1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both channels are simultaneously updated. Use of INBOTH reduces the required number of software writes required. The line inputs can be muted in the analogue domain under software control. The software control registers are shown below.
REGISTER ADDRESS 0000000 Left Line In
BIT 4:0
LABEL LINVOL[0:4]
DEFAULT 10111 ( 0dB )
DESCRIPTION Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute 1 = Enable Mute 0 = Disable Mute Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[0:4] and LINMUTE to RINVOL[0:4] and RINMUTE 0 = Disable Simultaneous Load Right Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute 1 = Enable Mute 0 = Disable Mute Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[0:4] and RINMUTE to LINVOL[0:4] and LINMUTE 0 = Disable Simultaneous Load
7
LINMUTE
1
8
LRINBOTH
0
0000001 Right Line In
4:0
RINVOL[0:4]
10111 ( 0dB )
7
RINMUTE
1
8
RLINBOTH
0
Table 2 Line Input Software Control
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WM8739 / WM8739L
Advanced Information
The line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs. The external components required to complete the line input application are shown in the Figure 9.
R1
C2 LINEIN
AGND
R2
C1
AGND
AGND
Figure 9 Line Input Application Drawing For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there is no clipping at the input. R1 = 5K, R2= 5K, C1=47pF, C2=470nF (10V ceramic type). R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level, so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the input to C2 charging to an excessive voltage which may otherwise damage any equipment connected that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove the DC path between the WM8739 and the driving audio equipment. C2 together with the input impedance of the WM8739 form a high pass filter.
ADC
The WM8739 uses a multi-bit illustrated in the Figure 10. oversampled sigma-delta ADC. A single channel of the ADC is
FROM LINE INPUT
ANALOG INTEGRATOR
TO ADC DIGITAL FILTERS
MULTI BITS
Figure 10 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise.
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WM8739 / WM8739L
Advanced Information
The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The device employs a pair of ADCs. The two channels cannot be selected independently. The digital data from the ADC is fed for signal processing to the ADC Filters.
ADC FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 11 illustrates the digital filter path.
FROM ADC
DIGITAL DECIMATOR
DIGITAL FILTER
DIGITAL HPF
TO DIGITAL AUDIO INTERFACE
HPFEN
Figure 11 ADC Digital Filter
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changed, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 3. REGISTER ADDRESS 0000101 Audio Path Control BIT 0 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset
4
HPOR
0
Table 3 ADC Software Control There are several types of ADC filter, the frequency and phase responses of which are shown in Digital Filter Characteristics. The filter types are automatically configured depending on the sample rate chosen. Refer to the sample rate section for more details.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. To allow WM8739 to be used in a centrally clocked system, the WM8739 is capable of either generating this `system' clock itself or receiving it from an external source as will be discussed. For applications where it is desirable that the WM8739 is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section). AI Rev 2.2 September 2001 14
WM8739 / WM8739L
Advanced Information
For applications where a component other than the WM8739 will generate the reference clock, the external system can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8739 can be safely powered down to conserve power (see POWER DOWN section)
CRYSTAL OSCILLATOR
The WM8739 includes a crystal oscillator circuit that allows the audio system's reference clock to be generated on the device. The crystal oscillator is a low radiation type, designed for low EMC. A typical application circuit is shown in Figure 12.
XTI/MCLK
XTO
Cp DGND
Cp DGND
Figure 12 Crystal Oscillator Application Circuit For crystals with a 30pF fundamental load capacitance, a value of 5pF for Cp is recommended. The WM8739 crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for a high quality audio ADC, regardless of the converter architecture. The WM8739 architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8739 to minimise such problems.
CORE CLOCK
The WM8739 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 4 below. REGISTER ADDRESS 0001000 Sampling Control 6 BIT LABEL CLKIDIV2 0 DEFAULT DESCRIPTION Core Clock divider select 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK
Table 4 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode.
DIGITAL AUDIO INTERFACES
WM8739 may be operated in either one of the 4 offered audio interface modes. These are: * * * * Right justified Left justified I2S DSP mode
All four of these modes are MSB first.
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Advanced Information
The digital audio interface takes the data from the internal ADC digital filters and places it on ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. ADCDAT is always an output. BCLK and ADCLRC maybe an input or an output depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section. There are four digital audio interface formats accommodated by the WM8739. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a LRCLK transition.
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
ADCDAT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK transition.
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
1 BCLK
1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
ADCDAT
1
2
MSB
LSB
MSB
LSB
Figure 14 I2S Mode Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK transition, yet MSB is still transmitted first.
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Advanced Information
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
ADCDAT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 15 Right Justified Mode DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK (selectable by LRP) following a LRCLK transition high. Right channel data immediately follows left channel data.
1/fs 1 BCLK
ADCLRC
BCLK
LEFT CHANNEL ADCDAT
1 2 3 n-2 n-1 n 1 2
RIGHT CHANNEL
3 n-2 n-1 n
MSB
Input Word Length (IWL)
LSB
Note: Input word length is defined by the IWL register, LRP = 1
Figure 16 DSP Mode The ADC digital audio interface modes are software configurable as indicated in Figure 16. Note that dynamically changing the software format may results in erroneous operation of the interfaces and is therefore not recommended. The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2's complement. The ADC digital filters process data using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. ADCDAT is always an output. It powers up and returns from standby `low'. ADCLRC and BCLK can be either outputs or inputs depending on whether the device is configured as a master or slave. If the device is a master then the ADCLRC and BCLK signals are outputs that default low. If the device is a slave then the ADCLRC and BCLK are inputs.
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Advanced Information
REGISTER ADDRESS
BIT
LABEL FORMAT[1:0]
DEFAULT 10
DESCRIPTION Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after LRC rising edge 0 = MSB is available on 1st BCLK rising edge after LRC rising edge Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode
0000111 1:0 Digital Audio Interface Format
3:2
IWL[1:0]
10
4
LRP
0
6
MS
0
Table 5 Digital Audio Interface Control Note: Right justified 32 bit mode is not supported, but if selected, will put the WM8739 into 24 bit right justified mode.
MASTER AND SLAVE MODE OPERATION
The WM8739 can be configured as either a master or slave mode device. As a master mode device the WM8739 controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8739 responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 6. REGISTER ADDRESS 0000111 Digital Audio Interface Format 6 BIT MS LABEL 0 DEFAULT DESCRIPTION Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode
Table 6 Programming Master/Slave Modes As a master mode device the WM8739 controls the sequencing of data transfer (ADCDAT) and output of clocks (BCLK, ADCLRC) over the digital audio interface. It uses the timing generated from either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 17. ADCDAT is always an output from the WM8739 independent of master or slave mode.
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Advanced Information
BCLK DSP ENCODER
WM8739 ADCLRC ADC
ADCDAT
Figure 17 Master Mode As a slave device the WM8739 sequences the data transfer (ADCDAT) over the digital audio interface in response to the external applied clocks (BCLK, ADCLRC). This is illustrated Figure 18.
BCLK
WM8739 ADCLRC ADC
DSP ENCODER
ADCDAT
Figure 18 Slave Mode
AUDIO DATA SAMPLING RATES
The WM8739 provides for two modes of operation (normal and USB) to generate the required ADC sampling rate. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal frequency and the sample rate control register setting. The WM8739 can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8739 can be directly used within such systems. WM8739 can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits.
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Advanced Information
REGISTER ADDRESS 0001000 Sampling Control 0
BIT
LABEL USB/ NORMAL BOSR
DEFAULT 0
DESCRIPTION Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs Normal Mode 0 = 256fs 1 = 384fs
1
0
5:2
SR[3:0]
0000
ADC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation
Table 7 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK/crystal oscillator is set up according to the desired sample rate of the ADC. For ADC sampling rates of 8, 32, 48 or 96KHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC sampling rates of 8, 44.1 or 88.2KHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used. The table below should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8739 in normal mode with the ADC sample rate at 48KHz, then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC will then operate with a Digital Filter of type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types. SAMPLING RATE kHz 48 8 32 96 44.1 8 (Note 1) 88.2 MCLK FREQUENCY MHz 12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 11.2896 16.9344 11.2896 16.9344 11.2896 16.9344 BOSR 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAMPLE RATE REGISTER SETTINGS SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 SR1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 SR0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 2 1 1 2 1 1 1 DIGITAL FILTER TYPE
Table 8 Normal Mode Sample Rate Look-up Table Notes: 1. 2. 8k not exact, actual = 8.018kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8739 digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate produced by the ADC.
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Example scenarios are: 1.
Advanced Information
with a requirement that the ADC data rate is 8kHz, then choosing MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6) with a requirement that ADC data rate is 8kHz, then choosing MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 0, SR0 = 1. The ADC will no longer output data at exactly 8.000KHz, instead it will be 8.018kHz (derived from 16.9344MHz/384 x 2/11). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018kHz rate.
2.
The exact sample rates achieved are defined by the relationships in Table 9. TARGET SAMPLING RATE MCLK=12.288 kHz 8 32 44.1 48 88.2 96 kHz 8
12.288MHz/256 x 1/6
ACTUAL SAMPLING RATE BOSR=0 (256fs) MCLK=11.2896 kHz 8.018
11.2896MHz/256 x 2/11
BOSR=1 (384fs) MCLK=18.432 kHz 8
18.432MHz/384 x 1/6
MCLK=16.9344 kHz 8.018
16.9344MHz/384 x 2/11
32
12.288MHz/256 x 2/3
not available 44.1
11.2896MHz/256
32
18.432MHz/384x 2/3
not available 44.1
16.9344MHz /384
not available 48
12.288MHz/256
not available 48
18.432MHz/384
not available 88.2
11.2896MHz/384 x 2
not available 88.2
16.9344MHz /384 x 2
not available 96
12.288MHz/256 x 2
not available 96
18.432MHz/384 x 2
not available
not available
Table 9 Normal Mode Actual Sample Rates
128/192fs NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8739 is also capable of being clocked from a 128/192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE kHz 48 44.1 MCLK FREQUENCY MHz 6.144 9.216 5.6448 8.4672 BOSR 0 1 0 1 SAMPLE RATE REGISTER SETTINGS SR3 0 0 1 1 SR2 1 1 1 1 SR1 1 1 1 1 SR0 1 1 1 1 2 2 DIGITAL FILTER TYPE
Table 10 128/192fs Normal Mode Sample Rate Look-up Table
512/768fs NORMAL MODE
512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 4 for software control.
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USB MODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only. SAMPLING RATE kHz 48 44.1 (Note 2) 8 8 (Note 1) 32 96 88.2 (Note 3) MCLK FREQUENCY MHz 12.000 12.000 12.000 12.000 12.000 12.000 12.000 BOSR 0 1 0 1 0 0 1 SAMPLE RATE REGISTER SETTINGS SR3 0 1 0 1 0 0 1 SR2 0 0 0 0 1 1 1 SR1 0 0 1 1 1 1 1
Advanced Information
DIGITAL FILTER TYPE SR0 0 0 0 0 0 1 1 0 1 0 1 0 3 2
Table 11 USB Mode Sample Rate Look-up Table Notes: 1. 2. 3. 4. 8k not exact, actual = 8.021kHz 44.1k not exact, actual = 44.118kHz 88.2k not exact, actual = 88.235kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8739 in USB mode with the ADC sample rate at 48kHz, then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0. The ADC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section for an explanation of the different filter types. The BOSR bit represents the base over-sampling rate. This is the rate that the WM8739 digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base oversampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate produced by the ADC. Example scenarios are: 1. with a requirement that the ADC data sampling rate is 8KHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC will then be exactly 8kHz (derived from 12MHz/250 x 1/6). with a requirement that ADC data rate is 8KHz the device is programmed with BOSR = 1 (272fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8kHz, instead it will be 8.021kHz (derived from 12MHz/272 x 2/11). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and (more importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.021kHz rate.
2.
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Advanced Information
The exact sample rates supported for all combinations are defined by the relationships in Table 12 below. TARGET SAMPLING RATE kHz 8 32 44.1 48 88.2 96 ACTUAL SAMPLING RATE BOSR=0 ( 250fs) kHz 8
12MHz/(250 x 48/8)
BOSR=1 (272fs) kHz 8.021
12MHz/(272 x 11/2)
32
12MHz/(250 x 48/32)
not available 44.117
12MHz/272
not available 48
12MHz/250
not available 88.235
12MHz/136
not available 96
12MHz/125
not available
Table 12 USB Mode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface the Audio Interface is disabled (tristate). Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS 0001001 Active Control 0 BIT LABEL ACTIVE 0 DEFAULT DESCRIPTION Activate Interface 1 = Active 0 = Inactive
Table 13 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of the CSB pin allows the user to select one of two addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire mode. This is achieved by setting the state of the MODE pin. MODE 0 1 INTERFACE FORMAT 2 wire 3 wire
Table 14 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
The WM8739 can be controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. The 3-wire interface protocol is shown in Figure 19.
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Advanced Information
CSB SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 19 3-Wire Serial Interface Notes: 1. 2. B[15:9] are Control Address Bits B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8739 supports a 2-wire MPU serial interface. The device operates as a slave device only. The WM8739 has one of two slave addresses that are selected by setting the state of pin 20, (CSB).
SDIN SCLK START
R ADDR
R/W
ACK
DATA B15-8
ACK
DATA B7-0
ACK
STOP
Figure 20 2-Wire Serial Interface Notes: 1. 2. B[15:9] are Control Address Bits B[8:0] are Control Data Bits
CSB STATE (DEFAULT = LOW) 0 1
ADDRESS 0011010 0011011
Table 15 2-Wire MPU Interface Address Selection To control the WM8739 on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high. This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see Table 15). If the correct address is received and the R/W bit is `0', indicating a write, then the WM8739 will respond by pulling SDIN low on the next clock pulse (ACK). The WM8739 is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. Once the WM8739 has acknowledged a correct address, the controller will send eight data bits (bits B[15]-B[8]). WM8739 will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8739 will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. AI Rev 2.2 September 2001 24
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Advanced Information
After receiving a complete address and data sequence the WM8739 returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits.
POWER DOWN MODES
The WM8739 contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS 0000110 Power Down Control 0 BIT LABEL LINEINPD DEFAULT 1 DESCRIPTION Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down ADC Power Down 1 = Enable Power Down 0 = Disable Power Down Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down Power Off Device 1 = Device Power Off 0 = Device Power On
2
ADCPD
1
5
OSCPD
0
7
POWEROFF
1
Table 16 Power Conservation Modes Software Control Unused register bits 1,3,4,6 should be set to `1' when writing to this register. The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used. OSCPD: Powers off the on board crystal oscillator. The MCLK input will function independently of the Oscillator being powered down. The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 17.
POWEROFF
DESCRIPTION LINEINPD OSCPD ADCPD
0 0
0 1
1 1
1 1
STANDBY, but with Crystal Oscillator STANDBY, Crystal oscillator not-available.
Table 17 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line inputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode.
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Advanced Information
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. As in STANDBY mode the crystal oscillator pin can be independently controlled. Refer to Table 18. POWEROFF DESCRIPTION LINEINPD OSCPD ADCPD
1 1
0 1
X X
X X
POWEROFF, but with Crystal Oscillator OSC available POWEROFF, Crystal oscillator not-available
Table 18 Power Off Mode
DEVICE RESETTING
The WM8739 contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS 0001111 Reset Register BIT 8:0 LABEL RESET DEFAULT not reset DESCRIPTION Reset Register Writing 00000000 to register resets device
Table 19 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 20).
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REGISTER MAP
Advanced Information
The complete register map is shown in Table 20. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER B 15 0 0 0 0 0 0 0 0 B 14 0 0 0 0 0 0 0 0 B 13 0 0 0 0 0 0 0 0 B 12 0 0 0 0 0 1 1 1 ADDRESS B 11 0 0 1 1 1 0 0 1 B 10 0 0 0 1 1 0 0 1 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
R0 (00h) R1 (02h) R5 (0Ah) R6 (0Ch) R7 (0Eh) R8 (10h) R9 (12h) R15(1Eh)
0 1 1 0 1 0 1 1
LRIN LIN BOTH MUTE RLIN RIN BOTH MUTE 0 0 0 0 0 0 PWR OFF 0 0 0
0 0 0 1 MS CLKI DIV2 0
0 0 0 OSCPD 0 HPOR 1 LRP SR 0 0 RESET DATA 0 0 1
LINVOL RINVOL 0 ADCPD IWL 0 1 ADC HPD LINEIN PD USB/ NORM ACTIVE
FORMAT BOSR 0 0
REGISTER ADDRESS 0000000 Left Line In
BIT 4:0
LABEL LINVOL[0:4]
DEFAULT 10111 ( 0dB ) 1
DESCRIPTION Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute 1 = Enable Mute 0 = Disable Mute Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[0:4] and LINMUTE to RINVOL[0:4] and RINMUTE 0 = Disable Simultaneous Load Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB Left Channel Line Input Mute 1 = Enable Mute 0 = Disable Mute Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[0:4] and RINMUTE to LINVOL[0:4] and LINMUTE 0 = Disable Simultaneous Load
7
LINMUTE
8
LRINBOTH
0
0000001 Right Line In
4:0
RINVOL[0:4]
10111 ( 0dB )
7
RINMUTE
1
8
RLINBOTH
0
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REGISTER ADDRESS BIT LABEL ADCHPD DEFAULT 0
Advanced Information DESCRIPTION ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down ADC Power Down 1 = Enable Power Down 0 = Disable Power Down Oscillator Power Down 1 = Enable Power Down 0 = Disable Power Down POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after LRC rising edge 0 = MSB is available on 1st BCLK rising edge after LRC rising edge Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Mode Select 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs 5:2 SR[3:0] 0000 (fs) 0 Normal Mode 0 = 256fs 1 = 384fs
0000101 0 Digital Audio Path Control 4
HPOR
0
0000110 Power Down Control
0
LINEINPD
1
2
ADCPD
1
5
OSCPD
0
7
POWEROFF
1
0000111 Digital Audio Interface Format
1:0
FORMAT[1:0]
10
3:2
IWL[1:0]
10
4
LRP
0
6
MS
0
0001000 Sampling Control
0
USB/ NORMAL BOSR
0
1
0
ADC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Core Clock divider select 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK
6
CLKIDIV2
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REGISTER ADDRESS 0001001 Active Control 0001111 Reset Register BIT 0 LABEL ACTIVE DEFAULT 0
Advanced Information DESCRIPTION Activate Interface 1 = Active 0 = Inactive Reset Register Write 000000000 to register triggers reset
8:0
RESET
not reset
Table 20 Register Map Description Note 1. All other bits not explicitly defined in the register table should be set to zero, unless specified otherwise (see Powerdown section).
DIGITAL FILTER CHARACTERISTICS
The ADC employs different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation High Pass Filter Corner Frequency f > 0.5465fs -3dB -0.5dB -0.1dB 0.5465fs -60 3.7 10.4 21.6 dB Hz f > 0.584fs +/- 0.05dB -6dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) 0 0.5fs +/- 0.05 dB 0.4535fs 0.584fs -60 dB TEST CONDITIONS +/- 0.05dB -6dB MIN 0 0.5fs +/- 0.05 dB TYP MAX 0.416fs UNIT
ADC Filter Type 0 (USB Mode, 250fs operation)
Table 21 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple - any variation of the frequency response in the pass-band region
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WM8739 ADC FILTER RESPONSES
0.02 0 0.01 -20 0
Response (dB)
Advanced Information
Response (dB)
-0.01 -0.02 -0.03 -0.04
-40
-60
-80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 21 ADC Digital Filter Frequency Response -Type 0
Figure 22 ADC Digital Filter Ripple -Type 0
0.02 0 0.01 -20 0
Response (dB)
Response (dB)
-0.01 -0.02 -0.03 -0.04
-40
-60
-80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 23 ADC Digital Filter Frequency Response -Type 1
Figure 24 ADC Digital Filter Ripple -Type 1
0.02 0 0.01 -20 0
Response (dB)
Response (dB)
-0.01 -0.02 -0.03 -0.04
-40
-60
-80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 25 ADC Digital Filter Frequency Response -Type 2
Figure 26 ADC Digital Filter Ripple -Type 2
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0.02 0 0.01 -20 0
Response (dB)
Advanced Information
Response (dB)
-0.01 -0.02 -0.03 -0.04
-40
-60
-80 -0.05 -100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 27 ADC Digital Filter Frequency Response -Type 3
Figure 28 ADC Digital Filter Ripple -Type 3
ADC HIGH PASS FILTER
The WM8739 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H(z) = 1 - z-1 1 - 0.9995 z-1
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WM8739 RECOMMENDED EXTERNAL COMPONENTS
3.3V
7
Advanced Information
3.3V 0.1F
15
6
DGND
AGND
10F
0.1F
5
+
1.5V - 3.3V
DCVDD
+
LLINEIN
18
WM8739 ADC
11 12 8
470nF 47pF
5K
+
17
Audio Serial Data I/F
ADCDAT ADCLRC BCLK
RLINEIN
470nF 47pF 5K
3-wire Interface 2-wire Interface
3.3V 10k
19 20 1 2
3-wire or 2-wire MPU Interface
MODE CSB SDIN SCLK VMID
16
0.1F
+
10F
XTI/MCLK XTO
3 4
15pF
15pF
Notes: 1. AGND and DGND should be connected as close to the WM8739 as possible. 2. 0.1F capacitors should be positioned as close the the WM8739 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.
Figure 29 External Components Diagram
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+
10F 5K 5K
10F
+
0.1F
DBVDD
AVDD
14
WM8739 / WM8739L PACKAGE DIMENSIONS (SSOP)
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
Advanced Information
DM0015.A
b
20
e
11
E1
E
GAUGE PLANE 1 10
D 0.25 c A A2 A1 -C0.10 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 o 0
Dimensions (mm) NOM --------1.75 --------7.20 0.65 BSC 7.80 5.30 0.75 o 4 JEDEC.95, MO-150
MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
AI Rev 2.2 September 2001 33
WM8739 PACKAGE DIMENSIONS (QFN)
FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 1 mm BODY, 0.50 mm LEAD PITCH
TOP VIEW
D2 B 22 D2/2 27 28 L INDEX AREA (D/2 X E/2) D
Advanced Information
DM023.B
21
1 2 E2/2
A
A
E2
E
15
7 SEE DETAIL B 2X 14 e 13 B 8 b ccc
M
aaa C aaa C
CAB
2X
DETAIL B
DATUM ccc C A 0.08 C A1 (A3) SEATING PLANE R
C
e
TERMINAL TIP 1
Symbols A A1 A3 b D D2 E E2 e L R aaa ccc REF: MIN 0.80 0 0.18 3.2 3.2
0.35 b(min)/2 Tolerances of Form and Position 0.15 0.10
JEDEC.95, MO-220, VARIATION VHHD-1
Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 BSC 3.3 3.4 5.00 BSC 3.3 3.4 0.5 BSC 0.4 0.45
NOTE
2 1 2 2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC.95, MO-220 WITH THE EXCEPTION OF D2, E2, A3: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION A3: NOMINAL VALUE LESS THAN JEDEC 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
AI Rev 2.2 September 2001 34
WM8739 / WM8739L IMPORTANT NOTICE
Advanced Information
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 667 9386 Fax :: +44 (0)131 667 5176 Email :: sales@wolfsonmicro.com
AI Rev 2.2 September 2001 35

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