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Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications.
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 200 5.0 60 0.9 UNIT V A W
PINNING - SOT428
PIN 1 2 3 tab gate drain source DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
2
drain
1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ID IDM PD PD/Tmb VGS EAS IAS Tj, Tstg Continuous drain current Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C Tmb > 25 C VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V MIN. - 55 MAX. 5 3.5 20 60 0.4 30 40 5 175 UNIT A A A W W/K V mJ A C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 2.5 UNIT K/W K/W
October 1997
1
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
ELECTRICAL CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL V(BR)DSS V(BR)DSS / Tj RDS(ON) VGS(TO) gfs IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss PARAMETER Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current Gate-source leakage current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 2.5 A VDS = VGS; ID = 0.25 mA VDS = 50 V; ID = 2.5 A VDS = 200 V; VGS = 0 V VDS = 160 V; VGS = 0 V; Tj = 150 C VGS = 30 V; VDS = 0 V ID = 4.8 A; VDD = 160 V; VGS = 10 V MIN. 200 2.0 1.5 TYP. 0.25 0.68 3.0 3.5 0.1 1 10 11 2 5.3 7 29 27 22 3.5 7.5 300 60 20 MAX. 0.9 4.0 25 250 100 15 3 7 UNIT V V/K V S A A nA nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 100 V; ID = 4.8 A; RG = 18 ; RD = 20
Measured from tab to centre of die Measured from source lead solder point to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL IS ISM VSD trr Qrr PARAMETER Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 5.2 A; VGS = 0 V IS = 4.8 A; VGS = 0 V; dI/dt = 100 A/s MIN. TYP. 114 0.8 MAX. 5 20 1.5 UNIT A A V ns C
October 1997
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1E+01
Zth j-mb / (K/W)
BUKX52
1E+00
0.5
0.2 0.1 0.05 1E-01 0.02 0
0 20 40 60 80 100 Tmb / C 120 140 160 180
P D
tp
D=
tp T t
1E-02 1E-07
T
1E-05
1E-03 t/s
1E-01
1E+01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
10
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
120 110 100 90 80 70 60 50 40 30 20 10 0
ID, Drain current (Amps) 10 V 7V Tj = 25 C
PHP5N20 6V
8 5.5 V 6 5V 4 VGS = 4.5 V 2
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
0
5
10 15 20 VDS, Drain-Source voltage (Volts)
25
30
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V
ID, Drain current (Amps) PHP5N20E
Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms) 4.5 V 5V 5.5 V
100
3 2.5
PHP5N20 6V 7V
10
RD
S(
ON
)
D =V
S/
ID
tp = 10 us 100 us 1 ms
2 1.5 VGS = 10 V 1 0.5 Tj = 25 C 0
1
DC
10 ms 100 ms
0.1
1
10 100 VDS, Drain-source voltage (Volts)
1000
0
2
4 6 ID, Drain current (Amps)
8
10
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS
October 1997
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
12 10
ID, Drain current (Amps) VDS = 30 V
PHP5N20E Tj = 25 C
4
VGS(TO) / V max.
typ.
8 6 4
3
Tj = 175 C
min. 2
1
2 0
0
0
2 4 6 VGS, Gate-source voltage (Volts)
8
10
-60
-20
20
60 Tj / C
100
140
180
Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj
gfs, Transconductance (S) VDD = 30 V 4 Tj = 25 C 3 Tj = 175 C 2 PHP5N20E
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
ID / A SUB-THRESHOLD CONDUCTION
5
1E-01
1E-02
1E-03
2%
typ
98 %
1E-04
1
1E-05
0
1E-06
0
2
4 6 8 ID, Drain current (Amps)
10
12
0
1
2 VGS / V
3
4
Fig.8. Typical transconductance. gfs = f(ID); parameter Tj
a Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Ciss, Coss, Crss, Junction capacitances (pF) PHP5N20E Ciss Coss Crss
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
1000
100
10
-60
-20
20
60 Tj / C
100
140
180
1
1
10 100 VDS, Drain-source voltage (Volts)
1000
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 2.5 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
October 1997
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
15
VGS, Gate-Source voltage (Volts) ID = 4.8 A Tj = 25 C VDS = 40 V 100 V
PHP5N20E 160 V
20
IF, Source-drain diode current (Amps) VGS = 0 V
PHP5N20E
15
10
Tj = 175 C 10
5
Tj = 25 C
5
0
0
5
10 Qg, Gate charge (nC)
15
20
0
0
0.5 1 VSDS, Source-drain voltage (Volts)
1.5
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS
Switching times (ns) PHP5N20E
Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
100
tr td(off) tf 10 td(on) VDD = 100 V VGS = 10 V RD = 20 Ohms ID = 4.8 A Tj = 25 C 20 40 60 RG, Gate resistance (Ohms) 80 100
120 110 100 90 80 70 60 50 40 30 20 10 0
1
0
20
40
60
80
Starting Tj ( C)
100
120
140
160
180
Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj V(BR)DSS @ 25 C
Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj)
1.15 1.1 1.05 1 0.95 0.9
+
L VDS VGS 0 RGS T.U.T. R 01 shunt
VDD
-ID/100
0.85 -100
-50
0 50 Tj, Junction temperature (C)
100
150
Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 C = f(Tj)
Fig.18. Unclamped inductive test circuit. 2 EAS = 0.5 LID V(BR)DSS /(V(BR)DSS - VDD )
October 1997
5
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane 6.73 max 1.1 2.38 max 0.93 max 5.4
tab
4 min 6.22 max 10.4 max 4.6
2 1 3
0.5 min 0.3 0.5
0.5
0.8 max (x2) 2.285 (x2)
Fig.19. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15 2.5
1.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
October 1997
6
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
October 1997
7
Rev 1.100

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