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HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S
Data Sheet March 2003
75A, 55V, 0.009 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel power MOSFETs are manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery operated products. Formerly developmental type TA75343.
Features
* 75A, 55V * Simulation Models - Temperature Compensating PSPICE(R) and SABERTM Models - Thermal Impedance PSPICETM and SABER Models Available on the WEB at: www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER HUF75343G3 HUF75343P3 HUF75343S3 HUF75343S3S PACKAGE TO-247 TO-220AB TO-262AA TO-263AB BRAND 75343G 75343P 75343S 75343S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75343S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (TAB)
JEDEC TO-263AB
JEDEC TO-262AA
SOURCE DRAIN GATE
GATE SOURCE
DRAIN (FLANGE)
DRAIN (FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2003 Fairchild Semiconductor Corporation HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified 55 55 20 75 Figure 4 Figure 6 270 1.81 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 11) VDS = 50V, VGS = 0V VDS = 45V, VGS = 0V, TC = 150oC
55 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 75A, VGS = 10V (Figure 9)
2 -
0.007
4 0.009
V
RJC RJA
(Figure 3) TO-247 TO-220, TO-263
-
-
0.55 30 62
oC/W oC/W oC/W
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 30V, ID 75A, RL = 0.4 Ig(REF) = 1.0mA (Figure 13) 170 92 6.0 13 42 205 110 7.2 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 30V, ID 75A, RL = 0.4, VGS = 10V, RGS = 2.5 9 75 32 18 125 75 ns ns ns ns ns ns
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S
Electrical Specifications
PARAMETER CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 3000 1100 230 pF pF pF TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 75A ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 100 200 UNITS V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 60 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) 80
40
20
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
PDM
0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
0.01 10-5
SINGLE PULSE 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Typical Performance Curves
2000
(Continued)
TC = 25oC
IDM, PEAK CURRENT (A)
1000
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150
VGS = 10V
100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
50 10-5
FIGURE 4. PEAK CURRENT CAPABILITY
500 1000 IAS, AVALANCHE CURRENT (A) TJ = MAX RATED TC = 25oC
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID, DRAIN CURRENT (A)
100
100s
100 STARTING TJ = 25oC
1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS(MAX) = 55V 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200 10ms
STARTING TJ = 150oC
10 0.01
0.1 1 tAV, TIME IN AVALANCHE (ms)
10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
150 VGS = 20V VGS = 10V VGS = 7V 100 VGS = 6V
150
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VDD = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
-55oC
175oC
100
50
VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
50
25oC 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Typical Performance Curves
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A 2.0 NORMALIZED GATE THRESHOLD VOLTAGE 1.0
(Continued)
1.2 VGS = VDS, ID = 250A
1.5
0.8
1.0
0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.6 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A C, CAPACITANCE (pF)
4000
3000 CISS 2000 COSS 1000 CRSS
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
1.1
1.0
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
0 0 10 20 30 40 50 60 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 47A ID = 18A 80 100
2 VDD = 30V 0 0 20
60 40 Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT IG(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S PSPICE Electrical Model
.SUBCKT HUF75343 2 1 3 ;
CA 12 8 3.95e-9 CB 15 14 5.05e-9 CIN 6 8 2.68e-9
10
rev 9Feb99
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 58.39 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.60e-9 LSOURCE 3 7 1.1e-9 KGATE LSOURCE LGATE 0.0085 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 0.70e-3 RGATE 9 20 0.36 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.79e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*609),2.5))} .MODEL DBODYMOD D (IS = 2.35e-12 RS = 2.21e-3 TRS1 = 2.47e-3 TRS2 = 3.97e-11 CJO = 6.34e-9 TT = 3.95e-8 M = 0.6) .MODEL DBREAKMOD D (RS = 9.1e-2 TRS1 = -2.24e-4 TRS2 = 5.23e-6) .MODEL DPLCAPMOD D (CJO = 2.15e-9 IS = 1e-30 N = 10 M= 0.73) .MODEL MMEDMOD NMOS (VTO = 3.30 KP = 5.49 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36) .MODEL MSTROMOD NMOS (VTO = 3.87 KP = 145 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.92 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6 RS =.1) .MODEL RBREAKMOD RES (TC1 = 1.04e-3 TC2 = 3.43e-7) .MODEL RDRAINMOD RES (TC1 = 4.44e-2 TC2 = 8.04e-5) .MODEL RSLCMOD RES (TC1 = 1.02e-4 TC2 = 2.07e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -3.49e-3 TC2 = -1.27e-5) .MODEL RVTEMPMOD RES (TC1 = -1.93e-3 TC2 = 1.38e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.90 VOFF= -3.90) VON = -3.90 VOFF= -6.90) VON = 0.39 VOFF= 3.39) VON = 3.39 VOFF= 0.39)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2003 Fairchild Semiconductor Corporation
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S SABER Electrical Model
REV February 1999 template huf75343 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 2.35e-12, cjo = 6.34e-9, tt = 3.950e-8, m = 0.6) d..model dbreakmod = () d..model dplcapmod = (cjo = 21.5e-10, is = 1e-30, n = 10, m = 0.730) m..model mmedmod = (type=_n, vto = 3.30, kp = 5.49, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.87, kp = 145, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.92, kp = 0.050, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.90, voff = -3.90) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.90, voff = -6.90) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.39, voff = 3.39) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 3.39, voff = 0.39) c.ca n12 n8 = 3.95e-9 c.cb n15 n14 = 5.05e-9 c.cin n6 n8 = 2.68e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1
LGATE GATE 1 RLGATE CIN
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
-
LSOURCE 7 RLSOURCE
l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.60e-9 l.lsource n3 n7 = 1.10e-9 k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
12
SOURCE 3
RSOURCE S1A 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.04e-3, tc2 = 3.43e-7 res.rdbody n71 n5 = 2.21e-3, tc1 = 2.47e-3, tc2 = 3.97e-11 res.rdbreak n72 n5 = 9.1e-2, tc1 = -2.24e-4, tc2 = 5.23e-6 res.rdrain n50 n16 = 0.70e-3, tc1 = 4.44e-2, tc2 = 8.04e-5 res.rgate n9 n20 = 0.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26.0 res.rlsource n3 n7 = 11.0 res.rslc1 n5 n51 = 1e-6, tc1 = 1.02e-4, tc2 = 2.07e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.79e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.93e-3, tc2 = 1.38e-6 res.rvthres n22 n8 = 1, tc1 = -3.49e-3, tc2 = -1.27e-5 spe.ebreak n11 n7 n17 n18 = 58.39 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/609))** 2.5)) } }
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S SPICE Thermal Model
REV 12 February 1999 HUF75343 CTHERM1 th 6 6.15e-3 CTHERM2 6 5 2.50e-2 CTHERM3 5 4 1.40e-2 CTHERM4 4 3 1.25e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 tl 12.55 RTHERM1 th 6 3.76e-3 RTHERM2 6 5 9.35e-3 RTHERM3 5 4 2.64e-2 RTHERM4 4 3 1.48e-1 RTHERM5 3 2 2.23e-1 RTHERM6 2 tl 2.96e-2
RTHERM1 CTHERM1 th JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF75343 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.15e-3 ctherm.ctherm2 6 5 = 2.50e-2 ctherm.ctherm3 5 4 = 1.40e-2 ctherm.ctherm4 4 3 = 1.25e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 3.76e-3 rtherm.rtherm2 6 5 = 9.35e-3 rtherm.rtherm3 5 4 = 2.64e-2 rtherm.rtherm4 4 3 = 1.48e-1 rtherm.rtherm5 3 2 = 2.23e-1 rtherm.rtherm6 2 tl = 2.96e-2 }
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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