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| Z86C96 CPS DC-4049-02 CUSTOMER PROCUREMENT SPECIFICATION Z86C96 CMOS Z8(R) MICROCONTROLLER GENERAL DESCRIPTION The Z86C96 microcontroller introduces a new level of sophistication to single-chip architecture. The Z86C96 is a member of the Z8 single-chip microcontroller family with 256 bytes of general-purpose RAM. The MCU is housed in 64-pin DIP and 68-pin Leaded ChipCarrier packages and is manufactured in CMOS technology. Zilog's CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86C96 architecture is characterized by Zilog's 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced consumer applications. The device applications demand powerful I/O capabilities. The Z86C96 fulfills this with 52 pins dedicated to input and output. These lines are grouped into six 8-bit ports and one 4-bit port. The ports are configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this wide range of configuration: program memory, data memory and 236 general-purpose registers. To unburden the program from coping with the real-time problems such as counting/timing and serial data communication, the Z86C96 offers two on-chip Counter/Timers with a large number of user selectable modes, and a Asynchronous Receiver/Transmitter (UART - see block diagram). Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC-4049-02 (6-8-93) 1 Z86C96 CPS DC-4049-02 GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Flags Counter/ Timers (2) Register Pointer Interrupt Control Register File 256 x 8-Bit Program Counter Port 6 Port 5 Port 4 Port 2 4 Port 0 4 Port 1 8 Address/Data or I/O (Byte Programmable) I/O (Bit Programmable) Address or I/O (Nibble Programmable) Z-BUS When Used As Address/Data Bus Functional Block Diagram 2 Z86C96 CPS DC-4049-02 PIN DESCRIPTION P44 VCC P45 XTAL2 XTAL1 P37 P30 N/C /RESET R/W /DS P46 P47 AS P35 N/C GND P32 P50 P51 P00 P01 P02 P03 P04 P05 P06 P07 VCC P52 P53 P54 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P43 P42 P36 P31 P41 P40 P27 P26 P25 P24 P23 P22 P60 P61 P21 P20 GND P33 P34 P62 P63 P17 P16 P15 P14 P13 P12 P57 P56 P11 P10 P55 Z86C96 DIP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64-Pin Dual In-Line Plastic Pin Assignments 3 Z86C96 CPS DC-4049-02 PIN DESCRIPTION (Continued) /R ES E P3 T 0 P3 7 XT AL 1 XT AL 2 P4 5 VC C P4 4 P4 3 P4 2 P3 6 P3 1 P4 1 P4 0 P2 7 P2 6 P2 5 60 59 58 57 56 55 54 9 R/W /P0DS /DS P46 P47 /P1DS /AS /DTIMERS P35 N/C GND P32 P50 P51 P00 P01 P02 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 P24 P23 P22 P60 P61 P21 P20 SCLK /SYNC GND P33 P34 P62 P63 P17 P16 P15 Z86C96 PLCC 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P0 7 VC C P5 2 3 P5 4 P5 5 P1 0 P1 1 P5 6 P5 7 P0 4 P0 5 P0 6 3 2 P1 68-Pin Plastic Leaded Chip Carrier Pin Assignments 4 P1 3 P1 4 P0 P5 Z86C96 CPS DC-4049-02 ABSOLUTE MAXIMUM RATINGS Symbol Description VCC TSTG TA Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max +7.0 +150 Units V C C Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Notes: * Voltages on all pins with respect to GND. See Ordering Information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Test Load Diagram). From Output Under Test +5V 2.1 k 150 pF 9.1 k Test Load Diagram PLEASE NOTE This device will not operate in extended Timing mode. Set Register 248 (F8H), D5 = 0. 5 Z86C96 CPS DC-4049-02 DC CHARACTERISTICS TA = 0C to +70C Min Max 3.8 -0.3 2.0 -0.3 2.4 VCC-100mV 3.8 -0.3 -2 -2 0.4 VCC+ 0.3 0.8 2 2 -80 35 6.5 7.0 10 7 VCC+ 0.3 0.8 VCC+ 0.3 0.8 TA = -40C to +105C Min Max 3.8 -0.3 2.0 -0.3 2.4 VCC-100mV 3.8 -0.3 -2 -2 0.4 VCC+ 0.3 0.8 2 2 -80 35 6.5 7.0 20 24 4 4.5 5 7 VCC+ 0.3 0.8 VCC+ 0.3 0.8 Typical at 25C Parameter Sym VCC = 4.5 V to 5.5 V VCH VCL VIH VIL VOH VOH VOL VRH VRL IIL IOL IIR ICC ICC1 ICC2 Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltge Output High Voltge Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current Standby Current Standby Current Units V V V V V V V V V V A A A mA mA mA A Conditions IIN < 250 A Driven by External Clock Generator Driven by External Clock Generator IOH = -2.0 mA IOH = -100 A IOL = +5.0 mA VIN = 0 V, VCC VIN = 0 V, VCC VRL = 0 V [1] @ 16 MHz [1] HALT Mode VIN = O V, VCC@12 MHz [1] HALT Mode VIN = O V,VCC@ 16 MHz [1] STOP Mode VIN = O V,VCC Notes: [1] All inputs driven to either 0 V or VCC, outputs floating. 6 Z86C96 CPS DC-4049-02 AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 19 3 Port 1 A7 - A0 1 2 D7 - D0 IN 9 /AS 8 4 5 6 18 11 /DS (Read) 17 10 Port1 A7 - A0 14 D7 - D0 OUT 15 7 /DS (Write) 17 External I/O or Memory Read/Write Timing 7 Z86C96 CPS DC-4049-02 AC CHARACTERISTICS External I/O or Memory Read or Write Timing Table TA = 0C to +70C 16 MHz Min Max 25 35 180 40 0 135 80 75 0 50 35 20 35 25 35 230 45 60 30 0 50 35 25 35 25 35 230 45 60 30 40 0 135 80 75 TA = -40C to +105C 16 MHz Min Max 25 35 180 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Rise Delay Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See Clock Dependent Formulas table. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. Clock Dependent Formulas Number 1 2 3 4 6 7 8 10 11 12 13 14 15 16 17 18 19 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TsDI(DS) TdDM(AS) Equation 0.40 TpC + 0.32 0.59 TpC - 3.25 2.83 TpC + 6.14 0.66 TpC - 1.65 2.33 TpC - 10.56 1.27 TpC + 1.67 1.97 TpC - 42.5 0.8 TpC 0.59 TpC - 3.14 0.4 TpC 0.8 TpC - 15 0.4 TpC 0.88 TpC - 19 4 TpC - 20 0.91 TpC - 10.7 0.8 TpC - 10 0.9 TpC - 26.3 8 Z86C96 CPS DC-4049-02 AC CHARACTERISTICS Additional Timing Diagram 1 3 Clock 2 2 3 T IN 4 IRQ N 5 Additional Timing AC CHARACTERISTICS Additional Timing Table TA = 0C to +70C 16 MHz Min Max 62.5 25 75 3TpC 8TpC 100 70 3TpC 3TpC 1000 10 TA = -40C to +105C 16 MHz Min Max 62.5 25 75 3TpC 8TpC 100 50 3TpC 3TpC 1000 10 No 1 2 3 4 5 6 7 8A 8B 9 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times Units ns ns ns ns Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3] ns ns Notes: [1] Clock timing references use 3.8 V for a logic 1 and 0.8 V for a logic 0. [2] Timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. 9 Z86C96 CPS DC-4049-02 AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid Next Data In Valid 1 3 2 /DAV (Input) 4 Delayed DAV 5 6 RDY (Output) Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) 8 10 9 Delayed DAV 11 RDY (Input) Delayed RDY Output Handshake Timing AC CHARACTERISTICS Handshake Timing Table TA = 0C to +70C 16 MHz Min Max 0 145 110 115 115 0 TpC 0 115 110 115 110 115 0 115 0 TpC TA = -40C to +105C 16 MHz Min Max 0 145 110 115 115 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay 10 Z86C96 CPS DC-4049-02 Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specifcation requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. (c) 1993 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 11 |
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