View YMU759_34963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

YMU759
MA-2
Outline
YMU759 is a synthesis LSI for portable telephone that is capable of playing high quality music by utilizing FMsynthesizer and ADPCM decorder that are included in this device. As a synthesis, YMU759 is equipped with Yamaha's original FM synthesizer, with which the device is capable of simultaneously generating up to 16 voices with different tones. Since the device is capable of generating ADPCM data simultaneously synchronous with the play of the FM synthesizer, various sampled voices can be used as sound effects. Since the play data of YMU759 are interpreted at anytime through FIFO, the length of the data (playing period) is not limited, so the device can flexibly support applications such as incoming call melody distribution service. The hardware sequencer built in this device allows playing of complex music without giving excessive load to the CPU of the portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time sound generation, allowing, for example, utilization of various sound effects when using the game software installed in the portable telephone. YMU759 includes a speaker amplifier with low ripple whose maximum output is 550 mW (SPVDD=3.6V). The device is also equipped with conventional functions including a vibrator and a circuit for controlling LEDs synchronous with music. For the headphone, it is provided with a stereophonic analog output terminal. For the purpose of enabling YMU759 to demonstrate its full capabilities, Yamaha proposes to use "SMAF: Synthetic music Mobile Application Format" as a data distribution format that is compatible with multimedia. Since the SMAF takes a structure that sets importance on the synchronization between sound and images, various contents can be written into it including incoming call melody with words that can be used for training karaoke, and commercial channel that combines texts, images and sounds, and others. The hardware sequencer of YMU759 directly interprets and plays blocks relevant to systhesis (playing music and reproducing ADPCM with FM synthesizer) that are included in the data distributed in SMAF.
Features
FM synthesizer functions Tones FM synthesizer is capable of creating countless tones theoretically. When synthesizing tones, it is necessary to designate the number of operators to be used for the synthesis. (Refer to "5-7. FM synthesis section" for explanation of operator.) Increasing the number of operators allows synthesis of tones that are more intricate and closer to those generated by natural musical instruments. YMU759 supports synthesis of tones of two types including 2-operator tones and 4-operator tones. Because operator's wave shape can be chosen from eight kinds, the quality of sound improves more remarkably than 2 operator sound of the MA-1 series. (A MA-1 series can choose operator wave shape from two kinds.) Number of voices simultaneously generated YMU759 is equipped with 32 operators. The number of voices simultaneously generated varies depending on how many 2-operator tones and 4-operator tones are used.
YAMAHA CORPORATION
YMU759 CATALOG CATALOG No.:LSI-4MU759A2 2001.1
YMU759
When only 2-operator tones are used: up to 16 voices can be generated simultaneously. When only 4-operator tones are used: up to 8 voices can be generated simultaneously. Compatible with stereophonic sound generation. Volume control Channel volume, master volume, expression, and pan pot control in individual channels Sequencer is built in. Can interpret Mobile Multimedia Format directly. Equipped with four systems of 96 FIFOs for sequence data Supports direct access that directly controls FM synthesizer. Supports key control with half an octave higher and lower. ADPCM reproduction function Equipped with ADPCM decoder with 4 bits, 1 channel Supports two kinds of sampling frequency, 4 kHz and 8 kHz. Sequencer is built in. Equipped with 348 byte FIFO for ADPCM data and 32 byte FIFO for sequence data Supports direct access that directly controls ADPCM section. Speaker amplifier and equalizer circuit Output of speaker amplifier: 550 mW when SPVDD=3.6 V, or 400 mW when SPVDD=3.0 V Balanced input speaker amplifier provides low ripple Built-in equalizer circuit corrects the difference of frequency response among the speakers and forms of bodies. Interface 4 wire serial interface or 12 wire parallel interface can be selected. Others PLL is built-in to support master clock input in 2 MHz to 20 MHz range. Provided with a circuit for controlling on/off of LEDs and vibrator. These can be operated synchronous with the play data. Provided with a stereophonic analog output terminal for headphone 16 bit stereophonic D/A converter is built in. Supports power down mode. (Typical current: 1 A or less) Power supply voltage The power supply includes two power supply sub-systems, analog power supply devoted to speaker amplifier and power supply for other sections. The power supply for the speaker amplifier (SPVDD) supplies voltages in the range 2.7 V ~ 4.5 V (Typ 3.6 V), and other power supplies (VDD) voltages in the range 2.7 V ~ 3.3 V (Typ 3.0 V). 32-pin plastic QFN.
-2-
YMU759
Terminal configuration
SPOUT2
SPOUT1
EXT2
25
D2
D3
24 23 22
D4
D5
D6
21 20 19 18 17 16 15 14 13 12 11 10
D7
D1 D0 /WR SDIN (/CS) SYNC (A0) SCLK (/RD) SDOUT
26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9
SPVSS SPVDD EQ3 EQ2 EQ1 HPOUT-R HPOUT-L/MONO
CLKI
EXT1
<32pin QFN Top View>
/IRQ
/RST
-3-
IFSEL
PLLC
VDD
VSS
VREF
YMU759
Terminal functions
No. 1 2 3 4 5 6 Name CLKI
EXT1
I/O Ish O O Ish I A
Clock input (2~20MHz)
Function
External device control terminal 1 (*) Interruption output Hardware reset input CPU I/F selection L: Serial I/F, H: Parallel I/F Connection of capacitor for built in PLL
/IRQ /RST IFSEL PLLC
Connect the 3.3k resistance and the 1000pF capacitor between this terminal and VSS in series. Digital power supply (Typically +3.0V) Connect 0.1 F and 4.7 F capacitors between this terminal and VSS Ground Analog reference voltage. Connect 0.1 F capacitor between this terminal and VSS Headphone L channel output: can be switched to mono through register setting Headphone R channel output Equalizer terminal 1 Equalizer terminal 2 Equalizer terminal 3 Analog power supply (Typically +3.6 V) Connect 0.1 F and 4.7 F capacitors between this terminal and SPVSS Analog ground for speaker amplifier Speaker terminal 1 Speaker terminal 2 External device control terminal 2 (*) Parallel I/F data bus 7 (*) Parallel I/F data bus 6 (*) Parallel I/F data bus 5 (*) Parallel I/F data bus 4 (To be open when IFSEL=L) Parallel I/F data bus 3 (To be open when IFSEL=L) Parallel I/F data bus 2 (To be open when IFSEL=L) Parallel I/F data bus 1 (To be open when IFSEL=L) Parallel I/F data bus 0 (To be open when IFSEL=L) Parallel I/F write pulse (To be open when IFSEL=L) IFSEL= L Serial I/F data input IFSEL= H Parallel I/F chip select input IFSEL= L Serial I/F data decision signal IFSEL= H Parallel I/F address signal IFSEL= L Serial I/F bit clock input IFSEL= H Parallel I/F read pulse Serial I/F data output (Pull up resistance is necessary for the outside)
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD VSS VREF HPOUT-L / MONO HPOUT-R EQ1 EQ2 EQ3
SPVDD
A A A A A A A A O I/O I/O I/O I/O I/O I/O I/O
I/O
SPVSS SPOUT1 SPOUT2 EXT2
D7 D6 D5
D4 D3 D2 D1 D0 /WR SDIN (/CS) SYNC (A0) SCLK (/RD) SDOUT
Ish Ish Ish Ish OD
Comment: Ish= Schmitt input, OD= open drain terminal, A= Analog terminal (*) The function changes by setup of the register.
-4-
PLLC
VSS
HPOUT-L /MONO
HPOUT-R
VDD
CLKI
Block diagram
/RST
PLL Timing Generator
HP Vol R HP Vol L
YMU759
Power Down Control
SCLK
Select
SYNC
SDIN
Rch Vol Lch Vol 16 - bit DAC Lch Rch
Register
SDOUT
FM Synthesizer
SELECT
/CS
CPU I/F
FM FIFO x4 Sequencer
16 sound generated simultaneously (Fs=49.7 kHz)
VREF
EQ Vol
EQ1
A0
EQ2
+
/WR
EQ3
-5Sequencer (Fs=4 or 8kHz)
/RD
D0 -D7
ADPCM Seq FIFO
ADPCM Playback
Vol & LPF
SP Vol
IFSEL
4
LED control Vibrator control TIMER
ADPCM Wave FIFO
SPOUT1
/IRQ
EXT1
Mix & Select
EXT2
VREF
SPOUT2
SPVSS
SPVDD
VREF
Analog power supply devoted to speaker amplifier
YMU759
Outline of blocks
Explanation about outline of built-in each blocks and flow of the signal are follows.
Clock Generate FM Sound Generator DAC
Headphone Output
Register CPU Interface FIFO
Hardware Sequencer ADPCM Playback
EQ Amplifier
External Parts
Speaker Amplifier
CPU interface Receives commands send from external CPU, interprets the contents, and then writes them into registers by index address. Controls reading of designated register data. As interfaces for controlling YMU759, 4 wire serial and 12 wire parallel interfaces are provided, which can be selected through IFSEL terminal. Registers Register groups that control the LSI except for sequence data. FM tone register data, various volumes and other control data are store here. FIFO Sequence data to move hardware sequencer and ADPCM wave data are stored in FIFO. This device is equipped with four FIFOs for FM and two FIFOs for ADPCM. The FIFOs for FM stores sequence data and those for ADPCM stores sequence and waveform data. The size of FIFOs for FM is 96 bytes, the one for ADPCM data is 384 bytes, and the one for sequence data is 32 bytes. Hardware sequencer FIFO is provided as a previous stage of the sequencer which reads sequence data from FIFO to control FM and ADPCM sections. The sequence data are compatible with SMAF(Synthetic music Mobile Application Format) proposed by yamaha. FM synthesis This is a synthesis that uses Yamaha's original FM system. It is able to generate up to 16 voices simultaneously. This section plays in accordance with commands from the sequencer. It can also play by directly controlling various registers without using the sequencer. The sampling frequency is 49.7 kHz that complies with stereophonic sound. ADPCM playback This section decodes 4 bit ADPCM data to 16 bit data by using the sampling frequency of 4 kHz or 8 kHz. It can playback one voice. It playback according to command from sequencer. And it can playback to control various register directly without using sequencer.
-6-
YMU759
DAC Converts digital signal from FM and ADPCM section to analog voice signal with resolution of 16 bits. Headphone output This section supports stereophonic analog output for the headphone. Monaural output is available by changing the setting. And built in volume adjust output level. EQ amplifier This section is used to set the response of filter or the gain by externally connecting a resistor and capacitor. Speaker amplifier A speaker amplifier is built in this device, which maximum output is 550 mW at AVDD=3.6 V. Built in volume adjust output level in front of amplifier. Low ripple is provided. Clock generate This block makes a necessary clock by increasing 2 to 20 MHz clock inputted through CLK1 terminal using the built-in PLL. The clock generated in this section is supplied to the inside of digital circuit.
-7-
YMU759
Electrical Characteristics
Absolute maximum rating Item
SPVDD terminal power supply voltage (Speaker amplifier section) VDD terminal power supply voltage (Others) SPOUT1 and SPOUT2 terminal impressed voltage Analog input voltage Digital input voltage Operating ambient temperature Storage temperature
Symbol
SPVDD VDD VINSP VINA VIND TOP TSTG
Min.
-0.3 -0.3 -0.3 -0.3 -0.3 -20 -50
Max.
6.0 4.2 SPVDD+0.3 VDD+0.3 VDD+0.3 85 125
Unit
V V V V V C C
Note: VSS = SPVSS = 0V
Recommended operating conditions Item
SPVDD operating voltage (Speaker amplifier section) VDD operating voltage (Others) Operating ambient temperature
Symbol
SPVDD VDD TOP
Min.
2.7 2.7 -20
Typ.
3.6 3.0 25
Max.
4.5 3.3 85
Unit
V V C
Note: VSS = SPVSS = 0V
DC characteristics
Item
Input voltage "H" level Input voltage "L" level Output voltage "H" level Output voltage "L" level Schmitt width Input leakage current Input capacity
Symbol
VIH1 VIL1 VOH VOL Vsh IL CI
Condition
Min.
0.7 x VDD -
Typ.
0.5
Max
0.2 x VDD 0.4
Unit
V V V V V
IOH = (*1) IOL = (*1)
0.8 x VDD -
-10
10 10
A pF
Note: TOP=-20 to 85C, VDD=3.00.3V, Capacitor load=50pF
(*1) /IRQ, , SDOUT, D0~D7 are IOH=-1mA, IOL=+1mA, (SDOUT is only IOL) EXT1, EXT2 are IOH=- 4mA, IOL=+ 4mA.
-8-
YMU759
AC characteristics /RST, CLKI Item
/RST active "L" pulse width CLKI frequency CLKI rise time / fall time CLKI duty
Symbol
TRSTW 1 / Tfreq Tr / Tf Th/Tfreq
Min.
1024 2
Typ.
Max.
Unit
x CLKI
20 30
MHz ns
%
30
50
70
Note: TOP=-20 ~ 85C, VDD=3.00.3 V, Capacitor load=50 pF. Input hardware reset at the time VDD is turned on.
VDD /RST
VIL= 0.2*VDD VIH= 0.7*VDD
TRSTW
CLKI
1024 clocks or more are needed.
Th
Tf
CLKI
Tr Tfreq
VIH= 0.7*DVDD VIL= 0.2*DVDD
-9-
YMU759
Serial I/F Item
SCLK clock period SCLK "L" pulse width SCLK "H" pulse width SCLK rise time SCLK fall time SYNC "H" pulse width SYNC "L" pulse width SYNC / SDIN rise time SYNC / SDIN fall time SYNC delay time SYNC -> SCLK setup time SDIN setup time SDIN hold time SDOUT delay time Read wait time
Symbol
Tclk_period Tclk_low Tclk_high Trise_clk Tfall_clk Tsync_high Tsync_low Trise Tfall Tdelay_SYNC Tsetup_SYNC Tsetup_SDIN Thold_SDIN Tdelay_SDOUT Trd_wait
Min.
80 20 20
Typ.
Max.
Unit
ns ns ns
30 30 30 30 30 30 0 120 20 20 70(*2) (*1) -
ns ns ns ns ns ns ns ns ns ns ns ns
Note: TOP=-20 ~ 85C, VDD=3.00.3 V, Capacitor load=50 pF. (*1): Read wait time varies in the register which accesses it. (*2): Max 70ns is the delay time when it is outputted from the D5 terminal. Delay time from the SDOUT terminal varies according to pull-up resistance value and the load capacity of the outside. Standard delay time can be calculated by step response expression of the RC circuit. Time to change to the voltage of [power supply of external pull-up resistance x 80%] is as follows. 1 - exp ( -t / R * C ) = 0.80 When R = 1k, C= 50pF, t = 80ns //
"Standard delay time" and the reason why it was written are because resistance value and capacity value swing by the part's own error and the temperature character.
-10-
YMU759
Tclk_high Tfall_clk Measurement point VIH = 0.7*VDD VIL = 0.2*VDD VOH= 0.8*VDD VOL = 0.4V Trise_clk Tclk_period Tclk_low
SCLK
Tsync_high
SYNC SDIN
Trise Tfall
SCLK
Tsetup_SDIN Thold_SDIN Tsetup_SYNC
SDIN
Tdelay_SYNC
SYNC
Tsync_low
Trend
SCLK
Tdelay_SDOUT
D5 or SDOUT SYNC
LSB
In the case of D5 terminal, H level output. In the case of SDOUT terminal, Hi-Z.
Tsync_low
SYNC
Trd_wait
SCLK D5 or SDOUT
MSB
-11-
YMU759
Parallel I/F (write cycle) Item
Chip select width Address setup time Address hold time Write pulse width Data setup time Data hold time
Symbol
TCSW TAS TAH TWW TWDS TWDH
Min.
100 10 10 50 30 5
Max.
Unit
ns ns ns ns ns ns
Note: TOP=-20 ~ 85C, VDD=3.00.3 V, Capacitor load=50 pF. (Read cycle) Item
Chip select width Address setup time Address hold time Read pulse width Read data access time Data hold time
Symbol
TCSR TAS TAH TRW TACC TRDH
Min.
100 0 0 80
Max.
Unit
ns ns ns ns
70 10 50
ns ns
Note: TOP=-20 ~ 85C, VDD=3.00.3 V, Capacitor load=50 pF. Write cycle
A0
TAH TCSW
/CS
TAS TWW
/WR
TWDS TWDH
D0~D7
Invalid
Valid
Invalid
Note: TCSW, TWW, TWDH and TAH are defined with respect to the moment /CS or /WR becomes High level.
Measurement point VIH = 0.7*VDD VIL = 0.2*VDD VOH= 0.8*VDD VOL = 0.4V
-12-
YMU759
Read cycle
A0
TAH TCSR
/CS
TAS TRW
/RD
TACC TRDH
D0~D7
Valid
Note: TACC is defined with respect to the moment /CS or /RD becomes Low level later. TCSR, TRW , TRDH and TAH are defined with respect to the moment /CS or /RD becomes High level.
Measurement point VIH = 0.7*VDD VIL = 0.2*VDD VOH= 0.8*VDD VOL = 0.4V
Power consumption Item
VDD section (normal operation) SPVDD section (no voice) SPVDD section 8 load and 400 mW output Power down mode (VDD + SPVDD) (*)
Min.
Typ.
17 5 210 1
Max.
Unit
mA mA mA
10
A
Note: TOP=-20 ~ 85C, VDD=3.00.3 V, SPVDD=3.6V. (*) Measurement condition : The input terminals except for CLKI are fixed on VIH=VDD, VIL=0V.
-13-
YMU759
Analog characteristics SP amplifier Item
Gain setting (Fixed) Minimum load resistance (RL) Maximum output voltage amplitude (RL=8) Maximum output power (RL=8, THD+N<=0.05%) Maximum output power (RL=8, THD+N<=1.0%) THD + N (RL=8, f=1kHz, output=400mW) Noise at no signal (A-filter: auditory sensation weighting filter) PSRR (f=1kHz) Amplitude center voltage (VSEL=0) Amplitude center voltage (VSEL=1) Differential output voltage
Min.
Typ. 2
8 6.0 500 580 0.02 -90 90 x 0.6 x 0.5 10
Max.
Unit
Times Vp-p mW mW % dBv dB VDD VDD
50
mV
Note: TOP=25C, VDD=3.0V, SPVDD=3.6V EQ amplifier Item
Gain setting range Maximum output current Maximum output voltage amplitude THD + N (f=1kHz) Noise at no signal (A-filter) Input impedance 10 -90 120 1.5 0.05
Min.
Typ.
Max.
30
Unit
dB A Vp-p % dBv M
Note: TOP=25 C, VDD=3.0 V and SPVDD=3.6 V. SP Volume Item
Volume setting range Volume step width Noise at no signal (A-filter) THD + N (f=1kHz)
Min.
-30
Typ.
Max.
0
Unit
dB dB dBv
1 -90 0.05
%
Note: TOP=25 C, VDD=3.0 V and SPVDD=3.6 V
-14-
YMU759
EQ Volume Item
Volume setting range Volume step width Noise at no signal (A-filter) Maximum output current Maximum output voltage amplitude Output impedance 120 1.5 300 600
Min.
-30
Typ.
Max.
0
Unit
dB dB dBv A Vp-p
1 -90
Note: TOP=25C, VDD=3.0V and SPVDD=3.6V. HP Volume Item
Volume setting range Volume step width Noise at no signal (A-filter) Maximum output current Maximum output voltage amplitude Output impedance 120 1.5 300 600
Min.
-30
Typ.
Max.
0
Unit
dB dB dBv A Vp-p
1 -90
Note: TOP=25C, VDD=3.0V and SPVDD=3.6V VREF Item
VREF voltage
Min.
Typ.
Max.
Unit
VDD
x0.5
Note: TOP=25C, VDD=3.0V and SPVDD=3.6V.
DAC Item
Resolution Full scale output voltage THD+N (f= 1kHz) Noise at no signal (A-filter) Frequency response (f=50Hz ~20kHz) -3.0(*1) -85
Min.
Typ.
16 1.5
Max.
Unit
Bit Vp-p
0.5 -80 +0.5
%
dBv dB
Note: TOP=25C, VDD=3.0V, SPVDD=3.6V (*1): The decline of high range response by aperture effect.
-15-
YMU759
External dimensions of package
-16-
YMU759
MEMO
-17-
YMU759
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to change without notice.
Agency
Address inquiries to:
Semiconductor Sales & Marketing Department
Head Office 203, Matsunokijima, Toyooka-mura, Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 Osaka Office Nanba Tsuzimoto Nissei Bldg. 4F 1-13-17, Nanbanaka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691
-18-

▲Up To Search▲

Price & Availability of YMU759

	To Download YMU759 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .