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| PRELIMINARY PRODUCT SPECIFICATION 1 Z89321/371/391 16-BIT DIGITAL SIGNAL PROCESSORS FEATURES Device Z89321 Z89371 Z89391 Note: *External s 1 DSP ROM (KW) 4 OTP (KW) 4 DSP RAM Lines 512 512 512 MIPS (Max) 24 16 24 Device Z89321 Z89371 Z89391 40-Pin DIP X X 44-Pin PLCC X X 44-Pin QFP X X 84-Pin PLCC 64* X Note: *General-Purpose 0C to +70C Standard Temperature Range -40C to +85C Extended Temperature Range 4.5- to 5.5-Volt Operating Range On-Board Peripherals s s Dual 8/16-Bit CODEC Interface Capable of up to 10 Mbps m-Law Compression Option (Decompression is Performed in Software) 16-Bit I/O Bus (Tri-Stated) Three I/O Address Pins (Latched Outputs) Wait-State Generator Three Vectored Interrupts 13-Bit General-Purpose Timer DSP Core s s s s s s 24 MIPS @ 24 MHz Maximum, 16-Bit Fixed Point DSP s 41.7 ns Minimum Instruction Cycle Time s Six-Level Hardware Stack s Six Register Address Pointers s Optimized Instruction Set (30 Instructions) s GENERAL DESCRIPTION The Z893XX products are high-performance Digital Signal Processors (DSPs) with a modified Harvard-type architecture featuring separate program and data memory. The design has been optimized for processing power while minimizing silicon space. The single-cycle instruction execution and bus structure promotes efficient algorithm execution, while the six register pointers provide circular buffering capabilities and dual operand fetching. Three vectored interrupts are complemented by a six-level stack, and the CODEC interface allows high-speed transfer rates to accommodate digital audio and voice data. A dedicated Counter/Timer provides the necessary timing signals for the CODEC interface, and an additional 13-bit timer is available for general-purpose use. DS97DSP0100 PRELIMINARY 1 Z89321/371/391 16-Bit Digital Signal Processors The Z893XX DSPs are optimized to accommodate advanced signal processing algorithms. The 24 MIPS (maximum) operating performance and efficient architecture provides real-time instruction execution. Compression, filtering, frequency detection, audio, voice detection/synthesis, and other vital algorithms can all be accommodated. The Z89321/371/391 devices feature an on-board CODEC interface, compatible with 8-bit PCM and 16-bit CODECs for digital audio applications. Additionally, an onboard wait-state generator is provided to accommodate slow external peripherals. For prototypes, as well as production purposes, the Z89371 member of the DSP product family is a one-time Zilog pro-grammable (OTP) device with a 16 MHz maximum operating frequency. Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS Program ROM/OTP 4096x16 PA0-15 PD0-15 PDATA PADDR Data RAM0 256x16 Data RAM1 256x16 DDAT A EA0-2 EXT0-15 /DS WAIT RD//WR XDAT A P0 X Y P1 P2 DP0-3 ADDR GEN0 P0 P1 P2 DP4-6 ADDR GEN1 8/16-Bit, Full Duplex, 10 MBPS Serial Port Multiplier INT0-2 HALT /RESET CLK Program Control Unit P Shifter TXD RXD SCLK FS0 FS1 13-Bit Timer User I/O UI1-0 UO1-0 Arithmetic Logic Unit (ALU) Accumulator Figure 1. Z89321/371/391 Functional Block Diagram 2 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors PIN DESCRIPTION EXT12 EXT13 EXT14 VSS EXT15 EXT3 EXT4 VSS EXT5 EXT6 EXT7 TXD EXT8 EXT9 VSS EXT10 EXT11 UI1 UI0 SCLK 1 40 DIP 40 - Pin 20 21 RXD VSS EXT2 EXT1 EXT0 VSS FS1 U01 U00 /INT0 FS0 CLK /DS VDD EA2 EA1 EA0 /RESET RD//WR VDD 1 Figure 2. Z89321/371 40-Pin DIP Pin Assignments Table 1. Z89321/371 40-Pin DIP Pin Identication No. 1-3 4 5 6-7 8 9-11 12 13-14 15 16-17 18 19 20 21 22 Symbol EXT12EXT14 VSS EXT15 Function External Data Bus Ground Direction Input/Output Table 1. Z89321/371 40-Pin DIP Pin Identication No. 23 24-26 27 28 Input/Output 29 30 Input/Output Output Input/Output 35 36-38 Input/Output 39 Input Input Input/Output* Input Output 40 VSS 31 32-33 34 /INT0 UO0-UO1 FS1 CLK FS0 Symbol /RESET EA0-EA2 VDD /DS Function Direction External Data Bus EXT3-EXT4 External Data Bus VSS Ground EXT5-EXT7 External Data Bus TXD Serial Output to CODECs EXT8-EXT9 External Data Bus VSS Ground EXT10EXT11 UI1 UI0 SCLK VDD RD//WR External Data Bus User Input User Input CODEC Serial Clock Power Supply Strobes for External Bus Input/Output Reset Input External Address Output Bus Power Supply Input Data Strobe for External Bus Clock CODEC 0 Frame Sync Interrrupt User Output CODEC 1 Frame Sync Ground Output Input Input/Output* Input Output Input/Output* EXT0-EXT2 External Data Bus VSS Ground RXD Input/Output Serial Input from Input CODECs Notes: *Input/Output is defined by interface mode selection. HALT/WAIT pins not available on 40-pin DIP package. DS97DSP0100 PRELIMINARY 3 Z89321/371/391 16-Bit Digital Signal Processors Zilog PIN DESCRIPTION (Continued) VSS EXT0 EXT1 EXT2 VSS RXD EXT12 EXT13 EXT14 VSS EXT15 7 FS1 UO1 UO0 /INT0 FSO HALT CLK /DS VDD EA2 EA1 6 1 40 39 PLCC 44 -Pin 17 18 29 28 EA0 /RESET WAIT RD//WR VDD SCLK UI0 UI1 INT1 INT2 EXT11 Figure 3. Z89321/371 44-Pin PLCC Pin Assignments 4 EXT3 EXT4 VSS EXT5 EXT6 EXT7 TXD EXT8 EXT9 VSS EXT10 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors Table 2. Z89321/371 44-Pin PLCC Pin Identication No. 1 2 3 4-5 6 7 8-10 11 12 13-15 16 17 18-19 20 21-23 24 25-26 27 28-29 30 31 32 33 34 35 36 37 38 39-41 42 43 44 Symbol HALT FS0 /INT0 O0-UO1 FS1 VSS EXT0-EXT2 VSS RXD EXT12-EXT14 VSS EXT15 EXT3-EXT4 VSS EXT5-EXT7 TXD EXT8-EXT9 VSS EXT10-EXT11 /INT2 /INT1 UI1 UI0 SCLK VDD RD//WR WAIT /RESET EA0-EA2 VDD /DS CLK Function Stop Execution CODEC 0 Frame Sync Interrupt User Output CODEC 1 frame sync Ground External data bus Ground Serial input from CODECs External data bus Ground External data bus External data bus Ground External data bus Serial output to CODECs External data bus Ground External data bus Interrupt Interrupt User input User input CODEC serial clock Power supply RD//WR strobe for EXT bus WAIT state Reset External Address bus Power Supply Data strobe for external bus Clock Direction Input Input/Output* Input Output Input/Output* Input/Output Input Input/Output Input/Output Input/Output Input/Output Output Input/Output Input/Output Input Input Input Input Input/Output* Input Output Input Input Output Input Output Input 1 Note: * Input or output is defined by interface mode selection. DS97DSP0100 PRELIMINARY 5 Z89321/371/391 16-Bit Digital Signal Processors Zilog PIN DESCRIPTION (Continued) VSS EXT0 EXT1 EXT2 VSS RXD EXT12 EXT13 EXT14 VSS EXT15 34 FS1 UO1 UO0 /INT0 FSO HALT CLK /DS VDD EA2 EA1 33 23 22 Z89321/371 QFP 44 1 12 11 EA0 /RESET WAIT RD//WR VDD SCLK UI0 UI1 INT1 INT2 EXT11 Figure 4. Z89321/371 44-Pin QFP Pin Assignments 6 EXT3 EXT4 VSS EXT5 EXT6 EXT7 TXD EXT8 EXT9 VSS EXT10 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors Table 3. Z89321/371 44-Pin QFP Pin Identication No. 1-2 3 4-6 7 8-9 10 11-12 13 14 15 16 17 18 19 20 21 22-24 25 26 27 28 29 30 31-32 33 34 35-37 38 39 40-42 43 44 Symbol EXT3-EXT4 VSS EXT5-EXT7 TXD EXT8-EXT9 VSS EXT10-EXT1 /INT2 /INT1 UI1 UI0 SCLK VDD RD//WR WAIT /RESET EA0-EA2 VDD /DS CLK HALT FS0 /INT0 UO0-UO1 FS1 VSS EXT0-EXT2 VSS RXD EXT12-EXT14 VSS EXT15 Function External data bus Ground External data bus Serial output to CODECs External data bus Ground External data bus Interrupt Interrupt User input User input CODEC serial clock Power supply RD//WR strobe EXT bus WAIT state Reset External address bus Power supply Data strobe for external bus Clock Stop execution CODEC 0 frame sync Interrupt User output CODEC 1 frame sync Ground External data bus Ground Serial input to CODECs External data bus Ground External data bus Direction Input/Output Input/Output Output Input/Output Input/Output Input Input Input Input Input/Output* Input Output Input Input Output Input Output Input Input Input/Output* Input Output Input/Output* Input/Output Input Input/Output Input/Output 1 Note: *Input or output is defined by interface mode selection. DS97DSP0100 PRELIMINARY 7 Z89321/371/391 16-Bit Digital Signal Processors Zilog PIN DESCRIPTION (Continued) 11 /EXTEN EXT3 PA8 EXT4 PA9 VSS EXT5 PA10 EXT6 PA11 EXT7 TXD PA12 EXT8 PA13 EXT9 VSS PA14 EXT10 PA15 VDD 12 /PA_EN EXT15 PA7 VSS PA6 EXT14 PA5 EXT13 PA4 EXT12 RXD VSS PA3 EXT2 PA2 EXT1 PA1 EXT0 VSS PA0 VDD 1 75 74 VSS PD15 FS1 PD14 UO1 PD13 UO0 PD12 INTO FS0 HALT PD11 CLK /DS PD10 VDD PD9 EA2 PD8 EA1 /ROMEN Z89391 84-Pin PLCC 32 33 53 54 8 VSS PD0 EXT11 PD1 INT2 PD2 INT1 PD3 UI1 UI0 SCLK VDD RD//WR PD4 WAIT PD5 /RESET PD6 EA0 PD7 VDD Figure 5. Z89391 84-Pin PLCC Pin Assignments PRELIMINARY DS97DSP0100 Zilog Table 4. Z89391 84-Pin PLCC Pin Identication No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 RXD EXT12 PA4 EXT13 PA5 EXT14 PA6 VSS PA7 EXT15 /PA_EN /EXTEN EXT3 PA8 EXT4 PA9 VSS EXT5 PA10 EXT6 PA11 EXT7 TXD PA12 EXT8 PA13 EXT9 VSS PA14 EXT10 PA15 VDD VSS PD0 EXT11 PD1 INT2 PD2 INT1 PD3 UI1 UI0 Function Serial Input from CODEC External Data 12 Program Address 4 External Data 13 Program Address 5 External Data 14 Program Address 6 Ground Direction Input In/Output Output In/Output Output In/Output Output Z89321/371/391 16-Bit Digital Signal Processors Table 4. Z89391 84-Pin PLCC Pin Identication No. Symbol 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 SCLK VDD RD//WR PD4 WAIT PD5 /RESET PD6 EA0 PD7 VDD /ROMEN EA1 PD8 EA2 PD9 VDD PD10 /DS CLK PD11 HALT FS0 INT0 PD12 UO0 PD13 UO1 PD14 FS1 PD15 VSS VDD PA0 VSS EXT0 PA1 EXT1 PA2 EXT2 PA3 VSS Function CODEC Interface Clock Power Supply R/W External Bus Program Data 4 Wait State Input Program Data 5 Reset Program Data 6 External Address 0 Program Data 7 Power Supply ROM Enable External Address 1 Program Data 8 External Address 2 Program Data 9 Power Supply Program Data 10 External Data Strobe Clock Program Data 11 Stop Execution Frame Synch for CODEC Interface 0 User Interrupt 0 Program Data 12 User Output 0 Program Data 13 User Output 1 Program Data 14 Frame Synch for CODEC Interface 1 Program Data 15 Ground Power Supply Program Address 0 Ground External Data 0 Program Address 1 External Data 1 Program Address 2 External Data 2 Program Address 3 Ground Direction In/Output Input Output Input Input Input Input Input Output Input Input Input Output Input Output Input Input Input Output Input Input Input In/Output Input Input Input Input Input Input In/Output Input Input Output In/Output Output In/Output Output In/Output Output 1 Program Address 7 Output External Data 15 In/Output Prog. Mem. Address Enable Input Ext. Bus Enable Input External Data 3 In/Output Program Address 8 Output External Data 4 In/Output Program Address 9 Output Ground External Data 5 Program Address 10 External Data 6 Program Address 11 External Data 7 Serial Output to CODEC Program Address 12 External Data 8 Program Address 13 External Data 9 Ground Program Address 14 External Data 10 Program Address 15 Power Supply Ground Program Data 0 External Data 11 Program Data 1 User Interrupt 2 Program Data 2 User Interrupt 1 Program Data 3 User Input 1 User Input 0 Input In/Output Input Input Input Input Input Input Input In/Output Output In/Output Output In/Output Output Output In/Output Output In/Output Output In/Output Output Input Note: *Input or output is defined by interface mode selection. DS97DSP0100 PRELIMINARY 9 Z89321/371/391 16-Bit Digital Signal Processors Zilog ABSOLUTE MAXIMUM RATINGS Symbol Description VCC TSTG TA Supply voltage (*) Storage Temp. Oper. Ambient Temp. Min. 0.3 65 Max. Units +7.0 +150 V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: * Voltage on all pins with respect to GND. See Ordering Information. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 6). +5V 2.1 K W From Output Under T est 30 pF 9.1 K W Figure 6. Test Load Diagram 10 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors DC ELECTRICAL CHARACTERISTICS (VDD= 5V 10%, TA = 0C to +70C, unless otherwise noted.) fclock=20 Sym Parameter Condition VDD = 5.5V 5 2.7 .8 10 IOH =100 mA VDD-0.2 IOL =2.0 mA V .5 10 VDD-0.2 .5 10 Min IDD Supply Current IDC DC Power Consumption VIH Input High Level VIL Input Low Level IL Input Leakage VOH Output High Voltage VOL Input Low Voltage IFL Output Floating Leakage Current 70 5 2.7 .8 10 VDD-0.2 .5 10 MHz1 Max. fclock=16 Min 55 5 2.7 .8 10 MHz2 Max fclock=24 Min 85 5 MHz3 Max Units mA mA V V mA V V mA 1 Typ Typ Typ Notes: 1. Z89321 and Z89391 only 2. Z89371 only. VDD = 5V, 5% for 16 MHz operation. VDD = 5V, 10% for 10 MHz operation. 3. Z89321 only. Limited availability. Contact Zilog sales office. DC ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, TA = 40C to +85C, unless otherwise specified) fclock = 20 MHz1 Sym IDD IDC VIH VIL IL VOH VOL IFL Notes: 1. Z89321 only Parameter Supply Current DC Power Consumption Input High Level Input Low Level Input Leakage Output High Voltage Input Low Voltage Output Floating Leakage Current Condition VDD=5.5V Min Typ 70 5 Max 2.7 .8 10 IOH=100 mA IOL =2.0 mA VDD -0.2 .5 10 DS97DSP0100 PRELIMINARY 11 Z89321/371/391 16-Bit Digital Signal Processors Zilog AC ELECTRICAL CHARACTERISTICS (VDD= 5V 10%, TA = 0C to +70C, unless otherwise specified.) fclock = 20 MHz1 Symbol Clock TCY Tr Tf CPW I/O DSVALID /DS Valid Time from CLOCK Fall DSHOLD /DS Hold Time from CLOCK Rise EASET EA Setup Time to /DS Fall EAHOLD EA Hold Time from /DS Rise RDSET Data Read Setup Time to /DS Rise RDHOLD Data Read Hold Time from /DS Rise WRVALID Data Write Valid Time from /DS Fall WRHOLD Data Write Hold Time from /DS Rise Interrupt INTSET Interrupt Setup Time to CLOCK Fall INTWIDTH Interrupt Low Pulse Width CODEC Interface SSET SCLK Setup Time from Clock Rise FSSET FSYNC Setup Time from SCLK Rise TXSET TXD Setup Time from SCLK Rise RXSET RXD Setup Time to SCLK Fall RXHOLD RXD Hold Time from SCLK Fall Reset RRISE Reset Rise Time RSET Reset Setup Time to CLOCK Rise RWIDTH Reset Low Pulse Width External Program Memory PAVALID PA Valid Time from CLOCK Rise PDSET PD Setup Time to CLOCK Rise PDHOLD PD Hold Time from CLOCK Rise Wait State WSET WAIT Setup Time to CLOCK Rise WHOLD WAIT Hold Time from CLOCK Rise Halt HSET Halt Setup Time to CLOCK Rise HHOLD Halt Hold Time from CLOCK Rise Notes: 1. Z89321 and Z89391 only 2. Z89371 only (VDD = 5V 5%) 3. Z89321 only. Limited availability. Contact Zilog sales office. fclock = 16 Min 6.25 MHz2 fclock = 24 MHz3 Min 41.7 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 6 7 7 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Clock Cycle Time Clock Rise Time Clock Fall Time Clock Pulse Width Min 50 Max Max 2 2 23 0 4 12 4 14 6 5 7 1 TCY 15 6 7 7 0 1000 15 2 TCY 20 10 10 23 1 3 10 10 10 23 1 3 10 15 2 TCY 7 0 15 15 29 0 4 12 4 14 6 5 7 1 TCY 2 2 19 15 15 0 4 12 4 14 6 5 7 1 TCY 15 6 7 2 2 15 15 18 18 18 10000 15 2 TCY 20 10 10 23 1 3 10 1000 20 12 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors AC ELECTRICAL CHARACTERISTICS (VDD= 5V 10%, TA = 40C to +85C, unless otherwise specified.) fclock = 20 MHz1 Symbol Clock TCY Tr Tf CPW I/O DSVALID DSHOLD EASET EAHOLD RDSET RDHOLD WRVALID WRHOLD Interrupt INTSET INTWIDTH CODEC Interface SSET FSSET TXSET RXSET RXHOLD Reset RRISE RSET RWIDTH External Program Memory PAVALID PDSET PDHOLD Wait State WSET WHOLD Halt HSET HHOLD Note: 1. Z89321 only 1 Parameter Clock Cycle Time Clock Rise Time Clock Fall Time Clock Pulse Width /DS Valid Time from CLOCK Fall /DS Hold Time from CLOCK Rise EA Setup Time to /DS Fall EA Hold Time from /DS Rise Data Read Setup Time to /DS Rise Data Read Hold Time from /DS Rise Data Write Valid Time from /DS Fall Data Write Hold Time from /DS Rise Interrupt Setup Time to CLOCK Fall Interrupt Low Pulse Width SCLK Setup Time from Clock Rise FSYNC Setup Time from SCLK Rise TXD Setup Time from SCLK Rise RXD Setup Time to SCLK Fall RXD Hold Time from SCLK Fall Reset Rise Time Reset Setup Time to CLOCK Rise Reset Low Pulse Width PA Valid Time from CLOCK Rise PD Setup Time to CLOCK Rise PD Hold Time from CLOCK Rise WAIT Setup Time to CLOCK Rise WAIT Hold Time from CLOCK Rise Halt Setup Time to CLOCK Rise Halt Hold Time from CLOCK Rise Min 50 Max 5 5 20 0 5 15 5 17 8 6 9 1 TCY 18 8 9 9 0 1000 18 2 TCY 25 12 12 28 2 4 12 18 18 20 DS97DSP0100 PRELIMINARY 13 Z89321/371/391 16-Bit Digital Signal Processors Zilog TIMING DIAGRAMS TCY Tr Tf CLOCK DSHOLD DSVALID CPW /DS EASET EAHOLD EA(2:0) Valid Address Out RD//WR RDHOLD RDSET EXT(15:0) Data In Figure 7. Read Timing TCY CLOCK WHOLD WSET WAIT /DS EA(2:0) Valid Address Out RD//WR EXT(15:0) Data In Figure 8. External (EXT) Bus Read Timing Using WAIT Pin 14 PRELIMINARY DS97DSP0100 Z89321/371/391 16-Bit Digital Signal Processors Zilog TIMING DIAGRAMS (Continued) TCY CLOCK DSHOLD DSVALID /DS EASET EAHOLD EA(2:0) Valid Address Out EASET EAHOLD RD//WR WRHOLD WRVALID EXT(15:0) Data Out Figure 9. Write Timing 15 PRELIMINARY DS97DSP0100 Z89321/371/391 16-Bit Digital Signal Processors Zilog TCY CLOCK SSET SCLK FSSET FSSET FS0, FS1 TXSET TXD 1 0 RXHOLD RXSET 1 0 1 RXD 1 0 1 0 1 Figure 10. CODEC Interface Timing TCY CLOCK INTSET INT 0,1,2 INTWidth PROGRAM ADDRESS Fetch N -1 Fetch N Fetch N +1 Fetch Int_Addr Fetch I Fetch I +1 EXECUTE Execute N -1 Execute N CALL Int Routine Execute Int Routine Figure 11. Interrupt Timing 16 PRELIMINARY DS97DSP0100 Z89321/371/391 16-Bit Digital Signal Processors Zilog TIMING DIAGRAMS (Continued) TCY CLOCK HHOLD HSET HALT Figure 12. HALT Timing TCY CLOCK RSET /RESET RWIDTH INTERNAL RESET RRISE EXECUTE Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Code Execution RD/WR /DS UO0-1 EA0-2 EXT0-15 Tri-Stated PA0-15 Tri-Stated Access Reset Vector RAM/ REGISTERS Intact* * The RAM and hardware registers are left intact during a warm reset. A cold reset will produce random data in these locations. The status register is set to zeroes in both cases. Figure 13. RESET Timing 17 PRELIMINARY DS97DSP0100 Z89321/371/391 16-Bit Digital Signal Processors Zilog TCY CLOCK PASET PROGRAM ADDRESS Valid Valid Valid PDSET PDHOLD PROGRAM DATA Valid Valid Valid Figure 14. External Program Memory Port Timing ADDRESS SPACE Program Memory. Programs of up to 4 K words can be masked into internal ROM (OTP for Z89371). Four locations are dedicated to the vector address for the three interrupts (0FFDH-0FFFH) and the starting address following a Reset (0FFCH). Internal ROM is mapped from 0000H to 0FFFH, and the highest location for program is 0FFBH. A 64 K word External Program Memory Space is available on the Z89391. The vector addresses for the Z89391 reside at FFFCH-FFFFH (Figure 15). Internal Data RAM. The Z89321, 371 and 391 all have internal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each: RAM0 and RAM1. Each data RAM bank is addressed by three pointers: Pn:0 (n = 0-2) for RAM0 and Pn:1 (n = 0-2) for RAM1. The RAM addresses for RAM0 and RAM1 are arranged from 0-255 and 256511, respectively. The address pointers, which may be written to, or read from, are 8-bit registers connected to the lower byte of the internal 16-bit D-Bus and are used to perform modulo addressing. Three addressing modes are available to access the Data RAM: register indirect, direct addressing, and short form direct. The contents of the RAM can be read to, or written from, in one machine cycle per word, without disturbing any internal registers or status other than the RAM address pointer used for each RAM. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The Z89321 has 19 internal registers and up to an additional eight external registers. The external registers are user-definable for peripherals, such as A/D or D/A, or to DMA, or other addressing peripherals. Both external and internal registers are accessed in one machine cycle. Data Memory FFFF Program Memory FFFF FFFC INT0-INT2 Vect. RESET Vector 64 Kwords Not Used Not Used Or 512 words DRAM1 DRAM0 01FF 0100 00FF 0000 4 Kwords INT0-INT2 Vect. RESET Vector 0FFF 0FFC 0000 On-Chip Memory Figure 15. Memory Map Off-Chip Memory 18 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors FUNCTIONAL DESCRIPTION Instruction Timing. Most instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. A multiplication or multiplication/accumulate instruction requires a single cycle. Specific instruction cycle times are described in the Condition Code section. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply, or multiply accumulate, in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers where the least significant bits are important, the data should first be scaled by eight bits (or the multiplier and multiplicand by four bits each) to avoid truncation errors. Note that all inputs to the multiplier should be fractional twoOs-complement, 16-bit binary numbers (Figure 16). This puts them in the range [1 to 0.9999695], and the result is in 24 bits so that the range is [1 to 0.9999999]. In addition, if 8000H is loaded into both X and Y registers, the resulting multiplication is considered an illegal operation as an overflow would result. Positive one cannot be represented in fractional notation, and the multiplier will actually yield the result 8000H x 8000H = 8000H (1 x 1 = 1). ALU. The ALU has two input ports, one of which is connected to the output of the 24-bit Accumulator. The other input is connected to the 24-bit P-Bus, the upper 16 bits of which are connected to the 16-bit D-Bus. A shifter between the P-Bus and the ALU input port can shift the data by three bits right, one bit right, one bit left or no shift (Figure 17). 1 DDATA XDATA 16 X Register (16) 16 Y Register (16) DDATA Mult. (24) 16 24 Shift Unit * 24 * Options: 1 Bit Right 3 Bits Right No Shift 1 Bit Left Multiplier P Register (24) 24 24 Shift Unit * 24 MUX 24 * Options: 1 Bit Right 3 Bits Right No Shift 1 Bit Left 24 24 MUX 24 Arithmetic Logic Unit (ALU) 24 Accumulator (24) Figure 17. ALU Block Diagram Figure 16. Multiplier Block Diagram DS97DSP0100 PRELIMINARY 19 Z89321/371/391 16-Bit Digital Signal Processors Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The Call instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the stack to the PC. User Inputs. The Z89321 has two inputs, UI0 and UI1, which may be used by Jump and Call instructions. The Jump or Call tests one of these pins and if appropriate, jumps to a new location. Otherwise, the instruction behaves like a NOP. These inputs are also connected to the status register bits S10 and S11, which may be read by the appropriate instruction (Figure 8). User Outputs. The status register bits S5 and S6 connect directly to UO0 and UO1 pins and may be written to by the appropriate instruction. Note: The user output value is the opposite of the status register content. Interrupts. The Z89321 has three positive edge-triggered interrupt inputs. An interrupt is acknowledged at the end of an instruction execution. It takes two machine cycles to enter an interrupt instruction sequence. The PC is pushed onto the stack. A RET instruction transfers the contents of the stack to the PC and decrements the stack pointer by one word. The priority of the interrupts is INT0 = highest, INT2 = lowest. INT1 is dedicated to the CODEC interface and INT2 is dedicated to the 13-bit timer if both peripherals are enabled. Note: The SIEF instruction enables the interrupts. The SIEF instruction must be used before exiting an interrupt routine since the interrupts are automatically disabled when entering the routine. Registers. The Z89321 has 19 physical internal registers and up to eight user-defined external registers. The EA2EA0 determines the address of the external registers. The signals are used to read from or write to the external registers /DS, WAIT, RD//WR. Zilog I/O Bus. The processor provides a 16-bit, CMOS-compatible bus. I/O Control pins provide convenient communication capabilities with external peripherals, and single-cycle access is possible. For slower communications, an onboard hardware wait-state generator can be used to accommodate timing conflicts. Three latched I/O address pins are used to access external registers. The EXT 4, 5, 6, 7 pins are used by the internal peripherals. Disabling a peripheral allows access to these addresses for generalpurpose use. CODEC Interface. The multi-compatible, dual CODEC interface provides the necessary control signals for transmission of CODEC information to the DSP processor. The interface accommodates 8-bit PCM or 16-bit Linear CODECs. Special compatibility with Crystal Semiconductor's 4215/4216 CODECs provides the necessary interface for audio applications. Many general-purpose 8-, 16-bit A/Ds, D/As are adaptable. The interface can also be used as a high-speed serial port. m-Law Compression. The 8-bit CODEC interface mode provides m-law compression from 13-bit format to 8-bit format. Decompression is performed in software by use of a 128-word lookup table. Timer. Two programmable timers are available. One is dedicated to the CODEC interface, the other for generalpurpose use. When a time-out event occurs, an interrupt request is generated. Single pass and/or continuous modes are available. If the CODEC interface is not used, both timers can be used for general-purpose. Note: Wait-State Generator. An internal wait-state generator is provided to accommodate slow external peripherals. A single wait-state can be implemented through control registers EXT7-2. For additional states, a dedicated pin (WAIT) can be held High. The WAIT pin is monitored only during execution of a read or write instruction to external peripherals (EXT bus). Note: A WAIT pin is not available on the 40-pin DIP package. 20 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors REGISTERS The internal registers are defined below: Register P X Y A SR Pn:b PC EXT4 EXT5-1 EXT5-2 EXT6-1 EXT6-2 EXT7-1 EXT7-2 Register Denition Output of Multiplier, 24-bit X Multiplier Input, 16-bit Y Multiplier Input, 16-bit Accumulator, 24-bit Status Register, 16-bit Six Ram Address Pointers, 8-bit each Program Counter, 16-bit 13-Bit Timer Conguration Register CODEC Interface Channel 0 Data CODEC Interface Channel 0 Data CODEC Interface Channel 1 Data CODEC Interface Channel 1 Data CODEC Interface Conguration Register Wait-State Generator/CODEC Interface Conguration Register EXTn are external registers (n = 0 to 7). There are eight 16-bit registers provided here for mapping external devices into the address space of the processor. Note that the actual register RAM does not exist on the chip, but would exist as part of the external device, such as an ADC result latch. Use of the CODEC interface and 13-bit timer reduces the number of external registers to four. BUS is a read-only register which, when accessed, returns the contents of the D-Bus. Bus is used for emulation only. Dn:b refers to locations in RAM that can be used as a pointer to locations in program memory which is efficient for coefficient addressing. The programmer decides which location to choose from two bits in the status register and two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in RAM. For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in RAM Bank 0. Note that when the data pointers are being written to, a number is actually being loaded to Data RAM, so they can be used as a limited method for writing to RAM. SR is the status register, which contains the ALU status and certain control bits (Table 5). Table 5. Status Register Bit Functions Status Register Bit S15 (N) S14 (OV) S13 (Z) S12 (L) S11 (UI1) S10 (UI0) S9 (SH3) S8 (OP) S7 (IE) S6 (UO1) S5 (UO0) S4-S3 S2-S0 (RPL) Function ALU Negative ALU Overow ALU Zero Carry User Input 1 User Input 0 MPY Output Arithmetically Shifted Right by Three Bits Overow Protection Interrupt Enable User Output 1 User Output 0 OShort Form DirectO bits RAM Pointer Loop Size 1 The following are virtual registers as physical RAM does not exist on the chip. Register Register Denition EXTn External Registers, 16-bit BUS D-Bus Dn:b Eight Data Pointers* Note: * These occupy the first four locations in RAM bank. P holds the result of multiplications and is read-only. X and Y are two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this register, it is placed into the 16 MSBs and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. Pn:b are the pointer registers for accessing data RAM, (n = 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM Bank 0 or 1). They can be directly read from or written to, and can point to locations in data RAM or Program Memory. DS97DSP0100 PRELIMINARY 21 Z89321/371/391 16-Bit Digital Signal Processors The status register can always be read in its entirety. S15S10 are set/reset by hardware and can only be read by software. S9-S0 control hardware looping and can be written by software (Table 6). Table 6. RPL Description S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Loop Size 256 2 4 8 16 32 64 128 Zilog S15-S12 are set/reset by the ALU after an operation. S11S10 are set/reset by the user inputs. S6-S0 are control bits described in Table 5. S7 enables interrupts. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. If S9 is set and a multiple/shift option is used, then the shifter shifts the result three bits right. This feature allows the data to be scaled and prevents overflows. PC is the Program Counter. When this register is assigned as a destination register, one NOP machine cycle is added automatically to adjust the pipeline timing. External Register, EXT4-EXT7, are used by the CODEC interface and 13-bit timer, the registers are reviewed in the CODEC interface section. N S15 OV S14 Z S13 C S12 UI1 S11 UI0 S10 SH3 S9 OP S8 IE S7 UO1 UO0 S6 S5 S4 S3 S2 RPL S1 S0 Ram Pointer Loop Size 000 256 001 2 010 4 011 8 100 16 101 32 110 64 111 128 "Short Form Direct" bits User Output 0-1* Interrupt Enable Overflow protection MPY output arithmetically shifted right by three bits User Input 0-1 (Read Only) Carry Zero Overflow Negative * The output value is the opposite of the status register content. Figure 18. Status Register 22 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors PERIPHERAL OPERATION Disabling Peripherals Disabling a peripheral (CODEC Interface, Counter) allows general-purpose use of the EXT address for the disabled peripheral. If the peripheral is not disabled, the EXT control signals and EXT data are still provided, but transfer of data on the EXT pins is not available (because internal transfers are being processed on the internal bus). Care must be taken to ensure that control of the EXT bus does not cause bus conflicts. EXT5-1 before being transferred along the internal data bus of the processor. This is accomplished by writing data to EXT5-2. 1 Writing Data to CODEC Interface Internal data is transferred from the internal data bus of the processor to the EXT5-2 register. The CODEC interface constantly transfers and receives data during normal operation. Data to be transferred is loaded to EXT5-2 and is automatically serially transferred. Note: EXT5-1 and EXT5-2 are used in the example, but this information applies equally to EXT6-1 and EXT6-2. (Refer to Figure 20, CODEC Block Diagram.) Reading Data from CODEC Interface* External data is serially transferred into the CODEC interface registers from an external CODEC. This serial data is loaded into EXT5-2 (8- or 16-bit modes). Because the interface is double-buffered, data must be transferred to Internal 16-Bit Bus 16 EXT7-1 EXT7-1 EXT7-2 CODEC Timer Register Wait-State Register 16 EXT7-2 Figure 19. EXT7 Register Conguration LOADING EXT7 Because EXT7 is double-buffered, a pair of writes are performed when loading the EXT7 registers (Figure 19). LD EXT7, #%54F4 LD EXT7, #%6CDA LD @P0:0, EXT7 Loads CODEC Timer Register Loads Wait-State Register Reads EXT7-1 and places data in RAM Interrupts The Z89321 features three interrupts: INT0 INT1 INT2 General-Purpose CODEC Interface 13-Bit Timer If all peripherals are enabled, INT0 (general-purpose) can be used. DS97DSP0100 PRELIMINARY 23 Z89321/371/391 16-Bit Digital Signal Processors Zilog CODEC Interface The CODEC Interface provides direct-connect capabilities for standard 8-, 16-bit CODECs. The interface also supports 8-bit PCM, 8-bit PCM with hardware m-law conversion (m-law expansion is done in software), 16-bit Linear and Crystal's Sigma-Delta Stereo CODEC modes. Registers are used to accommodate the CODEC Interface (EXT5, EXT6 and EXT7). The CODEC interface provides two Frame Sync signals, which allows two channels of data for transmission/receiving. CODEC Interface Control Signals SCLK (Serial Clock) The Serial Clock provides a clock signal for operating the external CODEC. A 4-bit prescaler is used to determine the frequency of the output signal. SCLK = (0.5* CLK)/PS where: CLK = System Clock PS = 4-bit Prescaler* * The Prescaler is an up-counter. CODEC Interface Hardware The CODEC Interface hardware uses six 16-bit registers, m-law compression logic and general-purpose logic to control transfers to the appropriate register (Figure 20). Note: An internal divide-by-two is performed before the clock signal is passed to the Serial Clock prescaler. Data Bus 16 16 16 m-Law Compression EXT5-1 CLKIN EXT6-1 CLKIN EXT7-1 16 16 16 16 EXT5-2 CLKIN EXT6-2 CLKIN EXT7-2 CLKIN CONTROL LOGIC TXD RXD Figure 20. CODEC Interface Block Diagram 24 PRELIMINARY DS97DSP0100 Zilog TXD (Serial Output to CODEC) The TXD line provides 8-, 16-, and 64-bit data transfers. Each bit is clocked out of the processor by the rising edge of the SCLK, with the MSB transmitted first. RXD (Serial Input from CODEC) The RXD line provides 8-, 16-, and 64-bit data transfers. Each bit is clocked into the processor by the falling edge of the SCLK, with the MSB received first. Z89321/371/391 16-Bit Digital Signal Processors FS0, FS1 (Frame Sync) The Frame Sync is used for enabling data transfer/receive. The rising and falling edge of the Frame Sync encloses the serial data transmission. Interrupt Once the transmission of serial data is completed an internal interrupt signal is initiated. A single-cycle Low pulse allows an interrupt on INT1. When this occurs, the processor will jump to the defined Interrupt 1 vector location (Figure 21). 1 int1_ fs1 fs0 sclk txd rxd Figure 21. CODEC Interface Timing (8-Bit Mode) CODEC INTERFACE TIMING Figure 21 depicts a typical 8-bit serial data transfer using both of the CODEC Interface Channels. The transmitting data is clocked out on the rising edge of the SCLK signal. An external CODEC clocks data in on the falling edge of the SCLK signal. Once the serial data is transmitted, an interrupt is given. The CODEC interface signals are not initiated if the CODEC interface is not enabled. The following modes are available for FSYNC and SCLK signals: SCLK Internal External External Internal FSYNC Internal External Internal External Full Duplex Operation The Transmit and Receive lines are used for transfer of serial data to or from the CODEC interface. The CODEC interface performs both data transmit and receive simultaneously. Control Registers The CODEC interface is double-buffered, therefore, four registers are provided for CODEC interface data storage. EXT5-1 and EXT5-2 operate with the Frame Sync 0 while EXT6-1 and EXT6-2 operate with Frame Sync 1. In 8- or 16-bit mode, the CODEC interface uses EXT5-1 and EXT6-1. For Stereo mode, all four registers are used (Figures 22 and 23). The CODEC Interface Control Register (EXT7-1) is shown in Figure 14. Setting of the CODEC mode, FSYNC, and Enable/Disable of CODEC 0 is done through this register. The Wait-State Generator, SCLK, and CODEC 1 are controlled from EXT7-2 (Figure 24). The CODEC interface timing is independent of the processor clock when external mode is chosen. This feature provides the capability for an external device to control the transfer of data to the Z89321. The Frame Sync signal envelopes the transmitted data, therefore care must be taken to ensure proper sync signal timing (Figure 21). DS97DSP0100 PRELIMINARY 25 Z89321/371/391 16-Bit Digital Signal Processors Zilog 5-1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Bits 15-0 5-2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Bits 15-0 Figure 22. CODEC Interface Data Registers (Channel 0) 6-1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Bits 15-0 6-2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Bits 15-0 Figure 23. CODEC Interface Data Registers (Channel 1) 26 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors REGISTERS EXT7-1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 SCLK Prescaler (up-counter) SCLK/FSYNC Ratio Prescaler (up-counter) CODEC Mode 00 01 10 11 8-bit with hardware m-law 8-bit without hardware m-law 16-bit linear Crystal CS4215 / CS4216 FSYNC 0 External Source* 1 Internal Source CODEC 0 Disable/Enable Note: The timer is an up-counter. Example: EXT7-1 = #%x00D EXT7-1 = #%x80F EXT7-1 = #%xFFx EXT7-1 = #%x000 OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz No interrupt Max interrupt period (667 ms for OSC = 12.288 MHz) 0 = Disable* 1 = Enable * Default Figure 24. CODEC Interface Control Register DS97DSP0100 PRELIMINARY 27 Z89321/371/391 16-Bit Digital Signal Processors Zilog EXT7-2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Wait State EXT0 Wait State EXT1 nws - no wait states ws - one wait states 00 01 10 11 no wait states (nws) read (nws), write (ws) read (ws), write (nws) read (ws), write (ws) Wait State EXT2 Wait State EXT3 Wait State EXT4 Wait State EXT5 Wait State EXT6 SCLK 0 1 External Source* Internal Source CODEC 1 Disable/Enable 0 = Disable* 1 = Enable *Default Figure 25. WSG, SCLK and CODEC Interface Control Register 28 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors A/D Accommodation The CODEC interface can be used for serial A/D or serial D/A transmission. The interface provides the necessary control signals to adapt to many standard serial converters. The low-pass and smoothing filters are necessary for systems with converters. High-Speed Serial Port The Z89321 CODEC interface can be used as a highspeed serial port. The necessary control signals are provided for adaptation to standard processors or external peripherals. Byte, word, or 64-bit data can be transmitted at speeds up to 10 Mbps. (Condition includes a 20 MHz oscillator. Data can be transferred with single-cycle instructions to an internal register file.) 1 Z89321/371/391 Serial A/D SCLK FSO FS1 CLKIN Communicate Data Serial Data Out Low-Pass Filter Analog In RXD TXD Serial A/D CLKIN Serial Data In Communicate Data Smoothing Filter Analog Out Figure 26. A/D, D/A Implementation Block Diagram Table 7. Tabulated Transmission Rates* Transmission Maximum SCLK Maximum Frame Sync 8-bit 16-bit Stereo (64-bit) Rate 10 Mbps 769.2 kHz 476.2 kHz 263.2 kHz 8-Bit CODEC Interface The Z89321 provides an option for a standard 8-bit CODEC interface. Hardware m-law compression is available (expansion performed by software lookup table). The CODEC interface transmits data consisting of 8-bit or compounded 8-bit information. Figure 27 shows a typical schematic arrangement. The timing for this type of arrangement is presented in Figure 28. The flexible design provides adaptation for 16-bit linear CODEC. Note: Calculations consider the interrupt access time (typically four cycles), transfer of data, loading of new data, and latency periods between CODEC transfers. During the interrupt cycle, developers often execute additional software, affecting the maximum transfer rate. Calculations are for single-channel transfers only. DS97DSP0100 PRELIMINARY 29 Z89321/371/391 16-Bit Digital Signal Processors Zilog Z89321 /371 /391 VCC TXD VDD RXD SCLK RDD RCE DC CCI TDD FS1 TDE VLS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VAG Rx0 +Tx Txl -Tx Mu/A PDI VSS VCC 10k 5k Analog In MC145505p Analog Out GND -5V Figure 27. 8-Bit CODEC Schematic int1_ fs1 fs0 sclk txd rxd Figure 28. 8-Bit Mode Timing Diagram 30 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors For data acquisition systems, designers may opt for a 16bit serial A/D. A block diagram of the Z89321 with the AD1876 16-bit 100 Kbps sampling ADC is shown in Figure 30. 16-Bit Linear CODEC Interface For higher precision transmissions, a 16-bit linear CODEC is used, however, data is not compressed in this mode of transmission. The Z89321 provides accommodation for two channels of 16-bit transmission (Figure 29). 1 int1_ fs1 fs0 sclk txd rxd Figure 29. 16-Bit Mode Timing Diagram Z89321/371/391 AD 1876 UO0 SCLK RxD FS1 Sample CLK Dout Busy Vin Anti-Alias Filtered Analog Signal 16-Bit A/D Figure 30. 16-Bit Mode Timing Diagram DS97DSP0100 PRELIMINARY 31 Z89321/371/391 16-Bit Digital Signal Processors Zilog A key feature of the Z893XX DSP product family is that it adapts easily to other stereo CODECs, including Crystal Semiconductor's CS4215 and CS4216 devices (Figure 31). The 64 bits of data transferred from the CODEC are placed in four registers, EXT5-1, 5-2, 6-1, and 6-2 (Figure 32 ). Stereo CODEC Interface The Z893XX DSP product family CODEC interface provides direct connection to other CODECs for master or slave modes, supporting 64 bits of transmission data (16 bits right channel, 16 bits left channel, and 32 bits of configuration information). This configuration information consists of input gain, input MUX, output attenuation, ADC clipping, and mute and error functions of the CODECs. Ferrite Bead 2.0 +5V Supply 0.1 mF 24 VA Audio Out (Right) 1.0 mF 40k 0.0022mF NPO Audio Out (Left) 1.0 mF 40k 0.0022mF NPO 10mF + 0.1mF 22 + 600 16 LOUT LIN2 + 600 0.01mF NPO 0.47mF 28 150 Channel 2 Input 0.01mF NPO 15 ROUT 1 mF + 0.1 mF 1 mF 4 VD RIN2 0.47mF 26 150 Channel 2 Input + Z89321 /371/391 CS4216 21 REFBYP REFGND RIN1 0.47mF 27 150 Channel 1 Input 0.01mF NPO 43 42 44 1 32 Mode Setting 31 30 29 SCLK SSYNC SDIN SDOUT LIN1 SMODE2 SFS1 SFS2 SMODE1 0.47mF 27 SCLK FS0 TxD RxD 150 Channel 1 Input 0.01mF NPO Figure 31. Z893XX and CS4216 CODEC Interface 32 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors int1_ 1 fs1 fs0 64 bits transferred sclk txd rxd Figure 32. CODEC Stereo Mode Timing Diagram 16-Bit General-Purpose Timer The 13-bit counter/timer is available for general-purpose use. When the counter counts down to the zero state, an interrupt is received on INT2. If the counter is disabled, EXT4 can be used as a general-purpose address. The counting operation of the counter can be disabled by resetting bit 14. Selection of the clock source allows the ability to extend the counter value past the 13 bits available in the control register. Use of the CODEC counter output can extend the counter to 26 bits (see Figure 33). Note: Placing zeroes into the count value register does not generate an interrupt. Therefore, it is possible to have a single-pass option by loading the counter with zeroes after the start of count. The counter is defaulted to the enable state, but if it is not needed, it can be disabled. However, once disabled, the counter cannot be enabled unless a reset of the processor is performed. Example: LD EXT, #%C008 ;1100 0000 0000 1000 ; Enable Counter ; Enable Counting ; Clock Source = OSC/2 ; Count Value = 1000 = 8 ; Interrupt will occur every 16 clock cycles DS97DSP0100 PRELIMINARY 33 Z89321/371/391 16-Bit Digital Signal Processors Zilog ADDRESSING MODES (Continued) EXT4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Count Value (Down-Counter) Clock Source 0 Oscillator/2* 1 CODEC Counter Output Count Operation 0 = Disable* 1 = Enable Counter * Default State 0 = Disable 1 = Enable* Figure 33. CODEC Timer Register ADDRESSING MODES This section discusses the syntax of the addressing modes supported by the DSP assembler. Table 8. Addressing Modes Symbolic Name Pn:b Dn:b X,Y,PC,SR,P , EXTn, A, BUS @A 34 PRELIMINARY DS97DSP0100 Zilog There are eight distinct addressing modes for data transfer. Z89321/371/391 16-Bit Digital Signal Processors specified by a value in RAM, and the location of the RAM is in turn specified by the value in the pointer. Note that the data pointer can also be used for a memory access in this manner, but only one O@O precedes the pointer. In both cases, the memory address stored in RAM is incremented by one, each time the addressing mode is used, to allow easy transfer of sequential data from program memory. 1 CONDITION CODES The following Instruction Description defines the condition codes supported by the DSP assembler. Code C EQ F IE MI NC NE NIE NOV NU0 Description Carry Equal (same as Z) False Interrupts Enabled Minus No Carry Not Equal (same as NZ) Not Interrupts Enabled Not Overow Not User Zero Code NU1 NZ OV PL U0 U1 UGE ULT Z Description Not User One Not zero Overow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero If the instruction description refers to the DS97DSP0100 PRELIMINARY 35 Z89321/371/391 16-Bit Digital Signal Processors Zilog PACKAGE INFORMATION Figure 34. 40-Pin Package Diagram Figure 35. 44-Pin PLCC Package Diagram 36 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors 1 Figure 36. 44-Pin QFP Package Diagram Figure 37. 84-Pin PLCC Package Diagram DS97DSP0100 PRELIMINARY 37 Z89321/371/391 16-Bit Digital Signal Processors Zilog ORDERING INFORMATION Z89321 20 MHz 44-Pin PLCC Z8932120VSC 20 MHz 40-Pin DIP Z8932120PSC 20 MHz 44-Pin QFP Z8932120FSC Z89371 16 MHz 44-pin PLCC Z8937116VSC 16 MHz 40-Pin DIP Z8937116PSC 16 MHz 44-Pin QFP Z8937116FSC Z89391 20 MHz 84-Pin PLCC Z8939120VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package P= Plastic DIP V = Plastic PLCC F = Plastic QFP Temperature S = 0C to +70C E = -40C to 85C Speed 20 = 20 MHz 16 = 16 MHz Environmental C = Plastic Standard Example: Z 89321 20 V S C is a Z89321, 20 MHz, PLCC, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix 38 PRELIMINARY DS97DSP0100 Zilog Z89321/371/391 16-Bit Digital Signal Processors 1 (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. ZilogOs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com DS97DSP0100 PRELIMINARY 39 Z89321/371/391 16-Bit Digital Signal Processors Zilog 40 PRELIMINARY DS97DSP0100 |
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