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Features *On-Chip Latches for Both DACs. *+5V to +12V Operation . *DACs Matched to 1%. *Four Quadrant Multiplication. *TTL/CMOS Compatibel from 5V to 12V. *Full Temperature Operation. *8-bit Endpoint Linearity(+1/2 LSB) *Microprocessor Compatible.
ES52110
8-bit D/A Converter
DESCRIPTION ES52110 contains two & two 8-bit multiplying D/A converter in a single chip.This monolithic construction offers excellent DACto DAC matching and trzcking. The ES 52110 consists of two R-2R resistor-ladder networks, two tracking span resistors, two data latches, one input buffer, and control logic circuit, Both DACs offer excellent four quadrant multiplication characteristics with a separated reference input and feedback resistor for each DAC. Applications *Disk Drives *Digital Gain/Attenuation Control *Digitally-Controlled Filter Parameters
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PIN Assignment
AGND 1 OUT A 2 RFBA 3 VREFA 4 DGND 5 DACA/DACB 6 (MSB)DB7 7 DB6 8 DB5 9 DB4 10 ES52099 (YOP VOEW)
ES52110
8-bit D/A Converter
20 OUT B 19 RFBB 18 VREFB 17 VDD 16 WR 15 CS 14 DB0(LSB) 13 DB 1 12 DR2 11 DB3
Pin Description
Pin NUMBER. 1 NAME AGND TYPE DESCRIPTION The currcnt from the digital input are switched between the DAC OUTPUT and AGND thus maintaining fixed currcnt in cach ladder leg. Independent of switch statc. Analog data is restored from D/A conveter which the digital data is transferred ino ether of the two DAC. Internal feedback resistor
2 20 3 19 4 18 5 6
OUT A OUT B RFB A RFB A VREF A RREF B DGND DAC A/D ACB
O O
The refercnce voltage for the R-2R ladder structure DAC.
I
7-14 15
DB7-DB0 CS
I I
17
VDD
Both DAC latchcs sharc a common s-bit input port. The control input DAC A/D ACB selects which DAC can accept data from the input port. Data bus is TTL./CMOS com -patible. Data is transferred into the either of two latches of DAC. DB0 is the least significant bit Input CS and WR control the operating mode of the selectod DAC. When CS and WR are both ow. The sclected DAC is in the Write mode. The input dath latches of the sclectod DAC are transparcnt and its analog output responds to activity on DB0-DB7 Power
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FUNCTION DESCRIPTION :
ES52110
8-bit D/A Converter
Function Mode The selected DAC latch retains the data which is present on DB0-DB7 just prior to CS or WR assuming a high state.Both analog outputs remain at the values corresponding to the data in their respective latches.
MODE SELECT TABLE DAC A/D ACB CS WR L L L H L L X H X X X H L=Low State H=High State X=Don't Care
DACA WRITE HOLD HOLD HOLD
DACB HOLD WRITE HOLD HOLD
Circuit Description D/A Converter The ES 52110 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly stable R-2R ladder and eight N-channel current steering switches. Asimplified D/A circuit for DAC A is shown in Figure 1. An inverted R-2R ladder structure is used, that is, binary weighted currents are switched between the DAC ouptut and AGND thus maintaining fixed currents in each ladder leg independent of switch state. There is normally closed switch in series with the internal feedback resistor (RFB). This switch improves linearity performance over temperature and power supply rejection; however , when the circuit is not powered up, the switch assumes and open state.
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ES52110
8-bit D/A Converter
Equivalent Circuit Figure 2 shows an approximate equivalent circuit for one of the ES 52110's D/A converters, in this case DAC A. A simpilar equivalent circuit can be drawn for DAC B. Note that AGND is common for both DAC A and DAC B. The current source ILKG is composed of surface and junction leakages , as with most semiconductor devices, apporximately doubles every 10 . The resistor Ro as shown in Figure 2, is the equivalent output resistance of the device which varies with 11k . COUT is the capacitance due to the N-channel switches and varies from about 50Pf to 120pF , depending upon the digital input. g(VREFA,N) is the Thevenin equivalent voltage generator, due to the reference input voltage VREFA and transfer function of the R-2R ladder.
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ABSOLUTE MAXIMUM RATINGS Parameter Min VDD to AGND O VDD to AGND O AGND to DGND O Digital Input Vdtage to DGND -0.3 VPIN2, VPIN20 to AGND -0.3 VREF, VREFB to AGND -25 VRFBA, VRFBB to AGND -25 Operating Temperature Range -55 Junction Temperature Storage Temperature -65 Lead Temperature Notes: Type
ES52110
8-bit D/A Converter
Max +15 +15 VDD+0.3 VDD+0.3 VDD +20 +20 +125 +150 +150 +300
Unit V V V V V V V
1.Do not aplly voltage higher than VDD or less than GND potential on any terminal except VREF. 2.The digital control inputs are Zener-Protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive form at all times until ready for use. 3.Do not insert this device into powered sockets; remove power before insertion or removal. 4.Use proper antistatic handing proced ures. 5.Stressed above those listed under"Abslute Maximum Ratings"may cause permanent damage to the device.
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Application Information
ES52110
8-bit D/A Converter
The most common application of this DAC is voltage output operation. Unipolar output operation provides a 0 to 10 volt output swing when connected, as shown in Figure 4. The maximum output voltage polarity is the inverse of the input reference voltage, since the op amp inverts the input currents. The transfer equation for unipolar operation is V OUT=-VIN D/256, where Dis the decimal value of the data bit inputs DB0 THRU DB7 and V IN is the reference input voltage. The transfer equation highlights another popular applicaton of CMOS DAC's , The output voltage is the product of the reference voltage and the digital input code. The reference input voltage can be any value in the range of VCC volts for both DC or AC signals. The circuit in Figure 4 performs tow-quadrant multiplication. Table 1 provides example analog outputs for the given digital input codes. For biploar output operation connect the ES 52110 as shown in Figure 5. This circuit configuration provides an offset current, derived from the reference to enable the output op amp to swing in both polarities. The digital input coding becomes offset binary . Table 2 provides some example analog outputs for various digital nputs (D). The transfer equation for bipolar operation is VOUT = VINx(D/128-1),where Dis the decimal value of the data bit inputs DB0 thru DB7. This circuit provides full four-quadrant multiplication able to accept both polarities on all input as well as the circuit output.
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ES52110
8-bit D/A Converter
DACLATCH CONTENTS ANALOG OUTPUT MSB LSB (DAC A or DACB) 11111111 -VIN(255/256) 1000001 -VIN(129/256) 10000000 -VIN(128/256) = -VIN /2 01111111 -VIN(127/256) 00000001 -VIN(1/ 256) 00000000 -VIN(0/ 256) = 0 Table 1. Unipolar Binary Code Table. NOTE: 1 LSB = (2 E-8)(VIN) = (1/256)(VIN)
DACLATCH CONTENTS ANALOG OUTPUT MSB LSB (DAC A or DACB) 111111111 +VIN(127/128) 10000001 +VIN(1 /128) 10000000 0 01111111 +VIN(1 /128) 00000001 +VIN(127 /128) 00000000 +VIN(128 /128) Table 1. Unipolar Binary Code Table. NOTE: 1 LSB = (2 E-7)(VIN) = (1/128)(VIN)
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ELECTRICAL CHARACTERISTICS Operating Conditions:
ES52110
8-bit D/A Converter
VDD = +5V5%;VREFA = VREFB = +10V;IOUT A = IOUTB = 0V; TA = Full Temp. Range specified under Absolute Maximum Rating, unless otherwise noted.
Static Accuracy
Parameter Resolution Relative Accuracy (Note 2) Differential Nonlineraity (Note 3) Full-Scale Gain Error (Note 4) Input Resistance (VREFA, VREFB) (Note 6) Input Resistance Match (VREFA/VREFB) Symbol N INL INL GFSE RIN RIN/RIN TA = +25 TA = Full Temp. Range Conditions Min 8 8 Typ Max Units 1/2 1/2 1/2 15 Bits LSB LSB LSB k
0.1
1
%
Digital Inputs (Note 9)
Parameter Digital Input High (Note 8) Digital Input Low (Note 8) Input Current (Note 7) Input Capacitance (Note 10) Symbol VINH VINL VIN CIN TA = +25 TA = Full Temp. Range DB0-DB7 WR, CS, DAV, A/DACB Conditions Min 2.4 Typ 0.01 Max Units 0.8 1 10 10 15 V V A pF
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Switching Characteristics (Note 10,11)
Parameter Chip Select to Write Set-Up To,e Chip Select to Write Hold time Chip Select to Write Hold time Data Select to Write Set-Up time Data Select to Write Hold time Write Pulse Width TWR tDH tDS tAS tCH Symbol tCS Conditions
ES52110
8-bit D/A Converter
Min 100 10 100 100 10 90
Typ
Max Units ns ns ns ns ns ns
Power Supply
Parameter Supply Current Symbol IDD Conditions All Digital Input = VDE or VNL All Digital Input = 0V or VDD TA = +25 TA = Full Temp. Range 0.5 1.0 mA Min Typ Max Units 1 mA
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AC Performance Characteristic
Parameter DC Supply Rejection Ratio (gain/VDD) (Note 13) Current Settling Time (Notes 10, 15, 16, 20) Digital Charge Injection (Note 17) Ouptput Capactiance Symbol Conditions TA = +25 PSRR TA = Full Temp. Range ts Q TA = Full Temp. Range TA = +25
ES52110
8-bit D/A Converter
Min Typ 100 Max Units 0.02 0.04 350 25 25 60 60 -70 -65 -70 -65 %/% ns nVs pF pF dB
COUTA DAC Latches Loaded COUTA With 0000 0000 COUTA DAC Latches Loaded COUTA With 0000 0000 FTA VREFA to IaxA : TA = +25 TA = Full Temp. Range VREFA to IaxA : TA = +25 TA = Full Temp. Range VREFA to IOUTB : VREFA = +20VP-P Sinewave @ f = 10kHz VREFB = 0V;TA = 25 VREFA to IOUTB : VREFA = +20VP-P Sinewave @ f = 10kHz VREFB = 0V;TA = 25 For Code Transition from 0000 0000 to 1111 1111 TA = +25 VDD = 6V @f = 1kHz TA = +25
AC Feedthrough FTA
dB
CCIBA Channel-to-Channel Isolation (Note 19) CCIBA
-80
dB
-80
dB
Digital Crosstalk Harmonic Distortion
Q THD

30 -85

nVs dB
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ES52110
8-bit D/A Converter
Operating Conditions : VDD = +12V5% ;VREFA = VREFB = +10V;IOUTA = IOUTB = 0V;TA = Full Temp. Range specified under Absolute Maximum Rating, unless otherwise noted. Static Accuracy
Parameter Symbol Conditions Min 8 TA = +25 TA = Full Temp. Range Typ 0.5 0.1 0.5 0.1 Max 1/2 1 2 3 Unit Bits LSB LSB LSB Resolution N Relative Accuracy INL (Note 2) Differential Nonlineraity DNL (Note 3) Full-Scale Gain Error GFSE (Note 4) Gain Tmperaturceoefficient TCGFSE (gain/tempertme) (Note 4) Output Leakage Curent IATA(Pin 2)IOUT(Pin 2) ILKG (Note 4) Input Resistance RIN (VREFA, VREFB) (Note 6) Input Resistance Match RIN/RIN (VREFA, VREFB)
TA = +25 TA = Full Temp.Range
0.0035 % 5 200
nA
8
15 1
k %
Digital Inputs (Note 9)
Parameter Digital Input High (Note 8) Digital Input Low (Note 8) Input Current (Note 7) Input Capacitance (Note 10) Symbol VINH VINL IIN CIN TA = +25 TA = Full Temp.Range DB0-DB7 WR,CS,DAV A/DACB Conditions Min 3.4 Typ 0.01 Max 1.5 1 10 10 15 Unit V V A pF
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Switchin g C harac teris tucs (Note 10, 11)
Parameter Chip Select to Write Set-Up Time Chip Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time Data Select to Write Set-Up Time Data Select to Write Hold Time Write Pulse Width TWR 60 TDH 10 TDS 70 TAH 10 TAS 60 TCH 10 Symbol TCS Conditions
ES52110
8-bit D/A Converter
Min 60
Typ
Max
Unit ns ns ns ns ns ns ns

Power Supply
Parameter Symbol Conditions All Digital Input = VINH or VINL TA = +25 Supply Current IDD TA = Full Temp. Range All Digital Input = 0V or VDD TA = +25 TA = Full Temp. Range 0.5 1.0 mA 6 6.5 mA Min Typ Max Unit
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Parameter DC Supply Rejection Ratio (gain /VDD) (Note 13) Current Settling Time (Note 10,15,16,20) Digital Charge Injection (Note 17) Ouptput Capactiance Symbol PSRR ts Q COUTA COUTA COUTA COUTA FTA Conditions TA = +25 TA = Full Temp. Range TA = Full Temp. Range TA = +25 DAC Latches Loaded With 0000 0000 DAC Latches Loaded With 0000 0000 VREFA to IaxA : TA = +25 TA = Full Temp. Range VREFA to IaxA : TA = +25 TA = Full Temp. Range VREFA to IOUTB : VREFA = +20VP-P Sinewave @ f = 10kHz VREFB = 0V;TA = 25 VREFA to IOUTB : VREFA = +20VP-P Sinewave @ f = 10kHz VREFB = 0V;TA = 25 For Code Transition from 0000 0000 to 1111 1111 TA = +25 VDD = 6V @f = 1kHz TA = +25
ES52110
8-bit D/A Converter
Min Typ 160 -80 Max 0.01 0.02 250 25 25 60 60 -70 -65 -70 -65 Unit %/% ns nVs pF pF
AC Feedthrough FTB
dB
dB dB
CCIBA Channel-to-Channel Isolation (Note 19) CCIAB
-80
dB
Digital Crosstalk Harmonic Distortion
Q THD

50 -85

nVs dB
Notes: 1.Specifications apply to both DAC A and DAC B. 2.This is an endpoint linearity specification. 3.All grades guaranteed to be monotonic over the full operating the full operating temp. range. 4.Measured using internal RFBA and RFBB. Both DAC latches loaded with 1111 1111. 5.DAC loaded with 0000 0000. 6.Input resistance TC = 300 ppm/. 7.VIN = 0V or VDD. 8.For all data bits DB0-DB7, WR, CS, DAC A/DACB. 9.Logic inputs are MOS gates. Typical input current(+25)is less than lnA. 10.Guaranteed and not tested. 11.See timing diagram. 12.These characteristics are for design guidance only and not subject to test. 13.VDD = 5%. 14.From digital input to 90% of final analog-output current. 15.VREFA = VREFB = +10V;LOUTA, IOUTB load = 100, CEXT = 13Pf. 16.WR, CS = 0V, DB0-DB7 = 0V to VDD or VDD to 0V.
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ES52110
8-bit D/A Converter
17.For code transition 0000 0000 to 1111 1111. 18.VREFA, VREFB = 20VP-P sinewave @ f = 10kHz. 19.Both DAC latches loaded with 1111 1111. 20.Extrapolated:ts(1/2LSB) = TPD + 6.2, where = the measured first time constant of the fimal RC decay.
WRITE CYCLE TIMING DIAGRAM
Notes: 1.All input signal rise and fall times measured from 10% to 90% are tr = tf = 20ns. 2.Timing measurement reference level is(VIH + VIL)/2.
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ES52110
8-bit D/A Converter
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