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a
Digital PAL/NTSC Video Encoder with Six DACs (10 Bits), Color Control and Enhanced Power Management ADV7172/ADV7173*
Color Signal Control/Burst Signal Control Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation Macrovision AntiTaping Rev 7.01 (ADV7172 Only) 2 Closed Captioning Support Teletext Insertion Port (PAL-WST) On-Board Color Bar Generation On-Board Voltage Reference 2-Wire Serial MPU Interface (I2C (R) Compatible and Fast I2C) Single Supply +5 V or +3.3 V Operation Small 48-Lead LQFP Package APPLICATIONS High Performance DVD Playback Systems, Portable Video Equipment including Digital Still Cameras and Laptop PCs, Video Games, PC Video/Multimedia and Digital Satellite/Cable Systems (Set-Top Boxes/IRD) GENERAL DESCRIPTION
FEATURES ITU-R1 BT601/656 YCrCb to PAL/NTSC Video Encoder Six High Quality 10-Bit Video DACs SSAFTM (Super Sub-Alias Filter) Advanced Power Management Features PC'98-Compliant (TV Detect with Polling and Auto Shutdown to Save On Power Consumption) Low Power DAC Mode Individual DAC ON/OFF Control Variable DAC Output Current (5 mA-36 mA) Ultralow Sleep Mode Current Hue, Brightness, Contrast and Saturation Controls CGMS (Copy Generation Management System) WSS (Wide Screen Signalling) NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60 YUV Betacam, MII and SMPTE Output Levels Single 27 MHz Clock Required ( 2 Oversampling) 80 dB Video SNR 32-Bit Direct Digital Synthesizer for Color Subcarrier Multistandard Video Output Support: Composite (CVBS) Component S-Video (Y/C) Component YUV EuroSCART RGB Component YUV + CHROMA + LUMA + CVBS EuroSCART Output RGB + CHROMA + LUMA + CVBS Programmable Clamping Output Signal Advanced Programmable Power-On Reset Sequencing Video Input Data Port Supports: CCIR-656 4:2:2 8-Bit Parallel Input Format SMPTE 170M NTSC-Compatible Composite Video ITU-R BT.470 PAL-Compatible Composite Video Luma Sharpness Control Programmable Luma Filters (Low-Pass [PAL/NTSC], Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF) Programmable Chroma Filters (Low-Pass [0.65 MHz, 1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF) Programmable VBI (Vertical Blanking Interval) Programmable Subcarrier Frequency and Phase Programmable LUMA Delay CCIR and Square Pixel Operation Integrated Subcarrier Locking to External Video Source
The ADV7172/ADV7173 is an integrated Digital Video Encoder that converts digital CCIR-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with world wide standards. There are six DACs available on the ADV7172/ADV7173. In addition to the Composite output signal there is the facility to output S-VHS Y/C Video, RGB Video and YUV Video. The on-board SSAF (Super Sub-Alias Filter), with extended luminance frequency response and sharp stopband attenuation, enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows extra luminance boost on the frequency response. An advanced power management circuit enables optimal control of power consumption in both normal operating modes and power down or sleep modes. A PC'98-Compliant autodetect feature has been added to allow the user to determine whether or not the DACs are correctly terminated. If not, the ADV7172/ ADV7173 flags that they are not connected through the Status bit and provides the option of automatically powering them down, thereby reducing power consumption.
NOTES *This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. 1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). 2 The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available. SSAF is a trademark of Analog Devices, Inc. 2 I C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADV7172/ADV7173
FUNCTIONAL BLOCK DIAGRAM
CLOCK PAL NTSC CSO_HSO VSO CLAMP HSYNC FIELD/ VSYNC BLANK RESET TTX TTXREQ VAA
8
SCLOCK SDATA
ALSB
VIDEO TIMING GENERATOR
I 2 C MPU PORT
TELETEXT INSERTION BLOCK BRIGHTNESS AND CONTRAST CONTROL + ADD SYNC + INTERPOLATOR
10
YUV TO RBG MATRIX + YUV LEVEL CONTROL BLOCK
10 10
10
Y YCrCb U TO YUV MATRIX V
8
P0 COLOR DATA P7
LUMA PROGRAMMABLE FILTER + SHARPNESS FILTER
10
M U L T I P L E X E R M U L T I P L E X E R
10
10-BIT DAC 10-BIT DAC 10-BIT DAC
DAC A DAC B DAC C VREF RSET2 COMP2 DAC E DAC F DAC D
10 10
DAC CONTROL BLOCK
10
4:2:2 TO 4:4:4 INTERPOLATOR
8
10-BIT DAC 10-BIT DAC 10-BIT DAC
8 8
8
SATURATION CONTROL 10 + ADD BURST 10 + INTERPOLATOR
PROGRAMMABLE CHROMA FILTER
MODULATOR + HUE CONTROL
10 10
10 10
10 10
ADV7172/ADV7173
REAL-TIME CONTROL CIRCUIT
SIN/COS DDS BLOCK
DAC CONTROL BLOCK
RSET1 COMP1
SCRESET/RTC
GND
The ADV7172/ADV7173 also supports both PAL and NTSC square pixel operation. The parts also incorporate WSS and CGMS-A data control generation. The ADV7172/ADV7173 is designed with four color controls (hue, contrast, brightness and saturation). All YUV formats (SMPTE, MII and Betacam) are supported in both PAL and NTSC. The output video frames are synchronized with the incoming data Timing Reference Codes. Optionally the encoder accepts (and can generate) HSYNC , VSYNC and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. The Encoder requires a single two times pixel rate (27 MHz) clock for standard operation. Alternatively the Encoder requires a 24.54 MHz clock for NTSC or 29.5 MHz clock for PAL square pixel mode operation. All internal timing is generated on-chip. HSO/CSO and VSO TTL outputs, synchronous to the analog output video, are also available. A programmable CLAMP output signal is also available to enable clamping in either the front or back porch of the video signal. A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. The ADV7172/ADV7173 modes are set up over a two wire serial bidirectional port (I2C-Compatible) with two slave addresses. Functionally the ADV7173 and ADV7172 are the same with the exception that the ADV7172 can output the Macrovision anticopy algorithm. The ADV7172/ADV7173 is packaged in a 48-lead LQFP package (1.4 mm thickness).
DATA PATH DESCRIPTION
Cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both Y, Cb and Cr. The ADV7172/ ADV7173 supports PAL (B, D, G, H, I, N, M) and NTSC (with and without pedestal) standards. The Y data is then manipulated by being scaled for contrast control and a setup level is added for brightness control. The Cr, Cb data is also scaled and saturation control is added. The appropriate Sync, Blank and Burst levels are then added to the YCrCb data. Macrovision AntiTaping (ADV7172 only), Closed-Captioning and Teletext levels are also added to Y, and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR Filters. The U and V Signals are modulated by the appropriate subcarrier sine/cosine phases and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. The resulting U and V signals are then added together to make up the chrominance signal. The luma (Y) signal can be delayed 1-3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. The luma and chroma signals are then added together to make up the composite video signal. All edges are slew rate limited. The YCrCb data is also used to generate RGB data with appropriate Sync and Blank levels. The YUV levels are also scaled to output the suitable SMPTE or Betacam levels. There are six DACs on the ADV7172/ADV7173. Three of these DACs are capable of providing 34.66 mA of current. The other three DACs provide 8.66 mA each. The six l0-bit DACs can be used to output: 1. Composite Video + RGB Video + LUMA + CHROMA. 2. Composite Video + YUV Video + LUMA + CHROMA. Alternatively, each DAC can be individually powered off if not required. A complete description of DAC output configurations is given in Appendix 8. Video output levels are illustrated in Appendix 6.
(continued on page 11)
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb 4:2:2 Data is input via the CCIR-656-Compatible Pixel Port at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form three data paths. Y typically has a range of 16 to 235, Cr and
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REV. A
SPECIFICATIONS(V
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN
ADV7172/ADV7173
AA =
5 V SPECIFICATIONS unless otherwise noted)
+5 V
5%1, VREF = 1.235 V, R SET1,2 = 600
Test Conditions1
unless otherwise noted. All specifications TMIN to TMAX2
Min Typ Max 10 1.0 1.0 2 Units Bits LSB LSB V V A pF V V A pF mA mA mA mA % % V k pF V V mA mA mA mA mA mA A A %/%
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V 10 ISOURCE = 400 A ISINK = 3.2 mA 2.4
0.8 1
DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS Output Current (DACs A, B, C)4 Output Current (DACs A, B, C)5 Output Current (DACs D, E, F)6 Output Current (DACs D, E, F)5 DAC-to-DAC Matching (DACs A, B, C)7 DAC-to-DAC Matching (DACs D, E, F)7 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF POWER REQUIREMENTS VAA Normal Power Mode IDAC (max)8, 9 IDAC (min)8, 9 ICCT10 Low Power Mode IDAC (max)11 IDAC (min)11 ICCT10 Sleep Mode IDAC12 ICCT13 Power Supply Rejection Ratio
0.4 10 10
RSET1 = 150 , R L = 37.5 RSET1 = 1041 , R L = 262.5 RSET2 = 600 , R L = 150 RSET2 = 1041 , R L = 262.5
33 8.25
34.7 5 8.66 5 1 1 30
37 9.25 4.0 4.0 +1.4 30
0 IOUT = 0 mA IVREFOUT = 20 A 1.112 4.75 RSET1,2 = 600 RSET1,2 = 1041 RSET1 = 150 1.235 5.0 59 30 78 64 15 78 0.1 0.1 0.01
1.359 5.25 65 90
90
COMP = 0.1 F
0.5
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 Characterized by design. 4 Full drive into 75 doubly terminated load. 5 Minimum drive current (used with buffered/scaled output load). 6 Full drive into 150 load. 7 Specification guaranteed by characterization. 8 IDAC is the total current ("min" corresponds to 5 mA output per DAC, "max" corresponds to 8.66 mA output per DAC ) to drive DACs A, B, C, D, E, F. Turning off individual DACs reduces I DAC correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA but DAC D, E, F must be turned off. 9 All six DACs on (DAC A, B, C, D, E, F). 10 I CCT (Circuit Current) is the continuous current required to drive the device. 11 Only large DACs (DACs A, B, C) on per low power mode. 12 Total DAC current in Sleep Mode. 13 Total continuous current during Sleep Mode. Specifications subject to change without notice.
REV. A
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ADV7172/ADV7173-SPECIFICATIONS
3.3 V SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS3 Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS3 Output Current (DACs A, B, C)4 Output Current (DACs A, B, C)5 Output Current (DACs D, E, F)6 Output Current (DACs D, E, F)5 DAC-to-DAC Matching (DACs A, B, C)3 DAC-to-DAC Matching (DACs D, E, F)3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT POWER REQUIREMENTS VAA Normal Power Mode IDAC (max)8, 9 IDAC (min)8 ICCT10 Sleep Mode IDAC11 ICCT12 Power Supply Rejection Ratio
3, 7 3
(VAA = +3.0 V-3.6 V 1, VREF = 1.235 V, R SET1,2 = 600 unless otherwise noted)
Test Conditions1
unless otherwise noted. All specifications TMIN to TMAX2
Min Typ Max 10 1.0 1.0 2 0.8 Units Bits LSB LSB V V A pF V V A pF mA mA mA mA % % V k pF V mA mA mA A A %/%
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V 10 ISOURCE = 400 A ISINK = 3.2 mA 2.4 0.4
1
10 10 RSET1 = 150 , R L = 37.5 RSET1 = 1041 , R L = 262.5 RSET2 = 600 , R L = 150 RSET2 = 1041 , R L = 262.5 34.7 5 8.66 5 1 1 30 IOUT = 0 mA 3.0 RSET1,2 = 600 RSET1,2 = 1041 3.3 58 30 40 0.1 0.1 0.01 30 3.6 65
4.0 4.0 +1.4
COMP = 0.1 F
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 Guaranteed by characterization. 4 Full drive into 75 doubly terminated load. 5 Minimum drive current (used with buffered/scaled output load). 6 Full Drive into 150 load. 7 Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110C. 8 IDAC is the total current ("min" corresponds to 5 mA output per DAC, "max" corresponds to 8.66 mA output per DAC ) to drive DACs A, B, C, D, E, F. Turning off individual DACs reduces I DAC correspondingly, also DACs A, B, C can be configured to output a max current of 37 mA. 9 DACs A, B, C can output 35 mA typically at 3.3 V (R SET = 150 and RL = 37.5 ), optimum performance obtained at 18 mA DAC Current (RSET = 300 and RL = 75 ). 10 I CCT (Circuit Current) is the continuous current required to drive the device. 11 Total DAC current in Sleep Mode. 12 Total continuous current during Sleep Mode. Specifications subject to change without notice.
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REV. A
ADV7172/ADV7173 5 V DYNAMIC SPECIFICATIONS
Parameter Differential Gain Differential Phase3, 4 Differential Gain3, 4 Differential Phase3, 4 SNR3, 4 (Pedestal) SNR3, 4 (Pedestal) SNR3, 4 (Ramp) SNR3, 4 (Ramp) Hue Accuracy3, 4 Color Saturation Accuracy3, 4 Chroma Nonlinear Gain3, 4 Chroma Nonlinear Phase3, 4 Chroma/Luma Intermod3, 4 Chroma/Luma Gain Inequality3, 4 Chroma/Luma Delay Inequality3, 4 Luminance Nonlinearity3, 4 Chroma AM Noise3, 4 Chroma PM Noise3, 4
3, 4
(VAA = +5 V 5% , VREF = 1.235 V, RSET1,2 = 600 unless otherwise noted. All specifications TMIN to TMAX 2 unless otherwise noted.)
Min Typ 0.3 0.4 0.5 2.0 75 66 60 58 0.7 0.9 1.2 0.3 0.2 1.0 0.5 1.0 82 80 Max 0.7 0.7 1.0 3.0 Units % Degrees % Degrees dB rms dB p-p dB rms dB p-p Degrees % % Degrees % % ns % dB dB
1
Conditions1 Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic
Referenced to 40 IRE
0.5 0.4
1.7
79 79
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 These specifications are for the low-pass filter only and guaranteed by design. 4 Guaranteed by characterization. Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS
Parameter Differential Gain Differential Phase3 Differential Gain3 Differential Phase3 SNR3 (Pedestal) SNR3 (Pedestal) SNR3 (Ramp) SNR3 (Ramp) Hue Accuracy3 Color Saturation Accuracy3 Luminance Nonlinearity3 Chroma AM Noise3 Chroma PM Noise3 Chroma Nonlinear Gain3, 4 Chroma Nonlinear Phase3, 4 Chroma/Luma Intermod3, 4
3
(VAA = +3.0 V - 3.6 V1, VREF = 1.235 V, RSET1,2 = 600 unless otherwise noted. All specifications TMIN to TMAX 2 unless otherwise noted.)
Min Typ 0.6 0.5 1.0 0.5 75 70 60 58 1.0 1.0 1.1 83 79 1.2 0.3 0.2 Max Units % Degrees % Degrees dB rms dB p-p dB rms dB p-p Degrees % % dB dB % Degrees %
Conditions1 Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic
Referenced to 40 IRE
NOTES 1 The max/min specification are guaranteed over this range. The max with values are typical over a 3.0 V to 3.6 V range. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and guaranteed by design. Specifications subject to change without notice.
REV. A
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ADV7172/ADV7173 5 V TIMING SPECIFICATIONS
Parameter MPU PORT3, 4 SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT5, 6 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 TELETEXT PORT3, 7 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3 RESET Low Time
3, 5
(VAA = +5 V 5%1, VREF = 1.235 V, RSET1 = 600 TMIN to TMAX2 unless otherwise noted.)
unless otherwise noted. All specifications
Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Units kHz s s s s ns ns ns s ns ns
Conditions
After this period the 1st clock is generated relevant for repeated Start Condition.
300 300 0.6 7 0
27 8 8 4.0 5.0 4 3 15 10 37 20 2 6 3 24
MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel Port consists of the following: Pixel Inputs: P7-P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP Clock Input: CLOCK 7 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice.
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REV. A
ADV7172/ADV7173 3.3 V TIMING SPECIFICATIONS
Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT4, 5, 6 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 TELETEXT PORT3, 4, 7 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time
3, 4
(VAA = +3.0 V-3.6 V1, VREF = 1.235 V, RSET1,2 = 600 otherwise noted.)
. All specifications TMIN to TMAX2 unless
Typ Max 400 Units kHz s s s s ns ns ns s ns ns
Conditions
Min 0 0.6 1.3 0.6 0.6 100
After this period the 1st clock is generated relevant for repeated Start Condition.
300 300 0.6 7 0
27 8 8 4.0 5 5 3 20 12 37 23 2 6 3
MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range. 2 Temperature range T MIN to T MAX: 0C to +70C. 3 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel Port consists of the following: Pixel Inputs: P7-P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP Clock Input: CLOCK 7 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice.
REV. A
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ADV7172/ADV7173
t5 t3
SDATA
t3
t6 t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
CONTROL I/PS HSYNC, FIELD/VSYNC, BLANK
t10
t12
PIXEL INPUT DATA HSYNC, FIELD/VSYNC, BLANK, CSO_HSO, VSO, CLAMP
Cb
Y
Cr
Y
Cb
Y
t11
t13
CONTROL O/PS
t14
Figure 2. Pixel and Control Data Timing Diagram
TXTREQ
t16
CLOCK
t17
TXT
t18
4 CLOCK CYCLES
4 CLOCK CYCLES
4 CLOCK CYCLES
3 CLOCK CYCLES
4 CLOCK CYCLES
Figure 3. Teletext Timing Diagram
DAC Average Current Consumption
DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by RSET2/VREF (see Appendix 8). DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by RSET1 (see Appendix 8). In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by RSET1.
Table I. Allowable Operating Configurations DACs A, B, C 3 DACs ON 3 DACs ON 3 DACs ON 3 DACs ON 3 DACs ON Output Current 37 mA 37 mA 37 mA 8.66 mA 4.33 mA Average DAC Current Consumption See Above 18.5 mA (See Above) 18.5 mA (See Above) See Above See Above DACs D, E, F 3 DACs ON 3 DACs ON 3 DACs OFF 3 DACs ON 3 DACs ON Output Current 8.66 mA 8.66 mA 8.66 mA 4.33 mA Average DAC Current Consumption See Above See Above See Above See Above See Above Power Mode Normal Low Power Low Power Normal Normal
5 V? No No Yes Yes Yes
3 V? Yes Yes Yes Yes Yes
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REV. A
ADV7172/ADV7173
ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . GND - 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +260C Analog Outputs to GND2 . . . . . . . . . . . GND - 0.5 V to VAA
NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Analog output short circuit to any power supply or common can be of an indefinite duration.
The 48-lead LQFP package is used for this device. The junctionto-ambient (JA) thermal resistance in still air on a four layer PCB is +54.6C/W. The junction-to-case thermal resistance (JC) is +16.7C. To reduce power consumption when using this part the user is advised to run the part on a 3.3 V supply, turn off any unused DACs. However, if 5 V operation is required the user can enable Low Power mode by setting MR16 to a Logic 1. Another alternative way to further reduce power is to use external buffers that dramatically reduce the DAC currents, the current can be lowered to as low as 5 mA (see Appendix 8 for more details) from a nominal value of 36 mA. The user must at all times stay below the maximum junction temperature of +110C. The following equation shows how to calculate this junction temperature:
PIN CONFIGURATION
SCRESET/RTC
Junction Temperature = [VAA (IDAC + ICCT) x JA ] +70C
where IDAC = 10 mA + (sum of the average currents consumed by each powered-on DAC).
VSO RESET PAL NTSC
TTXREQ
CLOCK
CLAMP TTX
RSET1
GND
48 47 46 45 44 43 42 41 40 39 38 37
VAA
1 PIN 1 IDENTIFIER
VAA
VREF
36 35 34 33 32
COMP1 DAC A VAA DAC B VAA
P0 2 P1 3 P2 4 P3 5 P4 6 P5 7 P6 8 P7 CSO HSO 10 VAA 11 GND 12
9
ORDERING GUIDE
ADV7172/ADV7173
TOP VIEW (Not to Scale)
31
GND 30 VAA
29 28 27 26 25
Model ADV7172KST ADV7173KST
Temperature Range 0C to +70C 0C to +70C
Package Description Plastic Thin Quad Flatpack Plastic Thin Quad Flatpack
Package Option ST-48 ST-48
DAC C DAC D VAA GND DAC E
13 14 15 16 17 18 19 20 21 22 23 24
FIELD/VSYNC
HSYNC
SCLOCK
COMP2
BLANK
ALSB
GND
SDATA
RSET2
GND
VAA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7172/ADV7173 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
DAC F
WARNING!
ESD SENSITIVE DEVICE
REV. A
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ADV7172/ADV7173
PIN FUNCTION DESCRIPTION
Mnemonic P7-P0 CLOCK HSYNC FIELD/VSYNC
Input/Output I I I/O I/O
Function 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7-P0) P0 represents the LSB. TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master Mode) or as an input and accept (Slave Mode) Sync signals. Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (Master Mode) or as an input (Slave Mode) and accept these control signals. Video Blanking Control Signal. The pixel inputs are ignored when this is logic level "0." This signal is optional. This pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It can be configured as a subcarrier reset pin, in which case a high to low transition on this pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a RealTime Control (RTC) Input. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). A 150 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from DACs A, B and C (the "large" DACs). A 600 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from DACs D, E and F (the "small" DACs). Compensation Pin for DACs A, B and C. Connect a 0.1 F Capacitor from COMP to VAA. For Optimum Dynamic Performance in Low Power Mode, the value of the COMP1 capacitor can be lowered to as low as 2.2 nF. Compensation Pin for DACs D, E and F. Connect a 0.1 F Capacitor from COMP to VAA. GREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output. BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output. RED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output. GREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output. BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output. RED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output. MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. TTL Output Signal to external circuitry to enable clamping of all video signals. Input signal to select PAL or NTSC mode of operation, pin set to Logic "1" selects PAL. VSO TTL Output Sync Signal. Dual function CSO or HSO TTL Output Sync Signal. TTL Address Input. This signal sets up the LSB of the MPU address. The input resets the on-chip timing generator and sets the ADV7172/ADV7173 into default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B and C powered OFF, DACs D, E and F powered ON, Composite and S-Video out. Teletext Data Input Pin. Teletext Data Request output signal used to control teletext data transfer. Power Supply (+3 V to +5 V). Ground Pin.
BLANK SCRESET/RTC
I/O I
VREF RSET1 RSET2 COMP1
I/O I I O
COMP2 DAC A DAC B DAC C DAC D DAC E DAC F SCLOCK SDATA CLAMP PAL_NTSC VSO CSO_HSO ALSB RESET
O O O O O O O I I/O O I O O I I
TTX TTXREQ VAA GND
I O P G
-10-
REV. A
ADV7172/ADV7173
(continued from page 2)
INTERNAL FILTER RESPONSE The Y Filter supports several different frequency responses, including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response and a QCIF response. The UV Filter supports several different frequency responses, including four low-pass responses, a CIF response and a QCIF response. These can be seen in Figures 4 to 18.
In Extended Mode there is the option of twelve responses in the range from -4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen in Figures 19 to 21.
FILTER TYPE LOW-PASS (NTSC) LOW-PASS (PAL) NOTCH (NTSC) NOTCH (PAL) EXTENDED (SSAF) CIF QCIF
FILTER SELECTION MR04 0 0 0 0 1 1 1 MR03 0 0 1 1 0 0 1 MR02 0 1 0 1 0 1 0
PASSBAND RIPPLE 3 dB BANDWIDTH (dB) (MHz) 0.091 0.15 0.015 0.095 0.051 0.018 MONOTONIC 4.157 4.74 6.54 6.24 6.217 3.0 1.5
STOPBAND STOPBAND CUTOFF (MHz) ATTENUATION (dB) 7.37 7.96 8.3 8.0 8.0 7.06 7.15 -56 -64 -68 -66 -61 -61 -50
Figure 4. Luminance Internal Filter Specifications
FILTER TYPE 1.3 MHz LOW PASS 0.65 MHz LOW PASS 1.0 MHz LOW PASS 2.0 MHz LOW PASS RESERVED CIF QCIF
FILTER SELECTION MR07 0 0 0 0 1 1 1 MR06 0 0 1 1 0 0 1 MR05 0 1 0 1 0 1 0
STOPBAND STOPBAND PASSBAND RIPPLE 3 dB BANDWIDTH CUTOFF (MHz) ATTENUATION (dB) (dB) (MHz) 0.084 MONOTONIC MONOTONIC 0.0645 0.084 MONOTONIC 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 -45 -58.5 -49 -40 -45 -50
Figure 5. Chrominance Internal Filter Specifications
0
0
-10 -20 MAGNITUDE - dB -30 MAGNITUDE - dB 0 2 4 6 8 FREQUENCY - MHz 10 12
-10 -20 -30
-40 -50 -60 -70
-40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 6. NTSC Low-Pass Luma Filter
Figure 7. PAL Low-Pass Luma Filter
REV. A
-11-
ADV7172/ADV7173
0 0 -10 -10 -20 MAGNITUDE - dB MAGNITUDE - dB 14 -30
-20 -30
-40 -50 -60 -70
-40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
14
Figure 8. NTSC Notch Luma Filter
Figure 11. CIF Luma Filter
0 -10 -20 MAGNITUDE - dB MAGNITUDE - dB 0 2 4 6 8 FREQUENCY - MHz 10 12 14
0
-10 -20 -30
-30 -40 -50
-40 -50 -60 -70
-60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
14
Figure 9. PAL Notch Luma Filter
Figure 12. QCIF Luma Filter
0 -10
0
-10 -20 MAGNITUDE - dB 0 2 4 6 8 FREQUENCY - MHz 10 12 14 -30
-20 MAGNITUDE - dB -30 -40
-40 -50 -60 -70
-50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
14
Figure 10. Extended Mode (SSAF) Luma Filter
Figure 13. 1.3 MHz Low-Pass Chroma Filter
-12-
REV. A
ADV7172/ADV7173
0 0 -10 -20 MAGNITUDE - dB -30 MAGNITUDE - dB 14 -10 -20 -30
-40 -50 -60 -70
-40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
14
Figure 14. 0.65 MHz Low-Pass Chroma Filter
Figure 17. CIF Chroma Filter
0 -10
0 -10
-20 MAGNITUDE - dB -30 -40 MAGNITUDE - dB 14
-20 -30
-40 -50 -60 -70
-50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
14
Figure 15. 1.0 MHz Low-Pass Chroma Filter
Figure 18. QCIF Chroma Filter
0
0
-10 -5 -20 MAGNITUDE - dB MAGNITUDE - dB 0 2 4 6 8 FREQUENCY - MHz 10 12 14 -30 -10
-40 -50
-15
-20 -60 -70
-25
0
1
2
3 4 5 FREQUENCY - MHz
6
7
8
Figure 16. 2.0 MHz Low-Pass Chroma Filter
Figure 19. Extended Mode Luma Filter with Programmable Gain, Negative Response
REV. A
-13-
ADV7172/ADV7173
4 4 3 AMPLITUDE - dB 2 1 0 -1 -10 -2 -12 -3 0 1 2 3 4 FREQUENCY - MHz 5 6 7 1 2 3 4 FREQUENCY - MHz 5 6 MAGNITUDE - dB 2 0 -2 -4 -6 -8
Figure 20. Extended Mode Luma Filter with Programmable Gain, Positive Response
Figure 21. Extended Mode Luma Filter with Programmable Gain, Combined Response
COLOR BAR GENERATION
The ADV7172/ADV7173 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75% amplitude, 100% saturation (100/0/75/0) for PAL color bars. These are enabled by setting MR46 of Mode Register 4 to Logic "1."
SQUARE PIXEL MODE
onto the Y data in PAL mode, NTSC mode without pedestal or NTSC mode with pedestal, in which case it is added directly onto the 7.5 IRE pedestal already present. The level added is programmed by the user into the Brightness Control Register (Bits 4-0) and the user is capable of adding from 0 IRE to a maximum of 14 IRE in 32 (25) steps. Because of different gains in the datapath for each mode, different values may need to be programmed to obtain the same IRE setup level in each mode. Maximum brightness is achieved when 31 is programmed into the Brightness Control Register. Table II illustrates the maximum setup/brightness amplitudes available in the various modes. Note that if a level of less than 7.5 IRE is required on the Y data in NTSC mode, then NTSC without pedestal must be the mode selected.
Table II. Maximum Brightness Levels Available
The ADV7172/ADV7173 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. COLOR SIGNAL CONTROL The color information can be switched on and off the video output using Bit MR44 of Mode Register 4. BURST SIGNAL CONTROL The burst information can be switched on and off the video output using Bit MR45 of Mode Register 4. NTSC PEDESTAL CONTROL The pedestal on both odd and even fields can be controlled on a line-by-line basis using the NTSC Pedestal Control Registers. This allows the pedestals to be controlled during the Vertical Blanking Interval (lines 10 to 25 and lines 273 to 288). COLOR CONTROLS The ADV7172/ADV7173 allows the user the advantage of controlling the brightness, contrast, hue and saturation of the color.
Contrast Control
Mode NTSC No Pedestal NTSC Pedestal PAL
Brightness Control Register 00011111 00011111 00011111
Setup 14 IRE 13 IRE 99 mV
Color Saturation Control
Color adjustment is achieved by scaling the Cr and Cb input data by a factor programmed by the user into the Color Control Registers 1 and 2, Bits 5-0. This factor allows the data to be scaled between 75% and 125%.
Hue Control
Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user into the Contrast Control Register Bits 5-0. This factor allows the data to be scaled between 75% and 125%.
Brightness Control
The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added
The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the color burst is modified and hence the hue is shifted. Hue adjustment is under the control of the Hue Control Register. The ADV7172/ADV7173 provides a range of 22 change in increments of 0.17578125.
-14-
REV. A
ADV7172/ADV7173
YUV LEVELS
625/50 systems, Lines 624 to Line 22 and lines 311 to 335. The "Opened VBI" consists of: 525/60 systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2. 625/50 systems, Line 7 to Line 22 and Lines 319 to 335.
SUBCARRIER RESET
This functionality is under the control of Mode Register 5, Bits 2-0. Bit 0 (MR50) allows the ADV7172/ADV7173 to output SMPTE levels on the Y output when configured in NTSC mode, and Betacam levels on the Y output when configured in PAL mode and vice-versa. Betacam SMPTE Video 286 mV 300 mV Sync 714 mV 700 mV
As the datapath is branched at the output of the filters, the luma signal relating to the CVBS or S-Video Y/C output is unaltered. Only the Y output of the YUV outputs is scaled. Bits 2-1 (MR52-MR51) allow UV levels to have a peak-peak amplitude of 700 mV or 1000 mV, or the default values of 934 mV in NTSC and 700 mV in PAL.
AUTODETECT CONTROL
Together with the SCRESET/RTC PIN and Bits MR42 and MR41 of Mode Register 4, the ADV7172/ADV7173 can be used in subcarrier reset mode. The subcarrier phase will reset to Field 0 at the start of the following field when a low to high transition occurs on this input pin.
REAL-TIME CONTROL
The ADV7172/ADV7173 provides the option of automatically powering down the DACs A, B and C if they are not correctly terminated (i.e., the 75 cable is not connected to the DAC). The voltage at the output of DACs A and B are compared to a selected reference level. This reference voltage (MR64) will depend on whether the user terminates with 37.5 (75 connected on the DAC end and 75 connected at TV end of cable, i.e., combined load of 37.5 ) or 75 . It cannot operate in a DAC buffering configuration. There are two modes of autodetect operation provided by the ADV7172/ADV7173: (1) Mode 0: The state of termination of the DAC may be read by reading the status bits in Mode Register 6. MR67 status bit indicates whether or not the composite DAC is terminated, MR66 status bit indicates whether or not the luma DAC is terminated. The user may then decide whether or not to power down the DACs using MR15-MR0. (2) Mode 1: The state of the DACs may be read as in Mode 0. If either of the DACs is unterminated, they are automatically powered down. If the luma DAC, DAC B is powered down then DAC C, the chroma DAC, will also be powered down. The state of termination of the DAC is checked each frame to decide whether or not it is to be powered up or down. Mode Register 6, Bits 3-2, indicates which mode of operation is used. Note that Mode Register 1, Bits 5-3, must be enabled ("1") for autodetect functionality to work. (DACs A, B, C are enabled.)
Vertical Blanking Data Insertion
Together with the SCRESET/RTC PIN and Bits MR42 and MR41 of Mode Register 4, the ADV7172/ADV7173 can be used to lock to an external video source. The real-time control mode allows the ADV7172/ADV7173 to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs a digital data stream in the RTC format (such as a ADV7185 video decoder, see Figure 22), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex should be written into all four subcarrier frequency registers when using this mode.
VIDEO TIMING DESCRIPTION
The ADV7172/ADV7173 is intended to interface to off-theshelf MPEG1 and MPEG2 Decoders. As a consequence, the ADV7172/ADV7173 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. The ADV7172/ADV7173 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7172/ADV7173 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required. In addition, the ADV7172/ADV7173 supports a PAL or NTSC square pixel operation in slave mode. The part requires an input pixel clock of 24.5454 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7172/ADV7173 has four distinct master and four distinct slave timing configurations. Timing control is established with the bidirectional SYNC, BLANK and FIELD/ VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other.
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/postequalization pulses (see Figures 24 to 25). This mode of operation is called "Partial Blanking" and is selected by setting MR32 to "1." It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS etc.). Alternatively the entire VBI may be blanked (no VBI data inserted) on these lines by setting MR32 to "0." The complete VBI comprises of the following lines: 525/60 systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
REV. A
-15-
ADV7172/ADV7173
CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE VIDEO DECODER (e.g., ADV7185) SCRESET/RTC M U X GREEN/COMPOSITE/Y BLUE/LUMA/U P7-P0 RED/CHROMA/V GREEN/COMPOSITE/Y HSYNC FIELD/VSYNC BLUE/LUMA/U RED/CHROMA/V
MPEG DECODER
ADV7172/ADV7173
H/LTRANSITION COUNT START LOW 128 13 14 BITS RESERVED 0 4 BITS RESERVED 21 FSCPLL INCREMENT1 SEQUENCE BIT2 RESET BIT3 5 BITS RESERVED RESERVED 0
RTC TIME SLOT: 01 14 NOT USED IN ADV7172/ADV7173 19 VALID SAMPLE INVALID SAMPLE 8/LLC 67 68
NOTES: 1F SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER IS FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7172/ADV7173. 2 SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3 RESET BIT RESET ADV7172/ADV7173's DDS
Figure 22. RTC Timing and Connections
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC and BLANK (if not used) pins should be tied high during this mode.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F00X8181 YrYF00Y0000 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE 81 81F00XC C C C C 00 00F00YbY rYbYr Yb
NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz)
4 CLOCK
4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE
Figure 23. Timing Mode 0 (Slave Mode)
-16-
REV. A
ADV7172/ADV7173
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7172/ADV7173 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 26.
DISPLAY VERTICAL BLANK DISPLAY
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H V F
EVEN FIELD ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
H V F
ODD FIELD EVEN FIELD
Figure 24. Timing Mode 0 (NTSC Master Mode)
DISPLAY VERTICAL BLANK
DISPLAY
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H V F
EVEN FIELD ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
H V F
ODD FIELD EVEN FIELD
Figure 25. Timing Mode 0 (PAL Master Mode)
REV. A
-17-
ADV7172/ADV7173
ANALOG VIDEO
H
F
V
Figure 26. Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7172/ADV7173 accepts horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260 HSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 27. Timing Mode 1 (NTSC)
-18-
REV. A
ADV7172/ADV7173
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 1 (PAL)
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7172/ADV7173 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates the HSYNC, BLANK and FIELD for an odd-or-even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK
PIXEL DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2
Figure 29. Timing Mode 1 Odd/Even Field Transitions Master/Slave
REV. A
-19-
ADV7172/ADV7173
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7172/ADV7173 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL).
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
260 HSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
BLANK VSYNC
ODD FIELD
EVEN FIELD
Figure 30. Timing Mode 2 (NTSC)
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC BLANK VSYNC
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK VSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 31. Timing Mode 2 (PAL)
-20-
REV. A
ADV7172/ADV7173
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7172/ADV7173 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL). Figure 32 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 33 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2 BLANK NTSC = 16 * CLOCK/2
PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
Figure 32. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PAL = 864 * CLOCK/2 NTSC = 858 * CLOCK/2
PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
Cb
Figure 33. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
REV. A
-21-
ADV7172/ADV7173
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7172/ADV7173 accepts or generates horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 34 (NTSC) and Figure 35 (PAL).
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260 HSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 34. Timing Mode 3 (NTSC)
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 35. Timing Mode 3 (PAL)
-22-
REV. A
ADV7172/ADV7173
OUTPUT VIDEO TIMING POWER-ON RESET
The video timing generator generates the appropriate sync, blank and burst sequence that controls the output analog waveforms. These sequences are summarized below. In slave modes, the following sequences are synchronized with the input timing control signals. In master modes, the timing generator free runs and generates the following sequences in addition to the output timing control signals. NTSC-Interlaced: Scan Lines 1-9 and 264-272 are always blanked and vertical sync pulses are included. Scan Lines 525, 10-21 and 262, 263, 273-284 are also blanked and can be used for closed captioning data. Burst is disabled on Lines 1-6, 261- 269 and 523-525. NTSC-Noninterlaced: Scan Lines 1-9 are always blanked and vertical sync pulses are included. Scan Lines 10-21 are also blanked and can be used for closed captioning data. Burst is disabled on Lines 1-6, 261-262. PAL-Interlaced: Scan Lines 1-6, 311-318 and 624-625 are always blanked and vertical sync pulses are included in Fields 1, 2, 5 and 6. Scan Lines 1-5, 311-319 and 624-625 are always blanked and vertical sync pulses are included in Fields 3, 4, 7 and 8. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1-6, 311-318 and 623-625 in Fields 1, 2, 5 and 6. Burst is disabled on Lines 1-5, 311-319 and 623-625 in Fields 3, 4, 7 and 8. PAL-Noninterlaced: Scan Lines 1-6 and 311-312 are always blanked and vertical sync pulses are included. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1-5, 310-312.
After power-up, it is necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port such that the pixel inputs P7-P0 are not selected. After reset, the ADV7172/ ADV7173 is automatically set up to operate in NTSC/PAL mode, depending on the PAL_NTSC pin. The subcarrier frequency registers are automatically loaded with the correct values for PAL or NTSC. All other registers, with the exception of Mode Registers 1 and 2, are set to 00H. Mode Register 1 is set to 07H. This is to ensure DACs D, E and F are ON after power-up. All bits of Mode Register 2 are set to "0," with the exception of Bit 3 (i.e., Mode Register 2 reads 08H). Bit MR23 of Mode Register 2 is set to Logic "1." This enables the 7.5 IRE pedestal.
RESET SEQUENCE
When RESET becomes active, the ADV7172/ADV7173 reverts to the default output configuration. DACs A, B, C are off and DACs D, E, F are powered on and output composite, luma and chroma signals respectively. Mode Register 2, Bit 6 (MR26), resets to "0." The ADV7172/ADV7173 internal timing is under the control of the logic level on the NTSC_PAL pin. When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7172/ADV7173. Output timing signals are still suppressed at this stage. When the user requires valid data, MR26 is set to "1" to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the timing registers. If, at this stage, the user wishes to select a video standard different from that on the NTSC_PAL pin, Mode Register 2, Bit 5 (MR25) is set ("1") and the video standard required is selected by programming Mode Register 0. Figure 36 illustrates the reset sequence timing.
RESET
COMPOSITE/Y
XXXXXXX
0
BLACK VALUE WITH SYNC
VALID VIDEO
CHROMA
XXXXXXX
512
BLACK VALUE
VALID VIDEO
MR26 PIXEL DATA VALID
XXXXXXX
0
1
DIGITAL TIMING
XXXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
TIMING ACTIVE
Figure 36. RESET Sequence Timing Diagram
REV. A
-23-
ADV7172/ADV7173
EXAMPLE: NTSC 525 OUTPUT VIDEO CSO 1 2 3 4 5 6 7 8 9 10 11-19
HSO
VSO
Figure 37. CSO, HSO, VSO Timing Diagram
SLEEP MODE
If after reset the SCRESET/RTC and NTSC_PAL pins are both set to high, the part ADV7172/ADV7173 will power-up in sleep mode to facilitate low power consumption before all registers have been initialized. If Mode Register 6, Bit 0 (MR60) is then set to ("1") sleep mode control passes to Mode Register 2, Bit 7 (i.e., control via I2C).
SCH PHASE MODE
0H
MR57 = 1 MR57 = 0
The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7172/ADV7173 is configured in RTC mode (MR41 = "1" and MR42 = "1"). Under these conditions (unstable video) the subcarrier phase reset should be enabled (MR42 = "0" and MR41 = "1") but no reset applied. In this configuration the SCH phase will never be reset, which that the output video will now track the unstable input video. The subcarrier phase reset when applied will reset the SCH phase to Field 0 at the start of the next field (e.g., subcarrier phase reset applied in Field 5 (PAL) on the start of the next field SCH phase will be reset to Field 0).
CSO, HSO AND VSO OUTPUTS
Figure 38. Clamp Output Timing
MPU PORT DESCRIPTION
The ADV7172 and ADV7173 support a two wire serial (I2C Compatible) microprocessor bus driving multiple peripherals. Two inputs serial data (SDATA) and serial clock (SCLOCK) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7172 and ADV7173 each have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 39 and Figure 40. The LSB sets either a read or write operation. Logic Level "1" corresponds to a read operation while Logic Level "0" corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7172/ADV7173 to Logic Level "0" or Logic Level "1." When ALSB is set to "0," there is greater bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to "1," there is reduced input bandwidth on the I2C lines which means that impulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X
The ADV7172/ADV7173 supports three timing signals, CSO (composite sync signal), HSO (horizontal sync signal) and VSO (vertical sync signal). These output TTL signals are aligned with the analog video outputs. HSO and CSO are shared on Pin 10. Mode Register 7, Bit MR75 can be used to configure this output pin. See Figure 37 for an example of these waveforms.
CLAMP OUTPUT
The ADV7172/ADV7173 has a programmable clamp TTL output signal. The clamp signal is programmable to the front and back porch. Mode Register 5, Bit MR57 can be used to control the porch position. Also the position of the clamp signal can be varied by 1-3 clock cycles in a positive and negative direction from the default position. Mode Register 5, Bits MR56, MR55 and MR54 control this position.
Figure 39. ADV7172 Slave Address
-24-
REV. A
ADV7172/ADV7173
0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X
start condition. If an invalid subaddress is issued by the user, the ADV7172/ADV7173 will not issue an acknowledge and will return to the idle condition. If, in autoincrement mode, the user exceeds the highest subaddress the following action will be taken: 1. In Read Mode the highest subaddress register contents will continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7172/ADV7173 and the part will return to the idle condition. Figure 41 illustrates an example of data transfer for a read sequence and the Start and Stop conditions.
Figure 40. ADV7173 Slave Address
To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic "0" on the LSB of the first byte means that the master will write information to the peripheral. A Logic "1" on the LSB of the first byte means that the master will read information from the peripheral. The ADV7172/ADV7173 acts as a standard slave device on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allows data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto increment function should then be used to increment and access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier frequency registers should not be accessed independently. Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then these cause an immediate jump to the idle condition. During a given SCLOCK high period the user should only issue one start condition, one stop condition or a single stop condition followed by a single
WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT SUB ADDR SUB ADDR A(S) DATA
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9
1-7 DATA
8
9 ACK
P STOP
START ADDR R/W ACK SUBADDRESS ACK
Figure 41. Bus Data Transfer
Figure 42 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the ADV7172/ADV7173 except the Subaddress Register, which is a write-only register. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. A read/write operation is then performed from/to the target address, which then increments to the next address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, NTSC pedestal Control/PAL teletext control registers, CGMS/WSS registers, contrast register, U- or V-scale registers, hue adjust register, brightness control register and sharpness response register in terms of its configuration. All registers can be read from as well as written to.
A(S) LSB = 1
DATA
A(S) P
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 42. Write and Read Sequences
REV. A
-25-
ADV7172/ADV7173
Subaddress Register (SR7-SR0)
The communications register is an 8-bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place.
Figure 43 shows the various operations under the control of the subaddress register. "0" should always be written to SR7.
Register Select (SR6-SR0)
These bits are set up to point to the required starting address.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR7
ZERO SHOULD BE WRITTEN HERE
ADV7173 SUBADDRESS REGISTER ADV7172 SUBADDRESS REGISTER SR5 SR5 SR4 SR3 SR2 SR1 SR0
SR6 SR5 SR4 SR3 SR2 SR1 SR0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 MODE REGISTER 6 MODE REGISTER 7 RESERVED RESERVED TIMING MODE REGISTER 0 TIMING MODE REGISTER 1 SUBCARRIER FREQUENCY REGISTER 0 SUBCARRIER FREQUENCY REGISTER 1 SUBCARRIER FREQUENCY REGISTER 2 SUBCARRIER FREQUENCY REGISTER 3 SUBCARRIER PHASE REGISTER CLOSED CAPTIONING EXTENDED DATA-BYTE 0 CLOSED CAPTIONING EXTENDED DATA-BYTE 1 CLOSED CAPTIONING DATA-BYTE 0 CLOSED CAPTIONING DATA-BYTE 1 NTSC PEDESTAL CONTROL REG 0 NTSC PEDESTAL CONTROL REG 1 NTSC PEDESTAL CONTROL REG 2 NTSC PEDESTAL CONTROL REG 3 CGMS WSS 0 CGMS WSS 1 CGMS WSS 2 TELETEXT REQUEST POSITION CONTRAST REGISTER U-SCALE REGISTER V-SCALE REGISTER HUE ADJUST REGISTER BRIGHTNESS REGISTER SHARPNESS RESPONSE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 MODE REGISTER 6 MODE REGISTER 7 RESERVED RESERVED TIMING MODE REGISTER 0 TIMING MODE REGISTER 1 SUB CARRIER FREQUENCY REGISTER 0 SUB CARRIER FREQUENCY REGISTER 1 SUB CARRIER FREQUENCY REGISTER 2 SUB CARRIER FREQUENCY REGISTER 3 SUB CARRIER PHASE REGISTER CLOSED CAPTIONING EXT. DATA-BYTE 0 CLOSED CAPTIONING EXT. DATA-BYTE 1 CLOSED CAPTIONING DATA-BYTE 0 CLOSED CAPTIONING DATA-BYTE 1 NTSC PEDESTAL CONTROL REG 0 NTSC PEDESTAL CONTROL REG 1 NTSC PEDESTAL CONTROL REG 2 NTSC PEDESTAL CONTROL REG 3 CGMS WSS 0 CGMS WSS 1 CGMS WSS 2 TELETEXT REQUEST POSITION CONTRAST REGISTER U-SCALE REGISTER V-SCALE REGISTER HUE ADJUST REGISTER BRIGHTNESS REGISTER SHARPNESS RESPONSE RESERVED RESERVED MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS
Figure 43. Subaddress Register
-26-
REV. A
ADV7172/ADV7173
MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H) MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H)
Figure 44 shows the various operations under the control of Mode Register 0.
MR0 BIT DESCRIPTION Encode Mode Control (MR01-MR00)
Figure 45 shows the various operations under the control of Mode Register 1.
MR1 BIT DESCRIPTION DAC Control (MR15-MR10)
These bits are used to set up the encoder mode. The ADV7172/ ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or PAL N standard video.
Luminance Filter Control (MR02-MR04)
MR15-MR10 bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7172/ ADV7173 if any of the DACs are not required in the application.
Low Power Control (MR16)
These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is selected.
Chrominance Filter Control (MR05-MR07)
These bits select the chrominance filter. A low-pass filter can be selected with a choice of cutoff frequencies, (0.65 MHz, 1.0 MHz, 1.3 MHz or 2 MHz) along with a choice of CIF or QCIF filters.
This bit enables the lower power mode of the ADV7172/ ADV7173. This will reduce by approximately 50% the average supply current consumed by each large DAC which is powered on. For each DAC in low power mode, the relationship between RSET1/VREF and the output current is unchanged by this (see Appendix 8). This bit is only relevant to the larger DACs, DACs A, B and C. DACs D, E and F are not affected by this low power mode.
Reserved (MR17)
A Logic "0" must be written to this bit.
MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00
CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1.3 MHz LOW-PASS FILTER 0.65 MHz LOW-PASS FILTER 1.0 MHz LOW-PASS FILTER 2.0 MHz LOW-PASS FILTER RESERVED CIF QCIF RESERVED LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1
OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 0 0 1 1 0 1 1 NTSC PAL (B, D, G, H, I) PAL (M) PAL (N)
LOW-PASS FILTER (NTSC) LOW-PASS FILTER (PAL) NOTCH FILTER (NTSC) NOTCH FILTER (PAL) EXTENDED MODE CIF QCIF RESERVED
Figure 44. Mode Register 0 (MR0)
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
LOW POWER MODE CONTROL MR16 0 1 DISABLE ENABLE
DAC B DAC C CONTROL MR14 0 1 POWER-DOWN NORMAL
DAC D DAC C CONTROL MR12 0 1 POWER-DOWN NORMAL
DAC F DAC C CONTROL MR10 0 1 POWER-DOWN NORMAL
MR17 (0) ZERO SHOULD BE WRITTEN TO THIS BIT
DAC A DAC C CONTROL MR15 0 1 POWER-DOWN NORMAL
DAC C DAC C CONTROL MR13 0 1 POWER-DOWN NORMAL
DAC E DAC C CONTROL MR11 0 1 POWER-DOWN NORMAL
Figure 45. Mode Register 1 (MR1)
REV. A
-27-
ADV7172/ADV7173
MODE REGISTER 2 MR2 (MR27-MR20) (Address (SR4-SR0) = 02H) Square Pixel Mode Control (MR24)
Mode Register 2 is an 8-bit-wide register. Figure 46 shows the various operations under the control of Mode Register 2.
MR2 BIT DESCRIPTION RGB/YUV Control (MR20)
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Standard I2C Control (MR25)
This bit enables the output from the small or large DACs to be set to YUV or RGB output video standard.
Large DACs Control (MR21)
This bit controls the video standard used by the ADV7172/ ADV7173. When this bit is set to "1," the video standard bits programmed in Mode Register 0, Bits 0-1, indicate the video standard. When this bit is set to "0," the ADV7172/ADV7173 is forced into the standard selected by the NTSC_PAL pin.
Pixel Data Valid Control (MR26)
This bit controls the output from DACs A, B and C. When this bit is set to "1," composite, luma and chroma signals are output from DACs A, B and C (respectively). When this bit is set to "0," RGB or YUV may be output from these DACs.
DAC Switching Control (MR22)
This bit is used to switch the DAC outputs from SCART to a EuroSCART configuration. A complete table of all DAC output configurations is shown in Table III.
Pedestal Control (MR23)
After reset, this bit has the value "0" and the pixel data input to the encoder is blanked such that a black screen is output from the DACs. The ADV7172/ADV7173 will be set to master mode timing. When this bit is set to "1" by the user (via the I2C), pixel data passes to the pins and the encoder reverts to the timing mode defined by Timing Mode Register 0.
Sleep Mode Enable Bit (MR27)
This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7172/ ADV7173 is configured in PAL mode.
When this bit is set ("1"), sleep mode is enabled. With this mode enabled the ADV7172/ADV7173 power consumption is reduced to less than 20 A. The I2C registers can be written to and read from when the ADV7172/ADV7173 is in sleep mode. If "0" is written to MR27 when the device is in sleep mode, the ADV7172/ADV7173 will come out of sleep mode and resume normal operation. Also, if the reset signal is applied during sleep mode, the ADV7172/ADV7173 will come out of sleep mode and resume normal operation. This mode will only operate when MR60 is set to a Logic "1," otherwise sleep mode is controlled by the PAL_NTSC and SCRESET/RTC pin.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
PIXEL DATA VALID CONTROL MR26 0 1 DISABLE ENABLE
SQUARE PIXEL CONTROL MR24 0 1 DISABLE ENABLE
SCART ENABLE CONTROL MR22 0 1 DISABLE ENABLE
RGB/YUV CONTROL MR20 0 1 RGB OUTPUT YUV OUTPUT
SLEEP MODE CONTROL MR27 0 1 DISABLE ENABLE
STANDARD I2C CONTROL MR25 0 1 DISABLE ENABLE
PEDESTAL CONTROL MR23 0 1 PEDESTAL ON PEDESTAL OFF MR21 0 1
LARGE DACs CONTROL RGB/YUV/COMP COMP/LUMA/CHROMA
Figure 46. Mode Register 2 (MR2)
Table III. DAC Output Configuration Matrix
MR22 0 0 0 0 1 1 1 1
MR21 0 0 1 1 0 0 1 1
MR20 0 1 0 1 0 1 0 1
DAC A G Y CVBS CVBS CVBS CVBS CVBS CVBS
DAC B B U LUMA LUMA B U LUMA LUMA
DAC C R V CHROMA CHROMA R V CHROMA CHROMA
DAC D CVBS CVBS G Y G Y G Y
DAC E LUMA LUMA B U LUMA LUMA B U
DAC F CHROMA CHROMA R V CHROMA CHROMA R V
-28-
REV. A
ADV7172/ADV7173
MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H) Teletext Mode Control (MR34)
Mode Register 3 is an 8-bit-wide register. Figure 47 shows the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION Revision Code (MR31-MR30)
This bit enables switching of the teletext request signal from a continuous high signal (MR34 = "0") to a bit wise request signal (MR34 = "1").
Closed Captioning Field Control (MR36-MR35)
This bit is read-only and indicates the revision of the device.
VBI Pass-Through Control (MR32)
These bits control the fields that closed captioning data is displayed on. Closed captioning information can be displayed on an odd field, even field or both fields.
Active Video Filter Switching (MR37)
This bit determines whether or not data in the vertical blanking interval (VBI) is output to the analog outputs or blanked. Note that this condition is also valid in timing slave mode 0.
Teletext Enable (MR33)
This bit, controls the filter mode applied outside the active video portion of the line. This filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is selected.
This bit must be set to "1" to enable teletext data insertion on the TTX pin.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
ACTIVE VIDEO FILTER CONTROL MR37 0 1 ENABLE DISABLE
TTX BIT REQUEST MODE CONTROL MR34 0 1 DISABLE ENABLE
VBI OPEN MR32 0 1 DISABLE ENABLE
MR31 MR30 RESERVED FOR REVISION CODE
CLOSED CAPTIONING FIELD SELECTION MR36 0 0 1 1 MR35 0 1 0 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) 0 1
TELETEXT CONTROL MR33 DISABLE ENABLE
Figure 47. Mode Register 3 (MR3)
REV. A
-29-
ADV7172/ADV7173
MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H) Active Video Line Width Control (MR43)
Mode Register 4 is a 8-bit wide register. Figure 48 shows the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION VSYNC_3H Control (MR40)
This bit switches between two active video line durations. A "0" selects ITU-R BT.470 (720 pixels PAL/NTSC) and a "1" selects ITU-R/SMPTE "analog" standard for active video duration (710 pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
When this bit is enabled ("1") in slave mode, it is possible to drive the VSYNC active low input for 2.5 lines in PAL mode and 3 lines in NTSC mode. When this bit is enabled in master mode, the ADV7172/ADV7173 outputs an active low VSYNC signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Control (MR42-MR41)
This bit enables the color information to be switched on and off the video output.
Burst Control (MR45)
This bit enables the color burst information to be switched on and off the video output.
Color Bar Control (MR46)
These bits control the genlock feature of the ADV7172/ADV7173. Setting MR41 to Logic "0" disables the SCRESET/RTC pin and allows the ADV7172/ADV7173 to operate in normal mode. By setting MR41 to "1," one of two operations may be enabled: 1. If MR42 is set to "0," the SCRESET/RTC pin is configured as a subcarrier reset input and the subcarrier phase will reset to Field 0 whenever a high-to-low field transition is detected on the SCRESET/RTC pin. 2. If MR42 is set to "1," the SCRESET/RTC pin is configured as a real-time control input and the ADV7172/ADV7173 can be used to lock to an external video source.
This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7172/ADV7173 is configured in a master timing mode. The output pins VSYNC/FIELD, HSYNC and BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninterlaced mode.
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
COLOR BAR CONTROL MR46 0 1 DISABLE ENABLE 0 1
CHROMINANCE CONTROL MR44 ENABLE COLOR DISABLE COLOR
GENLOCK SELECTION MR42 MR41 x 0 1 0 1 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN ENABLE RTC PIN VSYNC 3H MR40 0 1 DISABLE ENABLE
INTERLACE CONTROL MR47 0 1 INTERLACED NONINTERLACED MR45 0 1
BURST CONTROL ENABLE BURST DISABLE BURST 0 1
CCIR 624/CCIR 601 CONTROL MR43 CCIR 624 OUTPUT CCIR 601 OUTPUT
Figure 48. Mode Register 4 (MR4)
-30-
REV. A
ADV7172/ADV7173
MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H) RGB Sync (MR53)
Mode Register 5 is an 8-bit-wide register. Figure 49 shows the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION Y-Level Control (MR50)
This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs.
Clamp Delay Value (MR55-MR54)
This bit controls the Y output level on the ADV7172/ADV7173. If this bit is set ("0"), the encoder outputs SMPTE levels when configured in PAL mode and Betacam levels when configured in NTSC mode. If this bit is set ("1"), the encoder outputs Betacam levels when configured in PAL mode and SMPTE levels when configured in NTSC mode.
UV-Levels Control (MR52-MR51)
These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7172/ADV7173. It is possible to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP signal. If this bit is set ("1"), the delay is negative. If it is not set ("0"), the delay is positive.
Clamp Position (MR57)
These bits control the U and V output levels on the ADV7172/ ADV7173. It is possible to have UV levels with a peak-peak amplitude of either 700 mV (MR52 + MR51 = "01") or 1000 mV (MR52 + MR51 = "10") in NTSC and PAL. It is also possible to have default values of 934 mV for NTSC and 700 mV for PAL (MR52 + MR51 = "00").
MR57 MR56 MR55 MR54
This bit controls the position of the CLAMP signal. If this bit is set ("1"), the CLAMP signal is located in the back porch position. If this bit is set to ("0"), the CLAMP signal is located in the front porch position.
MR53
MR52
MR51
MR50
CLAMP POSITION MR57 0 1 FRONT PORCH BACK PORCH
CLAMP DELAY MR55 MR54 0 0 1 1 0 1 0 1 NO DELAY 1 PCLK 2 PCLK 3 PCLK 0 0 1 1 RGB SYNC MR53 0 1 DISABLE ENABLE
UV LEVEL CONTROL MR52 MR51 0 1 0 1 DEFAULT LEVELS 700 mV 1000 mV RESERVED Y LEVEL CONTROL MR50 0 1 DISABLE ENABLE
CLAMP DELAY DIRECTION MR56 0 1 POSITIVE NEGATIVE
Figure 49. Mode Register 5 (MR5)
REV. A
-31-
ADV7172/ADV7173
MODE REGISTER 6 MR6 (MR67-MR60) (Address (SR4-SR0) = 06H) DAC Termination Control Bit (MR64)
Mode Register 6 is an 8-bit-wide register. Figure 50 shows the various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION Power Up Sleep Mode Control (MR60)
This bit controls the load termination resistance detected by the autodetect functionality. If this bit is set ("0"), the autodetect feature is used to determine if a 75 termination is present. If this bit is set to ("1"), the autodetect feature is used to indicate if a 150 termination is present.
Reserved (MR65)
After reset this bit is set to "0," if both SCRESET/RTC and NTSC_PAL pins are tied high, the part will power-up in sleep mode (to facilitate low power consumption before the I2C is initialized). When this bit is set to "1" (via the I2C), sleep mode control passes to Mode Register 2, Bit 7.
Reserved (MR61)
A Logic "0" must be written to this bit.
Luma DAC Status Bit (MR66)
A Logic "0" must be written to this bit.
Luma Autodetect Control (MR62)
This bit is a read-only status bit for the autodetect feature of the ADV7172/ADV7173 and may be read to check whether or not the composite DAC is terminated. If this bit is set ("1"), there is no termination; if this bit is set ("0"), the composite DAC is terminated.
Composite DAC Status Bit (MR67)
This bit controls which mode of autodetect operation is being used on the luma DAC (DAC B) on the ADV7172/ADV7173. If this bit is set ("0"), Mode 0 is on; if this bit is set ("1"), then Mode 1 is being used.
Composite Autodetect Control (MR63)
This bit is a read only status bit for the autodetect feature of the ADV7172/ADV7173 and may be read to check whether or not the luma DAC is terminated. If this bit is set ("1"), there is no termination. If this bit is set ("0"), the luma DAC is terminated.
This bit controls which mode of autodetect operation is being used on the composite DAC (DAC A) on the ADV7172/ ADV7173. If this bit is set ("0"), Mode 0 is on; if this bit is set ("1"), then Mode 1 is being used.
MR67
MR66
MR65
MR64
MR63
MR62
MR61
MR60
COMPOSITE AUTODETECT STATUS MR67 0 NOT TERMINATED 1 TERMINATED
MR65 (0) ZERO SHOULD BE WRITTEN TO THIS BIT
COMP AUTODETECT MODE CONTROL MR63 0 1 MODE 0 MODE 1
MR61 (0) ZERO SHOULD BE WRITTEN TO THIS BIT
LUMA AUTODETECT STATUS MR66 0 1 NOT TERMINATED TERMINATED
DAC TERMINATION MODE CONTROL MR64 0 1 1 2 MODE MODE
LUMA AUTODETECT MODE CONTROL MR62 0 1 MODE 0 MODE 1
POWER-UP SLEEP MODE CONTROL MR60 0 1 ENABLE DISABLE
Figure 50. Mode Register 6 (MR6)
-32-
REV. A
ADV7172/ADV7173
MODE REGISTER 7 MR7 (MR77-MR70) (Address (SR4-SR0) = 07H) Brightness Enable Bit (MR73)
Mode Register 7 is an 8-bit-wide register. Figure 51 shows the various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION Color Control Enable Bit (MR70)
This bit is used to enable brightness control on the ADV7172/ ADV7173 by enabling the programmable "setup level" or pedestal described in the Brightness Control Register to be added to the scaled Y data. When this bit is set ("1"), brightness control is enabled. When this bit is set ("0") brightness control is disabled.
Sharpness Response Enable Bit (MR74)
This bit is used to enable control of contrast and saturation of color. If this bit is set ("1"), color controls are enabled; if this bit is set ("0"), the color control features are disabled.
Luma Saturation Control (MR71)
When this bit is set ("1"), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 after scaling by the contrast control. This prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set ("0"), this control is disabled.
Hue Adjust Enable Bit (MR72)
This bit is used to enable the sharpness of the luminance signal on the ADV7172/ADV7173 (MR04-MR02 = 100). The various responses of the filter are determined by the Sharpness Response Register. When this bit is set ("1") the luma response is altered by the amount described in the Sharpness Response Register. When this bit is set ("0"), the sharpness control is disabled (see Figures 19, 20 and 21 for luma signal responses).
HSO-CSO Output Select (MR75)
This bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7172/ADV7173. When this bit is set ("1"), the hue of the color is adjusted by the phase offset described in the Hue Adjust Control Register. When this bit is set ("0") hue adjustment is disabled.
This bit is used to determine whether HSO or CSO TTL output signal is output at the CSO_HSO pin. If this bit is set ("1"), then the CSO TTL signal is output. If this bit is set ("0"), then the HSO TTL signal is output.
Reserved (MR77-MR76)
A Logic "0" must be written to these bits.
MR77
MR76
MR75
MR74
MR73
MR72
MR71
MR70
CSO/HSO OUTPUT CONTROL MR75 0 1 HSO OUT CSO OUT
BRIGHTNESS ENABLE CONTROL MR73 0 1 DISABLE ENABLE
LUMA SATURATION CONTROL MR71 0 1 DISABLE ENABLE COLOR CONTROL ENABLE MR70 DISABLE ENABLE 0 1 DISABLE ENABLE
ZERO SHOULD BE WRITTEN TO THESE BITS MR77 MR76 (0)
SHARPNESS RESPONSE ENABLE MR74 0 1 DISABLE ENABLE
HUE ADJUST ENABLE MR72 0 1
Figure 51. Mode Register 7 (MR7)
REV. A
-33-
ADV7172/ADV7173
TIMING REGISTER 0 (TR07-TR00) (Address (SR4-SR0) = 07H) Luma Delay Control (TR05-TR04)
Figure 52 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR0 BIT DESCRIPTION Master/Slave Control (TR00)
These bits control the addition of a delay to the luminance with respect to the chrominance. Each bit represents a delay of 74 ns.
Min Luminance Value (TR06)
This bit controls whether the ADV7172/ADV7173 is in master or slave mode.
Timing Mode Control (TR02-TR01)
The bit is used to control the minimum luma value output by the ADV7172/ADV7173. When this bit is set to ("1"), the luma is limited to 7.5 IRE below the blank level. When this bit is set to ("0"), the luma value can be as low as the sync bottom level.
Timing Register Reset (TR07)
These bits control the timing mode of the ADV7172/ADV7173. These modes are described in more detail in the Timing and Control section of the data sheet. This bit controls whether the BLANK input is used when the part is in slave mode or whether BLANK is internally generated.
BLANK Control (TR03)
Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset or changed to a new timing mode.
TR07 TIMING REGISTER RESET TR07
TR06
TR05
TR04
TR03 BLANK INPUT CONTROL TR03 0 ENABLE 1 DISABLE
TR02
TR01
TR00 MASTER/SLAVE CONTROL
TR00 0 SLAVE TIMING 1 MASTER TIMING TIMING MODE SELECTION
MIN LUMA CONTROL TR06 0 1 LUMA MIN = SYNC BOTTOM LUMA MIN = BLANK -7.5 IRE 0 0 1 1
LUMA DELAY TR05 TR04 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY 0 0 1 1
TR02 TR01 0 1 0 1 MODE 0 MODE 1 MODE 2 MODE 3
Figure 52. Timing Register 0
-34-
REV. A
ADV7172/ADV7173
TIMING REGISTER 1 (TR17-TR10) (Address (SR4-SR0) = 0BH) HSYNC to FIELD Delay Control (TR15-TR14)
Timing Register 1 is an 8-bit-wide register. Figure 53 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR1 BIT DESCRIPTION HSYNC Width (TR11-TR10)
When the ADV7172/ADV7173 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge.
VSYNC Width (TR15-TR14)
When the ADV7172/ADV7173 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth. This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes.
HSYNC to Pixel Data Adjust (TR17-TR16)
These bits adjust the HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay Control (TR13-TR12)
These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL DATA ADJUSTMENT TR17 TR16 0 0 1 1 0 1 0 1 0 1 2 3 TPCLK TPCLK TPCLK TPCLK
HSYNC TO FIELD RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 x x 0 1 TC TB TB + 32 s
HSYNC TO FIELD/VSYNC DELAY TR13 TR12 0 0 1 1 0 1 0 1 TB 0 TPCLK 4 TPCLK 8 TPCLK 16 TPCLK
HSYNC WIDTH TR11 TR10 0 0 1 1 0 1 0 1 TA 1 TPCLK 4 TPCLK 16 TPCLK 128 TPCLK
VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 0 1 0 1 1 TPCLK 4 TPCLK 16 TPCLK 128 TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1 HSYNC LINE 313 LINE 314
TA TB TC
FIELD/VSYNC
Figure 53. Timing Register 1
REV. A
-35-
ADV7172/ADV7173
SUBCARRIER FREQUENCY REGISTERS 3-0 (FSC3-FSC0) (Address (SR4-SR0) = 0CH-0FH) CLOSED CAPTIONING ODD FIELD DATA REGISTER 1-0 (CCD15-CCD00) (Subaddress (SR4-SR0) = 13-14H)
These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: 232 -1 Subcarrier Frequency Register = x fSCF fCLK Example: NTSC Mode, fCLK = 27 MHz, fSCF = 3.5795454 MHz 232 - 1 x 3.579454 x 106 Subcarrier FrequencyValue = 27 x 106 = 21F07C16 HEX Figure 54 shows how the frequency is set up by the four registers.
SUBCARRIER PHASE REGISTER (FP7-FP0) (Address (SR4-SR0) = 10H)
These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 56 shows how the high and low bytes are set up in the registers.
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
BYTE 0
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
Figure 56. Closed Captioning Data Register
NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3-0 (PCE15-0, PCO15-0)/(TXE15-0, TXO15-0) (Subaddress (SR4-SR0) = 15-18H)
This 8-bit-wide register is used to set up the subcarrier phase. Each bit represents 1.41. For normal operation this register is set to 00Hex.
SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
These 8-bit-wide registers are used to enable the NTSC pedestal/PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 57 and 58 show the four control registers. A Logic "1" in any of the bits of these registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic "1" in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17
FSC16
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
SUBCARRIER FREQUENCY FSC15 FSC14 FSC13 FSC12 REG 1 SUBCARRIER FREQUENCY REG 0 FSC7 FSC6 FSC5 FSC4
FSC11 FSC10
FSC9
FSC8 FIELD 1/3
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
FSC3
FSC2
FSC1
FSC0 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
Figure 54. Subcarrier Frequency Registers
CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1-0 (CED15-CED00) (Address (SR4-SR0) = 11-12H)
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Figure 57. Pedestal Control Registers
These 8-bit wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 55 shows how the high and low bytes are set up in the registers.
FIELD 1/3 BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8 FIELD 1/3 BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2
LINE 8 TXO1
LINE 7 TXO0
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
Figure 55. Closed Captioning Extended Data Register
FIELD 2/4
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2
LINE 8 TXE1
LINE 7 TXE0
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
Figure 58. Teletext Control Registers
-36-
REV. A
ADV7172/ADV7173
TELETEXT CONTROL REGISTER TC07 (TC07-TC00) (ADDRESS (SR4-SR0) = 1CH) C/W BIT DESCRIPTION CGMS Data Bits (C/W03-C/W00)
Teletext Control Register is an 8-bit-wide register. See Figure 59.
TTXREQ Rising Edge Control (TC07-TC04)
These four data bits are the final four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
These bits control the position of the rising edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles.
TTXREQ Falling Edge Control (TC03-TC00)
These bits control the position of the falling edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext Bits below the default of 360. If Bits TC03-TC00 are 00Hex when Bits TC07-TC04 are changed, then the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07-C/W00) (ADDRESS (SR4-SR0) = 19H)
When this bit is enabled ("1"), the last six bits of the CGMS data, i.e., the CRC check sequence, are calculated internally by the ADV7172/ADV7173. If this bit is disabled ("0"), the CRC values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set ("1"), CGMS is enabled for odd fields. Note that this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set ("1"), CGMS is enabled for even fields. Note that this is only valid in NTSC mode.
WSS Control (C/W07)
When this bit is set ("1"), wide screen signalling is enabled. Note that this is only valid in PAL mode.
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60 shows the operations under control of this register.
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TTXREQ RISING EDGE CONTROL TC07 TC06 0 0 " 1 1 0 0 " 1 1 TC05 TC04 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK
TTXREQ FALLING EDGE CONTROL TC03 TC02 0 0 " 1 1 0 0 " 1 1 TC01 TC00 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK
Figure 59. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
WIDE SCREEN SIGNAL CONTROL C/W07 0 1 DISABLE ENABLE
CGMS ODD FIELD CONTROL C/W05 0 1 DISABLE ENABLE
C/W03-C/W00 CGMS DATA BITS
CGMS EVEN FIELD CONTROL C/W06 0 1 DISABLE ENABLE
CGMS CRC CHECK CONTROL C/W04 0 1 DISABLE ENABLE
Figure 60. CGMS_WSS Register 0
REV. A
-37-
ADV7172/ADV7173
CGMS_WSS REGISTER 1 C/W1 (C/W17-C/W10) (Address (SR4-SR0) = 1AH) CONTRAST CONTROL REGISTER (CC07-CC00) (Address (SR4-SR0) = 1DH)
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 61 shows the operations under control of this register.
C/W1 BIT DESCRIPTION CGMS/WSS Data Bits (C/W15-C/W10)
The contrast control register is an 8-bit-wide register used to scale the Y output levels. Figure 63 shows the operation under control of this register.
CC0 BIT DESCRIPTION Reserved (CC07-CC06)
These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.
CGMS Data Bits (C/W17-C/W16)
A Logic "0" must be written to these bits.
Y Scalar Value (CC05-CC00)
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 C/W1(C/W27-C/W20) (Address (SR4-SR0) = 1BH)
These six bits represent the value required to scale the Y pixel data from 0.75 to 1.25 of its initial level. The value of these six bits is calculated using the following equation: Contrast Control Register = (X -0.785) x 128 where X = Scaling factor for Y e.g., Scale Y by 0.9 Contrast Control Register = (0.9-0.75) x 128 = 19.2 = 010011 (rounded to the nearest integer) Actual scaling factor = 0.898.
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 62 shows the operations under control of this register.
C/S BIT DESCRIPTION CGMS/WSS Data Bits (C/W27-C/W20)
These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17 C/W16 CGMS DATA ONLY
C/W15-C/W10 CGMS/WSS DATA
Figure 61. CGMS_WSS Register 1
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27-C/W20 CGMS/WSS DATA
Figure 62. CGMS_WSS Register 2
CC07
CC06
CC05
CC04
CC03
CC02
CC01
CC00
CC07 CC06 ZERO SHOULD BE WRITTEN TO THESE BITS
CC05-CC00 Y SCALAR VALUE
Figure 63. Contrast Control Register
-38-
REV. A
ADV7172/ADV7173
COLOR CONTROL REGISTERS 2-1 (CC2-CC1) (Address (SR4-SR0) = 1EH-1FH) V Scalar Value (CC25-CC20)
The color control registers are 8-bit-wide registers used to scale the U and V output levels. Figure 64 shows the operations under control of these registers.
CC1 BIT DESCRIPTION Reserved (CC17-CC16)
These six bits represent the value required to scale the V pixel data from 0.75 to 1.25 of its initial level. The value of these six bits is calculated using the following equation: Color Control Register 2 = (X - 0.75) x 128 where X = Scaling factor for V e.g., Scale V by 1.2 Color Control Register 2 = (1.2 - 0.75) x 128 = 57.6 = 111001 (rounded to the nearest integer)
HUE CONTROL REGISTERS (HCR) (Address (SR5-SR0) = 20H)
A Logic "0" must be written to these bits.
U Scalar Value (CC15-CC10)
These six bits represent the value required to scale the U level from 0.75 to 1.25 of its initial level. The value of these six bits is calculated using the following equation: Color Control Register 1 = (X - 0.75) x 128 where X = Scaling factor for U e.g., Scale U by 0.8 Color Control Register 1 = (0.8 - 0.75) x 128 = 6.4 = 000110 (rounded to the nearest integer)
CC2 BIT DESCRIPTION Reserved (CC27-CC26)
The hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 65 shows the operation under control of this register.
HCR BIT DESCRIPTION Hue Control Value (HCR7-HCR0)
A Logic "0" must be written to these bits.
These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier with respect to the phase of the subcarrier during the color burst. The ADV7172/ADV7173 provides a range of 22 in increments of 0.17578125. For normal operation (zero adjustment) this register is set to 80 Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust = (0.17568125 x [HCR7 - HCR0 - 128]).
CC17
CC16
CC15
CC14
CC13
CC12
CC11
CC10
CC17 CC16 ZERO SHOULD BE WRITTEN TO THESE BITS
CC15-CC10 U SCALAR VALUE
CC27
CC26
CC25
CC24
CC23
CC22
CC21
CC20
CC27 CC26 ZERO SHOULD BE WRITTEN TO THESE BITS
CC25-CC20 V SCALAR VALUE
Figure 64. Color Control Registers
HCR7
HCR6
HCR5
HCR4
HCR3
HCR2
HCR1
HCR0
HCR7-HCR0 HUE ADJUST VALUE
Figure 65. Hue Control Register
REV. A
-39-
ADV7172/ADV7173
BRIGHTNESS CONTROL REGISTERS (SCR) (Address (SR5-SR0) = 21H) SHARPNESS RESPONSE REGISTER (PR) (Address (SR5-SR0) = 22H)
The brightness control register is an 8-bit-wide register which allows brightness control. Figure 66 shows the operation under control of this register.
SCR BIT DESCRIPTION Reserved (SCR7-SCR5)
The sharpness response register is an 8-bit-wide register. The four MSBs are set to "0." The four LSBs are written to in order to select a desired filter response. Figure 67 shows the operation under control of this register.
PR BIT DESCRIPTION Reserved (PR7-PR4)
A Logic "0" must be written to these bits.
Brightness Control Value (SCR4-SCR0)
A Logic "0" must be written to these bits.
Sharpness Response Select Value (PR3-PR0)
These five bits represent the value required to vary the "brightness level" or pedestal added to the luma data. The available range is from 0 IRE to 7.5 IRE in 18 steps. A value of 18 (10010) corresponds to 7.5 IRE setup level added onto the pixel data. This brightness control is possible in both PAL and NTSC.
These four bits are used to select the desired luma filter response. The option of twelve responses is given supporting a gain boost/attenuation in the range -4 dB to +4 dB. The value 12 (1100) written to these four bits corresponds to a boost of +4 dB while the value 0 (0000) corresponds to -4 dB. For normal operation these four bits are set to 6 (0110).
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SCR7-SCR5 ZERO SHOULD BE WRITTEN TO THESE BITS
SCR4-SCR0 BRIGHTNESS VALUE
Figure 66. Brightness Control Register
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
PR7-PR4 ZERO SHOULD BE WRITTEN TO THESE BITS
PR3-PR0 SHARPNESS RESPONSE SELECT
Figure 67. Sharpness Response Register
-40-
REV. A
ADV7172/ADV7173
APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7172/ADV7173 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7172/ ADV7173 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized to minimize inductive ringing.
Ground Planes
Supply Decoupling
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VAA pins on the ADV7172/ADV7173 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close to the device as possible. It is important to note that while the ADV7172/ADV7173 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The ground plane should encompass all ADV7172/ADV7173 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7172/ADV7173, the analog output traces, and all the digital signal traces leading up to the ADV7172/ ADV7173. The ground plane is the board's common ground plane. This should be as substantial as possible to maximize heat spreading and power dissipation on the board.
Power Planes
The digital inputs to the ADV7172/ADV7173 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7172/ADV7173 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC) and not the analog power plane.
Analog Signal Interconnect
The ADV7172/ADV7173, and any associated analog circuitry, should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7172/ADV7173. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7172/ADV7173 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode.
The ADV7172/ADV7173 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 load resistor connected to GND. These resistors should be placed as close as possible to the ADV7172/ADV7173 to minimize reflections. The ADV7172/ADV7173 should have no inputs left floating. Any inputs that are not required should be tied to ground.
REV. A
-41-
ADV7172/ADV7173
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1 F +5V (VAA) +5V (VAA) +5V (VAA) 0.1 F 36 COMP1 23 COMP2 37 VREF 2 P0 9 P7 DAC B 33 1, 11, 19, 27, 30, 32, 34, 46 VAA DAC A 35 75 0.01 F +5V (VAA) 10 F L1 (FERRITE BEAD) +5V 0.1 F 0.1 F 33 F (VCC) GND
ADV7172/ ADV7173
DAC C 29
75
10 CSO_HSO 45 VSO 42 CLAMP 43 PAL_NTSC 39 SCRESET/RTC +5V (VAA) 4k RESET 4.7 F "UNUSED INPUTS SHOULD BE GROUNDED" 14 HSYNC 15 FIELD/VSYNC 16 BLANK 44 RESET +5V (VAA) 10k TTX TTXREQ 41 TTX 40 TTXREQ 48 CLOCK ALSB 17 +5V (VAA) 10k 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) GND
75
DAC D 28 300
DAC E 25 300
DAC F 24 300 100 100
+5V (VCC) 4k
+5V (VCC) 4k MPU BUS
SCLOCK 20 SDATA 21 RSET2 22 RSET1 38 150
600
12, 13, 18, 26, 31, 47
Figure 68. Recommended Analog Circuit Layout
-42-
REV. A
ADV7172/ADV7173
APPENDIX 2 CLOSED CAPTIONING
The ADV7172/ADV7173 supports closed captioning, conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level "1" start bit. 16 bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data Registers 0 and 1. The ADV7172/ADV7173 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1. All clock run-in signals, and timing to support closed captioning on Lines 21 and 284, are automatically generated by the ADV7172/ADV7173. All pixels inputs are ignored during Lines 21 and 284. Closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7172/ADV7173 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. The data must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new data is required for transmission, zeros must be inserted in both data registers; this is called NULLING. It is also important to load "control codes," all of which are double bytes, on Line 21, or a TV will not recognize them. If there is a message like "Hello World," which has an odd number of characters, it is important to pad it out to an even number to get "end of caption" 2-byte control code to land in the same field.
10.5
0.25 s
12.91 s 7 CYCLES OF 0.5035 MHz (CLOCK RUN-IN)
TWO 7-BIT + PARITY ASCII CHARACTERS (DATA)
50 IRE
S T A R T
D0-D6
P A R I T Y
D0-D6
P A R I T Y
BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s 33.764 s
BYTE 1
Figure 69. Closed Captioning Waveform (NTSC)
REV. A
-43-
ADV7172/ADV7173
APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7172/ADV7173 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7172/ADV7173 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 70). These bits are output from the configuration registers in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the Bit C/W04 is set to a Logic "1," the last six bits, C19-C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7172/ADV7173 based on the lower 14 bits (C0-C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic "0," all 20 bits (C0-C19) are directly output from the CGMS registers (no CRC calculated, must be calculated by the user).
Function of CGMS Bits
Word 0 Word 1 Word 2 CRC Word 0 B1 B2 B3
- 6 Bits - 4 Bits - 6 Bits - 6 Bits
CRC Polynomial = X6 + X + 1 (Preset to 111111) 1 16:9 Letterbox 0 4:3 Normal
Aspect Ratio Display Format Undefined
Word 0 B4, B5, B6 Word 1 B7, B8, B9, B10
Identification information about video and other signals (e.g., audio) Identification signal incidental to Word 0
Word 2 B11, B12, B13, B14 Identification signal and information incidental to Word 0
100 IRE REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CRC SEQUENCE
0 IRE 49.1 s -40 IRE 11.2 s 2.235 s 20ns 0.5 s
Figure 70. CGMS Waveform Diagram
-44-
REV. A
ADV7172/ADV7173
APPENDIX 4 WIDE SCREEN SIGNALING
The ADV7172/ADV7173 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7172/ADV7173 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 71). The bits are output from the configuration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13. If the Bit C/W07 is set to a Logic "1" it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s from the falling edge of HSYNC) is available for the insertion of video.
Function of CGMS Bits
Bit 0-Bit 2 B0 0 1 0 1 0 1 0 1 B4 0 1 B5 0 1 B6 0 1 B7 B1 0 0 1 1 0 0 1 1 B2 0 0 0 0 1 1 1 1 B3 1 0 0 1 0 1 1 0
Aspect Ratio/Format/Position Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format Nonapplicable Position Nonapplicable Center Top Center Top Center Center Nonapplicable B9 0 1 0 1 B11 0 1 B12 B13 B10 0 0 1 1
Bit 3 is odd parity check of Bit 0-Bit 2
Camera Mode Film Mode Standard Coding Motion Adaptive Color Plus No Helper Modulated Helper RESERVED
No Open Subtitles Subtitles In Active Image Area Subtitles Out of Active Image Area Reserved No Surround Sound Information Surround Sound Mode RESERVED RESERVED
500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN SEQUENCE START CODE ACTIVE VIDEO
11.0 s 38.4 s 42.5 s
Figure 71. WSS Waveform Diagram
REV. A
-45-
ADV7172/ADV7173
APPENDIX 5 TELETEXT INSERTION
Time, tPD, is the time needed by the ADV7172/ADV7173 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears tSYNTXTOUT = 10.2 s after the leading edge of the horizontal signal. Time, TXTDEL , is the pipeline delay time by the source that is gated by the TTREQ signal in order to deliver TTX data. With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays. The width of the TTXREQ signal must always be maintained such that it allows the insertion of 360 (in order to comply with the Teletext Standard "PAL-WST") teletext bits at a text data rate of 6.9375 Mbits/s. This is achieved by setting TC03-TC00 to "0." The insertion window is not open if the Teletex Enable bit (MR34) is set to "0."
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows: (27 MHz/4) = 6.75 MHz (6.9375 x 106/6.75 x 106) = 1.027777 Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7172/ADV7173 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be outputted on the CVBS and Y outputs. At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines is controlled by Teletext Setup Registers.
45 BYTES (360 BITS) - PAL ADDRESS & DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 72. Teletext VBI Line
tSYNTXTOUT
CVBS/Y
tPD
HSYNC 10.2 s TXTDATA TXTDEL TXTREQ PROGRAMMABLE PULSE EDGES TXTST
tPD
tSYNTXTOUT = 10.2 s tPD = PIPELINE DELAY THROUGH ADV7172/ADV7173
TXTDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0-15 CLOCK CYCLES])
Figure 73. Teletext Functionality Diagram
-46-
REV. A
ADV7172/ADV7173
APPENDIX 6 NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE PEAK COMPOSITE 1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure 74. NTSC Composite Video Levels
100 IRE
REF WHITE
1048.4mV
714.2mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure 75. NTSC Luma Video Levels
1067.7mV 835mV (pk-pk)
PEAK CHROMA
286mV (pk-pk) 650mV
BLANK/BLACK LEVEL
232.2mV
PEAK CHROMA
0mV
Figure 76. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV
Figure 77. NTSC RGB Video Levels
REV. A
-47-
ADV7172/ADV7173
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV 0 IRE -40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV
Figure 78. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE -40 IRE
BLANK/BLACK LEVEL SYNC LEVEL
338mV 52.1mV
Figure 79. NTSC Luma Video Levels
1101.6mV 903.2mV (pk-pk)
PEAK CHROMA
307mV (pk-pk) 650mV
BLANK/BLACK LEVEL
198.4mV
PEAK CHROMA
0mV
Figure 80. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
0 IRE -40 IRE
BLANK/BLACK LEVEL SYNC LEVEL
336.5mV 51mV
Figure 81. NTSC RGB Video Levels
-48-
REV. A
ADV7172/ADV7173
PAL WAVEFORMS
1284.2mV
PEAK COMPOSITE
1047.1mV
REF WHITE
696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL
Figure 82. PAL Composite Video Levels
1047mV
REF WHITE
696.4mV
350.7mV 50.8mV
BLANK/BLACK LEVEL SYNC LEVEL
Figure 83. PAL Luma Video Levels
1092.5mV 885mV (pk-pk)
PEAK CHROMA
300mV (pk-pk) 650mV
BLANK/BLACK LEVEL
207.5mV
PEAK CHROMA
0mV
Figure 84. PAL Chroma Video Levels
1050.2mV
REF WHITE
698.4mV
351.8mV 51mV
BLANK/BLACK LEVEL SYNC LEVEL
Figure 85. PAL RGB Video Levels
REV. A
-49-
ADV7172/ADV7173
UV WAVEFORMS
MAGENTA MAGENTA YELLOW YELLOW GREEN GREEN BLACK BLACK 0mV -82mV 171mV BLACK 0mV -76mV -158mV BLACK 0mV -57mV -118mV -232mV -293mV -350mV -350mV WHITE WHITE
CYAN
CYAN
BLUE
505mV 423mV 334mV
505mV
171mV BETACAM LEVEL 0mV 0mV
BETACAM LEVEL 82mV 0mV
334mV -423mV 505mV -505mV
Figure 86. NTSC 100% Color Bars, No Pedestal U Levels
Figure 89. NTSC 100% Color Bars, No Pedestal V Levels
MAGENTA
YELLOW
GREEN
BLACK
WHITE
MAGENTA
YELLOW
GREEN
WHITE
CYAN
CYAN
BLUE
RED
467mV 391mV 309mV
467mV
158mV BETACAM LEVEL 0mV 0mV
BETACAM LEVEL 76mV 0mV
-309mV -391mV -467mV -467mV
Figure 87. NTSC 100% Color Bars with Pedestal U Levels
Figure 90. NTSC 100% Color Bars with Pedestal V Levels
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
BLACK
GREEN
WHITE
WHITE
CYAN
BLUE
CYAN
350mV 293mV 232mV SMPTE LEVEL 118mV SMPTE LEVEL 57mV 0mV 0mV 0mV
350mV
Figure 88. PAL 100% Color Bars, U Levels
Figure 91. PAL 100% Color Bars, V Levels
-50-
BLUE
RED
RED
BLUE
RED
BLUE
RED
RED
REV. A
ADV7172/ADV7173
APPENDIX 7 OPTIONAL OUTPUT FILTER
DECIBELS
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7172/ADV7173, the filter shown below can be used. The plot of the filter characteristics is shown in Figure 93. An Output Filter is not required if the outputs of the ADV7172/ADV7173 are connected to most analog monitors or analog TVs; however, if the output signals are applied to a system where sampling is used (e.g., Digital TVs), then a filter is required to prevent aliasing.
22pF
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 VdB - OP
2.2 H FILTER I/P 270pF 330pF FILTER O/P
-55 -60 -65 -70 10k 100k 1M FREQUENCY - Hz 10M 100M
Figure 92. Output Filter Used with Output Buffer
Figure 93. Output Filter Plot
APPENDIX 8 OPTIONAL DAC BUFFERING
When external buffering is needed of the ADV7172/ADV7173 DAC outputs, the configuration in Figure 94 is recommended. This configuration shows the DAC outputs, A, B, C, running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7172/ADV7173 to dissipate less power; the analog current is reduced by 50% with a RSET1 = 300 and RSET2 = 600 and an RLOAD of 75 . This mode is recommended for 3.3 V operation as optimum performance is obtained from the
VAA
DAC outputs at 18 mA with a VAA of 3.3 V. This buffer also adds extra isolation on the video outputs (see buffer circuit in Figure 95). Note that DACs D, E and F will always require buffering as the full-scale output current from these DACs is limited to 8.66 mA. With DACs A, B and C, buffering is optional, based on the user requirements for performance and power consumption. When calculating absolute output full-scale current and voltage, use the following equations: V OUT = IOUT x RLOAD
ADV7172/ADV7173
VREF RSET1 300 DAC A OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER CVBS
IOUT =
(V
REF
xK
)
RSET
LUMA
DAC B
K = 4.2146 constant , VREF = 1.235 V
1k
DAC C PIXEL PORT DIGITAL CORE DAC D RSET2 600 DAC F
CHROMA
G 1k B
+VCC
DAC E
75
AD847
R INPUT 300 -VCC
OUTPUT TO OUTPUT FILTER/ TV MONITOR
Figure 94. Output DAC Buffering Configuration
Figure 95. Recommended Output DAC Buffer
REV. A
-51-
ADV7172/ADV7173
APPENDIX 9 RECOMMENDED REGISTER VALUES
The ADV7172/ADV7173 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite/luma/chroma outputs with DACs D, E and F powered up to provide 8.66 mA and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. In the examples shown, the timing mode is set to Mode 0 in slave format. TR02-TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the Register Programming section of the data sheet. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples this register is programmed in default mode.
NTSC (FSC = 3.5795454 MHz) Address Data
PAL B, D, G, H, I (F SC = 4.43361875 MHz) Address
Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
10Hex 07Hex 68Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
11Hex 07Hex 68Hex 00Hex 00Hex 00Hex 01Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
Data
PAL M (F SC = 3.57561149 MHz) Address
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0
12Hex 07Hex 68Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex A3Hex EFHex E6Hex 21Hex 00Hex 00Hex
-52-
REV. A
ADV7172/ADV7173
PAL M (Continued) (FSC = 3.57561149 MHz) Address 12Hex Closed Captioning Ext Register 1 13Hex Closed Captioning Register 0 14Hex Closed Captioning Register 1 15Hex Pedestal Control Register 0 16Hex Pedestal Control Register 1 17Hex Pedestal Control Register 2 18Hex Pedestal Control Register 3 19Hex CGMS_WSS Reg 0 1AHex CGMS_WSS Reg 1 1BHex CGMS_WSS Reg 2 1CHex TeleText Control Register 1DHex Contrast Control Register 1EHex Color Control Register 1 1FHex Color Control Register 2 20Hex Hue Control Register 21Hex Brightness Control Register 22Hex Sharpness Response Register
PAL N (FSC = 4.43361875 MHz) Address
Data 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
Data
1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register 2 Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
Data
PAL-60 (FSC = 4.43361875 MHz) Address
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0
13Hex 07Hex 68Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
12Hex 07Hex 68Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
REV. A
-53-
ADV7172/ADV7173
POWER ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address Data POWER ON RESET REG VALUES (PAL_NTSC = 1, PAL Selected) Address Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register
00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex
-54-
REV. A
ADV7172/ADV7173
APPENDIX 10 OPTIONAL DAC BUFFERING
0.6
0.4
VOLTS
0.2
0.0
0.2 L608
0.0
10.0
20.0
30.0 MICROSECONDS
40.0
50.0
60.0
NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF SYNCHRONOUS
SOUND-IN-SYNC OFF SYNC = SOURCE
FRAMES SELECTED: 1 2 3 4
Figure 96. 100%/75% PAL Color Bars
0.5
VOLTS
0.0
L575
0.0
10.0
20.0
APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS
60.0
70.0
SOUND-IN-SYNC OFF SYNC = A
FRAMES SELECTED: 1
Figure 97. 100%/75% PAL Color Bars Luminance
REV. A
-55-
ADV7172/ADV7173
0.5
VOLTS
0.0
-0.5 L575
10.0
20.0
30.0
40.0
50.0 NO BRUCH SIGNAL
60.0 SOUND-IN-SYNC OFF SYNC = A
MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF SYNCHRONOUS
FRAMES SELECTED: 1
Figure 98. 100%/75% PAL Color Bars Chrominance
100.0
0.5 IRE:FLT 0.0
0.0
VOLTS
50.0
-50.0
F1 L76
0.0 APL = 44.6% 525 LINE NTSC
10.0
20.0
30.0 40.0 MICROSECONDS PRECISION MODE OFF
50.0
60.0
NO FILTERING
SYNCHRONOUS
SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 99. 100%/75% NTSC Color Bars
-56-
REV. A
ADV7172/ADV7173
0.6
0.4 50.0 IRE:FLT 0.2 0.0 0.0 VOLTS -0.2 F2 L238
10.0
20.0
30.0 40.0 MICROSECONDS
50.0
60.0
NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
SYNCHRONOUS
SYNC = SOURCE
FRAMES SELECTED: 1 2
Figure 100. NTSC Color Bars Luminance
0.4 50.0
0.2 IRE:FLT -50.0 -0.4 F1 L76 VOLTS
0.0
-0.2
0.0
10.0
20.0
30.0 40.0 MICROSECONDS PRECISION MODE OFF
50.0
60.0
NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
SYNCHRONOUS
SYNC = B
FRAMES SELECTED: 1 2
Figure 101. 100%/75% NTSC Color Bars Chrominance
REV. A
-57-
ADV7172/ADV7173
V APL = 39.6% cy SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V & -V M g
g
R
75% 100% YI b U
yl
B
G Cy m g
r
SOUND IN SYNC OFF
Figure 102. PAL Vector Plot
R-Y APL = 45.1% I cy SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE
R M g Q
YI 100%
b B-Y
75% B
G Cy -Q
-I
SETUP 7.5%
Figure 103. NTSC Vector Plot
-58-
REV. A
ADV7172/ADV7173
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING PLANE TOP VIEW
(PINS DOWN)
0.354 (9.00) BSC 0.276 (7.0) BSC
48 1 37 36
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.006 (0.15) 0.002 (0.05) 0 - 7 0 MIN 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.019 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
REV. A
-59-
PRINTED IN U.S.A.
C3441a-1-6/99

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