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74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
October 1993 Revised March 1999
74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVX374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance
Ordering Code:
Order Number 74LVX374M 74LVX374SJ 74LVX374MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011612.prf
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74LVX374
Truth Table
Inputs Dn H L X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition
Outputs OE L L H On H L Z
CP

X
Functional Description
The LVX374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVX374
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Power Dissipation 75 mA -65C to +150C 180mW 25 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA -0.5V to 7V -0.5V to +7.0V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time (t/V) 2.0V to 3.6V 0V to 5.5V 0V to VCC -40C to +85C 0 ns/V to 100 ns/V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 3.6 3.6 0.1 4.0 1.0 40.0 VCC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.25 2.0 3.0 TA = +25C Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 2.5 A A A V VIN = VIH V Typ Max TA = -40C to +85C Min 1.5 2.0 2.4 0.5 0.8 0.8 VIN = VIH IOH = - 50A IOH = -4mA IOL = 50A IOL = 4mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND or VIL IOL = 50A or VIL IOH = -50A V V Max Units Conditions
Noise Characteristics (Note 3)
Symbol VOLP VOLV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 3.3 3.3 3.3 3.3 TA = 25C Typ 0.5 -0.5 Limit 0.8 -0.8 2.0 0.8 V V V V Units CL (pF) 50 50 50 50
Note 3: Input tr = tf = 3 ns
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74LVX374
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency 3.3 0.3 tPLH tPHL Propagation Delay Time CP to On 2.7 3.3 0.3 tPZL tPZH 3-STATE Output Enable Time 3.3 0.3 tPLZ tPHZ tW tS tH tOSLH tOSHL 3-STATE Output Disable Time CP Pulse Width Setup Time Dn to CP Hold Time Dn to CP Output to Output Skew (Note 4) 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 7.5 5.0 6.5 4.5 2.0 2.0 1.5 1.5 2.7 VCC (V) 2.7 TA = +25C Min 60 45 100 60 Typ 115 60 160 95 8.5 11.0 6.7 9.2 7.6 10.1 5.9 8.4 11.5 9.6 16.3 19.8 10.6 14.1 14.5 18.0 9.3 12.8 18.5 13.2 Max TA = -40C to +85C Min 50 40 85 55 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 8.0 5.5 6.5 4.5 2.0 2.0 1.5 1.5 19.5 23.0 12.5 16.0 17.5 21.0 11.0 14.5 22.0 15.0 ns ns ns ns ns CL = 50 pF ns ns MHz Max CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF, RL = 1 k CL = 50 pF, RL = 1 k CL = 15 pF, RL = 1 k CL = 50 pF, RL = 1 k CL = 50 pF, RL = 1 k CL = 50 pF, RL = 1 k Units Conditions
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
TA = +25C Min Typ 4 6 32 Max 10
TA = -40C to +85C Min Max 10
Units pF pF pF
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74LVX374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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