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74LVC544A Octal D-type registered transceiver, inverting (3-State)
Product specification 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * In accordance with JEDEC standard no. 8-1A * CMOS low power consumption * Direct interface with TTL levels * Combines 74LVC640 and 74LVC533 type functions in one chip * Octal transceiver with D-type latch * Back-to-back registers for storage * Separate controls for data flow in each direction * 3-State inverting outputs for bus oriented applications * 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC544A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of the data flow. The `544A' contains eight D-type latches with separate inputs and controls for each set. For data flow from A to B, for example, the A-to-B enable (EAB) input must be LOW in order to enter data from A0-A7 or take data from B0-B7, as indicated in the function table. With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and display the data present at the outputs of the A latches.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf v2.5 ns SYMBOL PARAMETER tPHL/tPLH CI CI/O CPD Propagation delay An to Bn Input capacitance Input/output capacitance Power dissipation capacitance per latch Notes 1, 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 4 5.0 10 30 UNIT ns pF pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 x fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC544A D 74LVC544A DB 74LVC544A PW NORTH AMERICA 74LVC544A D 74LVC544A DB 7LVC544APW DH PKG. DWG. # SOT137-1 SOT340-1 SOT355-1
1998 Jul 29
2
853-2107 19804
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
PIN DESCRIPTION
PIN NUMBER 1 2 3, 4, 5, 6, 7, 8, 9, 10 11 12 22, 21, 20, 19, 18, 17, 16, 15 13 14 23 24 SYMBOL LEBA OEBA A0-A7 EBA GND B0-B7 OEAB LEAB EAB VCC FUNCTION `B' to `A' latch enable input (active LOW) `B' to `A' output enable input (active LOW) `A' data inputs/outputs `B' to `A' enable input (active LOW) Ground (0V) `B' data inputs/outputs `A' to `B' output enable input (active LOW) `A' to `B' latch enable input (active LOW) `A' to `B' enable input (active LOW) Positive supply voltage
PIN CONFIGURATION
LEBA OEBA A0 A1 A2 A3 A4 A5 A6 1 2 3 4 5 6 7 8 9 24 VCC 23 EBA 22 B0 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 LEAB 13 OEAB
A7 10 EAB 11 GND 12
SV00733
FUNCTION TABLE
INPUTS OEXX H X L L L L L L L XX H L h l X NC Z EXX X H L L L L L LEXX X X L L L L H DATA X X h l h l H L X Z Z Z Z L H L H NC Disabled Disabled Disabled + Latch Latch + Display Transparent Hold OUTPUTS STATUS
= AB for A-to-B direction, BA for B-to-A direction = HIGH voltage level = LOW voltage level = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA = Don't care = LOW-to-HIGH level transition = No change = High impedance OFF-state
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
2 23
1EN3 G1 1C5 2EN4 G2 2C6 22
3
A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
1 13 11 14
3
3 6D
5D 4
10
A7
4 5 6
21 20 19 18 17 16 15
2 OEBA 13 OEAB 11 EAB 23 EBA 14 LEAB 1 LEBA 7 8 9 10
SV00734
SV00735
LOGIC DIAGRAM
OEBA EBA LEBA OEAB EAB LEAB
LE D
An LE D 8 IDENTICAL CHANNELS
Bn
TO 7 OTHER CHANNELS
SV00736
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC 5.5 +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 mW UNIT V mA V mA V V mA mA C
PTOT
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ IOFF ICC ICC Input leakage current 3-State output OFF-state current Power off leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3.6V; VI = 5.5V or GND VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI = 5.5V; VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "5 "10 10 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL PARAMETER Propagation delay An to Bn, Bn to An Propagation delay LEBA to An, LEAB to Bn 3-State output enable time OEBA to An, OEAB to Bn 3-State output disable time OEBA to An, OEAB to Bn 3-State output enable time EBA to An, EAB to Bn 3-State output disable time EBA to An, EAB to Bn LEXX pulse width HIGH Set-up time An/Bn to LEXX, An/Bn to EXX Hold time An/Bn to LEXX, An/Bn to EXX WAVEFORM MIN tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ tW tsu th Figures 1, 5 Figures 2, 5 Figures 3, 5 Figures 3, 5 Figures 3, 5 Figures 3, 5 Figure 2 Figure 4 Figure 4 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 4.0 VCC = 3.3V 0.3V TYP1 4 4.3 4.5 3.9 4.7 3.9 - - - MAX 6.5 7.5 8.5 6.5 8.9 6.9 - - - VCC = 2.7V MIN 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 1.0 MAX 7.5 8.5 9.5 7.5 9.9 7.9 - - - ns ns ns ns ns ns ns ns ns UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
1998 Jul 29
6
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
AC WAVEFORMS
An, Bn INPUT
GND
LEXX, EXX INPUT GND
VI An, Bn INPUT GND VOH Bn, An OUTPUT VOL tPHL tPLH VM
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 4. Data set-up and hold times for the (An, Bn) input to the LEXX and EXX inputs
VM
TEST CIRCUIT
SV00737
VCC S1 2 x VCC Open GND
Figure 1. Input (An, Bn) to output (Bn, An) propagation delays.
PULSE GENERATOR VM VM VM VI
VI LEXX INPUT
GND
tw tPHL VOH An, Bn OUTPUT VOL VM
tPLH VCC VM t 2.7V 2.7V - 3.6V VI VCC 2.7V
SV00738
Figure 2. Latch enable input (LEXX) pulse width, the latch enable input to output (An, Bn) propagation delays.
VI OEXX, EXX INPUT GND VM
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled VY
tPZL
VM
tPZH
VM
outputs enabled
SW00210
Figure 3. 3-State enable and disable times
1998 Jul 29
7
EEEEEEEEEE EEE E EEE E EEEEEEEEEE EEE EEEEEEEE EEE
VI VM th th tSU tSU VI VM
VM = 1.5V at VCC w 2.7V VM = 0.5V * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH - 0.3V at VCC w 2.7V VY = VOH - 0.1VCC at VCC < 2.7V
SV00739
VO D.U.T. RT CL 50pF
500
500
Test tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
SY00003
Figure 5. Load circuitry for switching times
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Jul 29
8
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1998 Jul 29
9
Philips Semiconductors
Product specification
Octal D-type registered transceiver, inverting (3-State)
74LVC544A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04512
Philips Semiconductors
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