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16 Megabit FlashBank Memory
SST38VF166
SST38VF16616Mb (x16) FlashBank + 64Kb E2
Data Sheet
FEATURES:
* * * Single 2.7-3.6V Read and Write Operations Separate Memory Banks for Code or Data - Simultaneous Read and Write Capability Superior Reliability - Endurance: E2 bank - 500,000 Cycles (typical) Flash bank - 100,000 Cycles (typical) - Greater than 100 years Data Retention Low Power Consumption - Active Current, Read: 15 mA (typical) - Active Current, Concurrent Read while Write: 40 mA (typical) - Standby Current: 3 A (typical) - Auto Low Power Mode Current: 3 A (typical) Fast Write Operation - Flash Bank-Erase + Program: 8 sec (typical) - Flash Block-Erase + Program: 500 ms (typical) - Flash Sector-Erase + Program: 30 ms (typical) - E2 bank Word-Write: 9 ms (typical) Fixed Erase, Program, Write Times - Remain constant after cycling * * * Read Access Time - 70 ns Latched Address and Data End-of-Write Detection - Toggle Bit - Data# Polling E2 Bank: - Word-Write (Auto Erase before Program) - Sector-Erase (32 Words) + Word-Program (same as Flash bank) Flash Bank: Two Small Erase Element Sizes - 1 KWords per Sector or 32 KWords per Block - Erase either element before Word-Program CMOS I/O Compatibility JEDEC Standard Command Set Packages Available - 48-Pin TSOP (12mm x 20mm) Continuous Hardware and Software Data Protection (SDP) A One Time Programmable (OTP) E2 Sector
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PRODUCT DESCRIPTION
The SST38VF166 consists of three memory banks, 2 each 512K x16 bits sector mode flash EEPROM plus a 4K x16 bits word alterable E2PROM manufactured with SST's proprietary, high performance SuperFlash Technology. The SST38VF166 erases and programs with a single power supply. The internal Erase/Program in the E2 bank is transparent to the user. The device conforms to (proposed) JEDEC standard pinouts for word-wide memories. The SST38VF166 device is divided into three separate memory banks, 2 each 512K x16 Flash banks and a 4K x16 E2 bank. Each Flash bank is typically used for program code storage and contains 512 sectors, each of 1 KWords or 16 blocks, each of 32 KWords. The Flash banks may also be used to store data. The E2 bank is typically used for data or configuration storage and contains 128 sectors, each of 32 words. Any bank may be used for executing code while writing data to a different bank. Each memory bank is controlled by separate Bank Enable (BE#) lines. The SST38VF166 inherently uses less energy during Erase, Program, and Write than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase, Program, or Write operation is less than alternative flash technologies. The Auto Low Power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approximately 1 mA/MHz of Read cycle time. The SuperFlash technology provides fixed Erase, Program, and Write times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
Device Operation
The SST38VF166 operates as two independent 8-Megabit Word-Program, Sector-Erase flash EEPROMs with the additional functionality of a 64 Kbit word-alterable E2PROM. All banks are superimposed in the same memory address space. All three memory banks share common address lines, I/O lines, WE#, and OE#. Memory bank selection is by bank enable. BE#1 selects the first
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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashBank is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
16 Megabit FlashBank Memory SST38VF166
Data Sheet Flash bank, BE#2 selects the second Flash bank, BE#3 selects the E2 bank. WE# is used with SDP to control the Write or Erase and Program operation in each memory bank. The SST38VF166 provides the added functionality of being able to simultaneously read from one memory bank while writing, erasing, or programming to one other memory bank. Once the internally controlled Write, Erase, or Program cycle in a memory bank has commenced, a different memory bank can be accessed for read. Also, once WE# and the applicable BE# are high during the SDP load sequence, a different bank may be accessed to read. If multiple bank enables are asserted simultaneously, the outputs will tri-state and no new memory operations can be initiated. Only one bank may be written, erased, or programmed at any given time. The device ID and Common Flash Interface (CFI) functions cannot be accessed while any bank is writing, erasing, or programming. The Auto Low Power Mode automatically puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15mA to typically 3A. The Auto Low Power mode reduces the typical IDD active read current to the range of 1mA/MHz of Read cycle time. The device exits the Auto Low Power Mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty.
Write Modes
The SST38VF166 device has separate Write modes for the E2 bank and Flash banks. The conventional E2PROM Word-Write with internally timed automatic Erase before Program is the most convenient and easy method for the user to alter data in the E2 bank with the Word-Write operation, the word being written is the only word that is altered. Bank- or Sector-Erase plus Word-Program operations may also be used for the E2 bank. For both banks of the Flash array, the SST38VF166 offers Bank-, Block-, and SectorErase plus Word-Program operations.
Write
All Write operations are initiated by first issuing the Software Data Protect (SDP) entry sequence for Bank-, Block-, or Sector-Erase then Word-Program in the selected Flash bank; or for Word-Write or for Sector-Erase and Word-Program in the E2 bank. Word-Write, Word-Program, and all Erase commands have a fixed duration, that will not vary over the life of the device, i.e., are independent of the number of Erase/Program cycles endured. Either Flash bank may be read during the internally controlled E2 bank Write cycle, e.g., the Flash bank may be accessed to fetch instructions or data when the E2 bank is being written, erased, or programmed. Additionally, the alternate Flash bank may be read while erasing or programming the other Flash or E2 bank. At any given time, only one bank may be performing a Write operation, during that time any other bank is available for read. The Write Status command may be used to determine if any bank is being written, at any given time. This may be required if the system does not use a timer or does not monitor toggle bit or data# polling when writing a specific bank. In order to implement the Write Status command, address 5XXXH in the E2 bank address space is reserved. This address is outside the normal address space of the E2 bank; therefore, will not interfere with normal reading within the E2 bank address space. The device is always in the Software Data Protected mode for all Write operations in both the Flash bank and E2 bank. Write operations are controlled by toggling WE# or BE#. The falling edge of WE# or BE#, whichever occurs last, latches the address. The rising edge of WE# or BE#, whichever occurs last, latches the data and initiates the Erase, Program, or Write cycle. The SDP Erase, Program, or Write commands are all BE# specific. Whichever BE# is used for the first SDP bus cycle (except for Read operation with WE# high), that BE# must be used for all subsequent SDP bus cycles, for the command to be executed. If a different BE# is pulsed during a
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Flash Bank Read
The Read operation of the SST38VF166 Flash Bank is controlled by BE#1 or BE#2 and OE#, a bank enable and output enable both have to be low for the system to obtain data from the outputs. BE#1 is used for Flash bank 1 selection. When BE#1 is high, the Flash bank 1 is deselected. BE#2 is used for Flash bank 2 selection. When BE#2 is high, the Flash bank 2 is deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the timing waveforms for further details (Figure 2 or 3).
E2 Bank Read
The Read operation of the E2 bank is controlled by BE#3 and OE#, both have to be low for the system to obtain data from the outputs. BE#3 is used for E2 bank selection. When BE#3 is high, the E2 bank is deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the timing waveforms for further details (Figure 4).
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16 Megabit FlashBank Memory SST38VF166
Data Sheet subsequent bus cycle, when WE# is low, in the SDP command sequence, the device will abort the attempted SDP command and revert to the Read mode. Note, the SDP command sequence may be suspended by taking WE# high. A different BE# may then be pulsed to read from either of the banks not involved with the SDP command sequence. For the purposes of simplification, the following descriptions will assume WE# is toggled to initiate an Erase, Program, or Write. Toggling the applicable BE# will accomplish the same function. Note, there are separate timing diagrams to illustrate both WE# and BE# controlled Program or Write commands. The Write operation has two functional cycles: the Word Load cycle and the internal Write cycle. The Word Load cycle consists of loading 1 word of data into the word buffer at the completion of the SDP sequence. The internal Write cycle consists of the write timer operation, to erase and program the selected address. Note, the word does NOT have to be erased prior to writing. During the Write operation, the only valid reads are Data# Polling and Toggle Bit from the E2 bank or normal read from either of the Flash banks.
E2 Bank Word-Program
The E2 bank Word-Program operation consists of issuing the SDP Word-Program command, initiated by forcing BE#3 and WE# low and OE# high. The Word-Program command programs the desired addresses word-by-word. The words to be programmed must be in the erased state, prior to programming, unlike the Word-Write operation. During the Word-Program cycle, the addresses are latched by the falling edge of WE#. The data is latched by the rising edge of WE#. See Figure 11 for WE# or 12 for BE#3 controlled Program cycle timing waveforms, Table 7 for the command sequence and Figure 50 for a flowchart. During the E2 bank Erase or Program operation, the only valid reads from the bank are Data# Polling and Toggle Bit. Either Flash bank may be read. The specified Bank- or Sector-Erase time is the only time required to erase. There are no preprogramming or other commands or cycles required either internally or externally to erase the bank or sector.
Flash Bank Word-Program
The Flash bank Word-Program operation consists of issuing the SDP Word-Program command, initiated by forcing BE#1 or BE#2 and WE# low, and OE# high. The words to be programmed must be in the erased state, prior to programming. The Word-Program command programs the desired addresses word-by-word. During the Word-Program cycle, the addresses are latched by the falling edge of WE#. The data is latched by the rising edge of WE#. See Figure 5 or 7 for WE# or 6 and 8 for BE# controlled WordProgram cycle timing waveforms, Table 6 for the command sequence, and Figure 49 for a flowchart. During the Flash bank Erase or Program operation, the only valid reads from that bank are Data# Polling and Toggle Bit. The other Flash bank or the E2 bank may be read. The specified Bank-, Block-, or Sector-Erase time is the only time required to erase. There are no preprogramming or other commands or cycles required either internally or externally to erase the bank, block, or sector.
Erase Operations
The Bank-Erase is initiated by a specific six-word load sequence See Tables 6 and 7. A Bank-Erase will typically be less than 70 ms. An alternative to the Bank-Erase in the Flash bank is the Block-Erase or Sector-Erase. The Block-Erase will erase an entire Block (32 KWords) in typically 15 ms. The SectorErase will erase an entire sector (1024 words) in typically 15 ms. The Sector-Erase provides a means to alter a single sector using the Sector-Erase and Word-Program modes. The Sector-Erase is initiated by a specific six-word load sequence, see Table 6. The E2 bank may also use a Sector-Erase, instead of Bank-Erase. An E2 bank sector consists of 32 words that will typically erase in 7 ms. The Sector-Erase is initiated by a specific six-word load sequence, see Table 7. Sector- or Bank-Erase and Word-Program is an alternative to WordWrite as a means to alter the E2 bank.
E2 Bank Word-Write
The E2 bank Word-Write operation consists of issuing the SDP command, initiated by forcing BE#3 and WE# low, and OE# high; followed by the Word Load cycle to the SST38VF166. The internally controlled Write cycle stores the data loaded in the word buffer into the E2 bank. The address selected is then erased and programmed, by internally controlled signals. During the Word Load cycle, the address is latched by the falling edge of WE#. The data is latched by the rising edge of WE#. The internal write cycle is initiated on the rising edge of WE#. The Write cycle, once initiated, will continue to completion, typically within 7 ms. See Figure 9 for WE# or 10 for BE# controlled write cycle timing waveforms, Table 7 for the command sequence, and Figure 48 for a flowchart.
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Data Sheet During any Sector-, Block-, or Bank-Erase within a bank, any other bank may be read. During the Word-Write of the E2 bank, either Flash bank may be read. The E2 Bank-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protection operation. After the loading cycle, the device enters into an internally timed cycle. See Table 7 for specific codes, Figure 19 for the timing waveform, and Figure 44 for a flowchart.
Flash Bank Bank-Erase
The SST38VF166 provides a Flash Bank-Erase mode, which allows the user to clear the Flash bank to the "1" state. This is useful when the entire Flash must be quickly erased. The software Flash Bank-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protection operation. After the loading cycle, the device enters into an internally timed cycle. See Table 6 for specific codes, Figure 13 or 16 for the timing waveform, and Figure 44 for a flowchart.
E2 Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which allows the user to clear any sector in the E2 bank to the "1" state. The software Sector-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed. See Tables 6 and 7 for specific codes, Figure 20 for the timing waveform, and Figure 46 for a flowchart. During the Erase operation, the only valid reads are Data# Polling and Toggle Bit in the E2 bank or normal read from either of the Flash banks.
Flash Bank Block-Erase
The SST38VF166 provides a Block-Erase mode, which allows the user to clear any block in the Flash bank to the "1" state. The software Block-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle. See Table 6 for specific codes, Figure 14 or 17 for the timing waveform, and Figure 45 for a flowchart. During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read.
Write Operation Status Detection
The SST38VF166 provides two software means to detect the completion of a E2 bank or a Flash bank Program cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write Detection mode is enabled after the rising edge of WE#, which initiates the internal Write, Erase, or Program cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious device rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Additionally, a Write Status read may be executed to determine if any bank has an Erase, Program, or Write operation in progress. A Write Status read may be used when, for any reason, the system may have lost track of the status of a Write, Erase, or Program operation in any bank. Although normally, a Word-Write, Word-Program, SectorErase, or Block-Erase will be completed prior to recovery from a system reset, if a Bank-Erase was initiated prior to the reset, the system may need to verify the Bank-Erase is no longer in progress. Note, a Bank-Erase will not be performed on the bank containing the boot code, so there will
Flash Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which allows the user to clear any sector in the Flash bank to the "1" state. The software Sector-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle. See Table 6 for specific codes, Figure 15 or 18 for the timing waveform, and Figure 47 for a flowchart. During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read.
E2 Bank Bank-Erase
The SST38VF166 provides a E2 Bank-Erase mode, which allows the user to clear the E2 bank to the "1" state. This is useful when the entire E2 bank must be quickly erased. The E2 bank Bank-Erase command is disabled if the E2 bank OTP option is enabled.
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Data Sheet be no issue when recovering from the system reset. See Table 6 or 7 for the specific codes and Figure 40 for a timing waveform. There is no provision to abort an Erase, Program, or Write operation, once initiated. For the SST SuperFlash technology, the associated Erase, Program, and Write times are so fast, relative to system reset times, there is no value in aborting the operation. Note, reads can always occur from any bank not performing an Erase, Program, or Write operation. Should the system reset, while a Block- or Sector-Erase or Word-Program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading that bank. Since the maximum time the system would have to wait is 25 ms (for a Block-Erase), the system ability to read the boot code would not be affected.
Toggle Bit (DQ6) - E2 Bank
During the E2 bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 26 for E2 bank Toggle Bit timing waveforms and Figure 51 for a flowchart.
Data Protection
The SST38VF166 provides both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5 volts. Write Inhibit Mode: Forcing OE# low, BE#1 and BE#2 high, or WE# high will inhibit the Write operation to the Flash bank. Forcing OE# low, BE#3 high, or WE# high will inhibit the Write operation to the E2 bank. This prevents inadvertent writes during power-up or power-down.
Data# Polling (DQ7) - Flash Bank
When the SST38VF166 is in the internal Flash bank Program cycle, any attempt to read DQ7 of the last word loaded during the Flash bank Word Load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 21 or 22 for the Flash bank Data Polling timing waveforms and Figure 51 for a flowchart.
A One Time Programmable E2 Sector
The first sector of the E2 bank offers the option of OTP (One Time Programmable) prevention of write for the first sector, i.e., addresses A5 to A13 are "0" (0000H to 001FH). Once the OTP software instruction is executed, no Write, Erase, or Program operation can be performed on these 32 words. This is permanent and non-reversible. Additionally, if the OTP prevention is enabled, the Bank-Erase for the E2 bank will not function. See Table 7 for specific codes and Figure 39 for a timing waveform.
Data# Polling (DQ7) - E2 Bank
When the SST38VF166 is in the internal E2 bank Write cycle, any attempt to read DQ7 of the last word loaded during the E2 bank Word Load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 23 for E2 bank Data Polling timing waveforms and Figure 51 for a flowchart.
Software Data Protection (SDP)
The SST38VF166 provides the JEDEC approved Software Data Protection scheme as a requirement for initiating a Write, Erase, or Program operation. With this scheme, any Write operation requires the inclusion of a series of three word-load operations to precede the Word-Write or WordProgram operation. The three-word load sequence is used to initiate the Write or Program cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The six-word sequence is required to initiate any Bank-, Block-, or Sector-Erase operation.
Toggle Bit (DQ6) - Flash Bank
During the Flash bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 24 or 25 for Flash bank Toggle Bit timing waveforms and Figure 51 for a flowchart.
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Data Sheet The requirements for JEDEC compliant SDP are in byte format. The SST38VF166 is organized by word; therefore, the contents of DQ8 to DQ15 are "Don't Care" during any SDP (3-word or 6-word) command sequence. During the SDP load command sequence, the SDP load cycle is suspended when WE# is high. This means a read may occur to any other bank during the SDP load sequence. The SDP load sequence is bank specific, i.e., the same BE# must be low for each bus cycle. If the command sequence is aborted, e.g., a different BE# is brought low (except for Read operation with WE# high), an incorrect address is loaded, or incorrect data is loaded, the device will return to the Read mode within TRC of execution of the load error.
Product Identification
The product identification mode identifies the device manufacturer as SST and provides a code to identify each bank. The manufacturer ID is the same for each bank; however, each bank has a separate device ID. Each bank is individually accessed using the applicable BE# and a software command. Users may wish to use the device ID operation to identify the write algorithm requirements for each bank. For details, see Table 6 or 7 for software operation and Figures 27, 28, or 29 for timing waveforms. TABLE 2: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID Flash Bank 1 Flash Bank 2 E2 Bank 0001H 0001H 0001H 2791H 2792H 2793H
T2.1 327
Data 00BFH
0000H
Concurrent Read and Write Operations
The SST38VF166 provides the unique benefit of being able to read any bank, while simultaneously writing, erasing, or programming one other bank. This allows data alteration code to be executed from one bank, while altering the data in another bank. The following table lists all valid states. TABLE 1: CONCURRENT READ/WRITE STATE
Flash Bank 2 No Operation Write Read Read No Operation Write E2 Bank Write No Operation No Operation Write Read Read
T1.0 327
Device IDs are unique to each bank. Should a chip ID be required, any of the bank IDs may be used as the chip ID. While in the read software ID mode or CFI mode, no other operation is allowed until after exiting these modes.
Flash Bank 1 Read Read Write No Operation Write No Operation
Product Identification Mode Exit
In order to return to the standard Read mode, the Product Identification mode must be exited. Exit is accomplished by issuing the Software ID exit command, which returns the device to normal operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. For details, see Table 6 or 7 for software operation and Figures 30, 31, or 32 for timing waveforms.
Note: For the purposes of this table, write means to Word-Write; Block-, Sector-, or Chip-Erase; or Word-Program as applicable to the appropriate bank.
SST does not recommend that any two of the bank enable signals BE#1, BE#2 or BE#3 be simultaneously asserted. The device will ignore all SDP commands and toggling of WE# when an Erase, Program, or Write operation is in progress. Note, both Product Identification and the Common Flash Interface entry commands use SDP; therefore, these commands will also be ignored while an Erase, Program, or Write operation is in progress.
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Data Sheet
Common Flash Interface (CFI)
The SST38VF166 also contains the CFI information in each bank, to describe the characteristics of that bank. See Tables 8 through 16 for the CFI contents for each bank. Both flash banks use the same information, as each bank operates the same. The E2 bank contains the applicable information for that bank. In order to obtain the CFI information, the CFI memory space is accessed by using the CFI entry command. For details, see Table 6 or 7 for software operation and Figures 33, 34, or 35 for timing waveforms.
CFI Mode Exit
In order to return to the standard Read mode, the CFI mode must be exited. Exit is accomplished by issuing the CFI exit command, which returns the device to normal operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. For details, see Table 6 or 7 for software operation and Figures 36, 37, or 38 for timing waveforms. CFI is specified for byte wide information. Since the SST38VF166 is organized word wide, the first byte (2 nibbles) of each CFI word is always 00H.
FUNCTIONAL BLOCK DIAGRAM
Charge Pump & Vref.
Y - Decoder
4K x 16 E2 Bank
Address Buffer and Latches
X - Decoder 512K x 16 Flash Bank 1
512K x 16 Flash Bank 2
A18 - A0
OE# BE#1 BE#2 BE#3 WE#
Control Logic
I/O Buffers and Data Latches
DQ15 - DQ0
327 ILL F02.1
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Data Sheet
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# NC BE#2 NC BE#3 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard Pinout Top View Die Up
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS BE#1 A0
327 ILL F01b.5
FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP (12MM X 20MM) TABLE
Symbol A18-A0 A11-A0 A18-A15 A18-A10 A11-A5
3: PIN DESCRIPTION
Name Flash Bank Addresses E2 Bank Addresses Flash Bank Block Addresses E2 Bank Sector Addresses Functions To provide Flash Bank addresses To provide E2 Bank addresses To select a Flash Bank Block for erase To select an E2 Bank Sector for erase To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high or BE#1, BE#2, and BE#3 are high. To gate the data output buffers To control the Write, Erase, or Program operations To provide 2.7-3.6V power supply Unconnected pins
T3.4 327
Flash Bank Sector Addresses To select a Flash Bank Sector for erase
DQ15-DQ 0 Data Input/output
OE# WE# VDD VSS NC
Output Enable Write Enable 1 Power Supply Ground No Connect
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Data Sheet TABLE
Read Flash Bank 1 Flash Bank 2 Block-Erase Flash Bank 1 Flash Bank 2 Sector-Erase Flash Bank 1 Flash Bank 2 Program Flash Bank 1 Flash Bank 2 Standby Write Inhibit Flash Bank 1 Flash Bank 2 Flash Bank-Erase Flash Bank 1 Flash Bank 2 Status Operation Mode Write Status Read Illegal State Illegal State Illegal State Illegal State Product Identification Flash Bank 1 Flash Bank 2 Common Flash Interface Flash Bank 1 Flash Bank 2 VIL VIH VIH VIL VIH VIH VIL VIL VIH VIH DOUT DOUT See Tables 6 and 7 See Tables 6 and 7
T4.5 327
4: OPERATION MODES SELECTION FOR FLASH BANK
BE#1 VIL VIH VIL VIH VIL VIH VIL VIH VIH VIH X VIL VIH BE#1 VIH VIL VIL VIL X VIL VIH BE#2 VIH VIL VIH VIL VIH VIL VIH VIL VIH X VIH VIH VIL BE#2 VIH VIL VIL X VIL VIH VIL BE#3 VIH VIH VIH VIH VIH VIH VIH VIH VIH X X VIH VIH BE#3 VIL VIL X VIL VIL VIH VIH OE# VIL VIL VIH VIH VIH VIH VIH VIH X VIL VIL VIH VIH OE# VIL X X X X VIL VIL WE# VIH VIH VIL VIL VIL VIL VIL VIL X VIH VIH VIL VIL WE# VIH X X X X VIH VIH DQ DOUT DOUT DIN DIN DIN DIN DIN DIN High Z X X DIN DIN DQ DOUT1 High Z High Z High Z High Z DOUT DOUT Address AIN AIN See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 X X X See Tables 6 and 7 See Tables 6 and 7 Address 5XXXXH X2 X2 X2 X2 See Tables 6 and 7 See Tables 6 and 7
Array Operation Mode
1. If Flash Bank 1 is writing, DQ1 is low. If Flash Bank 2 is writing, DQ2 is low. If E2 Bank is writing, DQ3 is low. 2. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write will continue to normal completion.
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16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 5: OPERATION MODES SELECTION FOR E2 BANK
BE#1 VIH VIH VIH VIH VIH E2 E2 Bank Bank X VIH VIH BE#1 VIH VIL VIL VIL X VIH VIH BE#2 VIH VIH VIH VIH VIH X VIH VIH BE#2 VIH VIL VIL X VIL VIH VIH BE#3 VIL VIL VIL VIL VIH VIH VIL VIL BE#3 VIL VIL X VIL VIL VIL VIL OE# VIL VIH VIH VIH X VIL VIH VIH OE# VIL X X X X VIL VIL WE# VIH VIL VIL VIL X VIH VIL VIL WE# VIH X X X X VIH VIH DQ DOUT1 DIN DIN DIN DIN High Z DIN DIN DQ DOUT2 High Z High Z High Z High Z DOUT DOUT See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 See Tables 6 and 7 X See Tables 6 and 7 See Tables 6 and 7 Address 5XXXXH X3 X3 X3 X3 See Tables 6 and 7 See Tables 6 and 7
T5.6 327
Read Operation Mode Read E2 Bank Write E2 Bank Sector-Erase E2 Bank Program Standby Write Inhibit OTP Enable Erase E2 Bank Status Operation Mode Write Status Read Illegal State Illegal State Illegal State Illegal State Product Identification E2 Bank Common Flash Interface E2 Bank E2 Bank
Address
1. A11-A0 are valid addresses; A15-A12 are "Don't Care"; A 18-A16 cannot be 5H 2. If Flash Bank 1 is writing, DQ1 is low. If Flash Bank 2 is writing, DQ2 is low. If E2 Bank is writing, DQ3 is low. 3. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write will continue to normal completion.
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
10
16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 6: SOFTWARE COMMAND SEQUENCE FOR FLASH BANKS
1st Bus Cycle Command Code Software ID Entry Software ID Exit Flash Bank Word-Program Flash Bank Sector-Erase Flash Bank Block-Erase Flash Bank Bank-Erase CFI Entry CFI Exit Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 AAH AAH AAH AAH AAH AAH AAH AAH 2nd Bus Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 55H 55H 55H 3rd Bus Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 90H F0H A0H 80H 80H 80H 98H F0H 4th Bus Cycle Addr1
3 4
5th Bus Cycle Addr1 Data2
6th Bus Cycle Addr1 Data2
Data2
WA 5 5555H 5555H 5555H
7 4
Data In AAH AAH AAH 2AAAH 2AAAH 2AAAH 55H 55H 55H SA6 BA6 5555H 30H 50H 10H
T6.4 327
1. Command Code Address format A14-A0 (Hex), Addresses > A 14 are "Don't Care" for Command sequences 2. Data format DQ7 -DQ0 (Hex), DQ15 - DQ8 are "Don't Care" 3. With A14-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A0 = 1 for the applicable BE# active 4. The device does not remain in Software Product ID Mode or CFI Mode if powered down. 5. WA = Word address 6. SA = Sector address BA = Block address 7. There is a separate CFI for each bank. See Tables 8 through 16
TABLE
7: SOFTWARE COMMAND SEQUENCE FOR E2 BANKS
1st Bus Cycle 2nd Bus Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 55H 55H 55H 55H 3rd Bus Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 90H F0H A0H A5H 80H 80H 80H 98H F0H 4th Bus Cycle Addr1
3 4
5th Bus Cycle Addr1 Data2
6th Bus Cycle Addr1 Data2
Command Code Software ID Entry Software ID Exit Bank Word-Write E2 Bank Word-Program E2 Bank Sector-Erase E2 Bank Bank-Erase E2 Bank OTP Enable CFI Entry CFI Exit E2
Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H
Data2 AAH AAH AAH AAH AAH AAH AAH AAH AAH
Data2
WA 5 WA 5 5555H 5555H 5555H
7 4
Data In Data In AAH AAH AAH 2AAAH 2AAAH 2AAAH 55H 55H 55H SA6 5555H 5555H 30H 10H 70H
T7.4 327
1. Command Code Address format A14-A0 (Hex), Addresses > A 14 are "Don't Care" for Command sequences 2. Data format DQ7 -DQ0 (Hex), DQ15 - DQ8 are "Don't Care" 3. With A14-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A0 = 1 for the applicable BE# active 4. The device does not remain in Software Product ID Mode or CFI Mode if powered down. 5. WA = Word address 6. SA = Sector address 7. There is a separate CFI for each bank. See Tables 8 through 16
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
11
16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 8: CFI QUERY IDENTIFICATION STRING FOR FLASH BANK 1
Data 0051H 0052H 0059H 0001H 0008H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH
Primary OEM command set (JEP-137) Address for Primary Extended Table (00H = none exists) Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T8.2 327
TABLE
1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H
9: SYSTEM INTERFACE INFORMATION FOR FLASH BANK 1
Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no V PP pin) VPP max. (00H = no VPP pin) Typical time out for Word-Program 2N s Typical time out for min. size Page-Write 2N s (00H = not supported) Typical time out for individual Sector-Erase 2N ms Typical time out for Bank-Erase 2N ms Maximum time out for Word-Program 2N times typical Maximum time out for Page-Write 2N times typical (00H = not supported) Maximum time out for individual Sector-Erase 2N times typical Maximum time out for Chip-Erase 2N times typical
T9.7 327
Address
TABLE 10: DEVICE GEOMETRY INFORMATION FOR FLASH BANK 1
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0014H 0001H 0000H 0000H 0000H 0002H 00FFH 0001H 0008H 0000H 000FH 0000H 0000H 0001H Data Bank size = 2N Byte (14H > 220 = 1 MByte = 8 Mbits) Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous) Maximum number of bytes in Page-Write = 2N (00H = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (Sector) (Refer to the CFI specification or JESD-68) y = 511 + 1 = 512 sectors (01FFH = 511) z = 2 KBytes/sector = 8 x 256 Bytes Erase Block Region 2 Information (Block) (Refer to the CFI specification or JESD-68) y = 15 + 1 = 16 blocks z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T10.5 327
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 11: CFI QUERY IDENTIFICATION STRING FOR FLASH BANK 2
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0008H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary OEM command set (JEP-137) Address for Primary Extended Table (00H = none exists) Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T11.2 327
TABLE 12: SYSTEM INTERFACE INFORMATION FOR FLASH BANK 2
Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no V PP pin) VPP max. (00H = no VPP pin) Typical time out for Word-Program 2N s Typical time out for min. size Page-Write 2N s (00H = not supported) Typical time out for individual Sector-Erase 2N ms Typical time out for Bank-Erase 2N ms Maximum time out for Word-Program 2N times typical Maximum time out for Page-Write 2N times typical (00H = not supported) Maximum time out for individual Sector-Erase 2N times typical Maximum time out for Chip-Erase 2N times typical
T12.8 327
TABLE 13: DEVICE GEOMETRY INFORMATION FOR FLASH BANK 2
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0014H 0001H 0000H 0000H 0000H 0002H 00FFH 0001H 0008H 0000H 000FH 0000H 0000H 0001H Data Bank size = 2N Byte (14H > 220 = 1 MByte = 8 Mbits) Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous) Maximum number of bytes in Page-Write = 2N (00H = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (Sector) (Refer to the CFI specification or JESD-68) y = 511 + 1 = 512 sectors (01FFH = 511) z = 2 KBytes/sector = 8 x 256 Bytes Erase Block Region 2 Information (Block) (Refer to the CFI specification or JESD-68) y = 15 + 1 = 16 blocks z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T13.5 327
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
13
16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 14: CFI QUERY IDENTIFICATION STRING FOR E2 BANK
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0009H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary OEM command set (JEP-137) Address for Primary Extended Table (00H = none exists) Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T14.1 327
TABLE 15: SYSTEM INTERFACE INFORMATION FOR E2 BANK
Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0005H 0000H 0003H 0006H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no V PP pin) VPP max. (00H = no VPP pin) Typical time out for Word-Program 2N s Typical time out for min. size Page-Write 2N s (00H = not supported) Typical time out for individual Sector-Erase 2N ms Typical time out for Bank-Erase 2N ms Maximum time out for Word-Program 2N times typical Maximum time out for Page-Write 2N times typical (00H = not supported) Maximum time out for individual Sector-Erase 2N times typical Maximum time out for Chip-Erase 2N times typical
T15.7 327
TABLE 16: DEVICE GEOMETRY INFORMATION FOR E2 BANK
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H Data 000DH 0001H 0000H 0001H 0000H 0001H 007FH 0000H 0001H 0000H Data Device size = 2N Byte (DH > 213 = 8 KBytes = 64 Kbits) Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous) Maximum number of bytes in Page-Write = 2N (00H = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (Sector) (Refer to the CFI specification or JESD-68) y = 127 + 1 = 128 sectors (007FH = 127) z = 32 Bytes/sector = 1 x 256 Bytes
T16.4 327
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE:
Range Commercial Ambient Temp 0C to +70C VDD 2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 42 and 43
TABLE 17: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits Symbol IDD Parameter Power Supply Current Read Write: Flash Bank 35 40 mA mA Min Max Units Test Conditions Address input = VIL/VIH, at f=1/TRC Min VDD=VDD Max BE#1,BE#2, or BE#3=VIL, WE#=VIH, all I/Os open BE#1/2=WE#=VIL, OE#=VIH VDD=VDD Max or E2 Bank BE#3=WE#=VIL, OE#=VIH VDD=VDD Max Address input = VIL/VIH, at f=1/TRC Min WE#=VIH, VDD=VDD Max BE#1,BE#2, or BE#3=VIL, OE#=WE#=VIH, BE#1,BE#2, or BE#3=VIHC, VDD = VDD Max BE#1,BE#2, or BE#3=VILC, WE#= VIHC, all I/Os open, Address input = VIHC/VIHC and static VDD=V DD Max VIN =GND to VDD, VDD = VDD Max VOUT =GND to VDD, VDD = VDD Max VDD = VDD Min VDD = VDD Max VDD = VDD Max IOL = 100 A, V DD = VDD Min IOH = -100 A, VDD = VDD Min
T17.1 327
Read: Flash Bank plus Write/Program/Erase: E2 Bank or Flash Bank ISB IALP Standby VDD Current (CMOS inputs) Auto Low Power Mode (CMOS inputs) Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.2
75
mA
50 50
A A
ILI ILO VIL VILC VIH VIHC VOL VOH
1 1 0.3VDD 0.2
A A V V V V
0.2
V V
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
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16 Megabit FlashBank Memory SST38VF166
Data Sheet TABLE 18: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE1 Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s
T18.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 19: CAPACITANCE (Ta = 25C, f=1 Mhz, other pins open)
Parameter CI/O1 CIN1 Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 12 pF 6 pF
T19.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 20: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Parameter Endurance - Flash Bank Endurance - E2 Bank Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up Minimum Specification 10,000 100,000 100 2000 200 100 + IDD Units Cycles/Sector Cycles/Word Years Volts Volts mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
T20.0 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
AC CHARACTERISTICS
TABLE 21: READ CYCLE TIMING PARAMETERS
SST38VF166-70 Symbol TRC TBE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 20 20 Min 70 70 70 30 Max Units ns ns ns ns ns ns ns ns ns
T21.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 22: WRITE, ERASE, PROGRAM CYCLE TIMING PARAMETERS
Symbol TWC TBPE TBPF TSEF TLEF TBEF TSEE TBEE TAS TAH TBES TBEH TOES TOEH TWP TWPH TDS TDH TVDDR1 TDBR TTBR TIDA TBS Parameter Word-Write Cycle (Erase and Program) Word-Program Time E2 Bank Word-Program Time - Flash Bank Sector-Erase Time - Flash Bank Block-Erase Time - Flash Bank Bank-Erase Time - Flash Bank Sector-Erase Time - E2 Bank Bank-Erase Time - E2 Bank Address Setup Time Address Hold Time BE# Setup Time BE# Hold Time OE# High Setup Time OE# High Hold Time Write Pulse Low Width Write Pulse High Time Data Setup Time Data Hold Time VDD Rise Time Time to DATA# Polling Read Time to Toggle Bit Read Time to ID or CFI Read/Exit Cycle Bank Enable Setup Time for Concurrent Operation 0 0 40 0 0 0 0 40 30 40 0 0.1 35 35 150 50 Min Max 12.5 40 20 25 25 100 12.5 100 Units ms s s ms ms ms ms ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns
T22.0 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
TIMING DIAGRAMS
Address and data format are in hexadecimal
TRC ADDRESS A18-0
TAA
BE#1
TBE
OE# VIH BE#2, BE#3, WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
327 ILL F03a.2
FIGURE 2: FLASH BANK 1, READ CYCLE TIMING DIAGRAM
TRC ADDRESS A18-0
TAA
BE#2
TBE
OE# VIH BE#1 , BE#3, WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
327 ILL F03b.2
FIGURE 3: FLASH BANK 2, READ CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
TRC ADDRESS A11-0
TAA
BE#3
TBE
OE# VIH BE#1 , BE#2, WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
327 ILL F03c.2
FIGURE 4: E 2 BANK, READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBPF ADDRESS A18-0 5555 TAH TWP WE# TAS BE#2, BE#3, OE# TWPH TDS 2AAA 5555 ADDR TDH
BE#1 TBES DQ150 AA SW0 55 SW1 A0 SW2
TBEH
DATA WORD (ADDR/DATA)
327 ILL F04a1.3
FIGURE 5: FLASH BANK 1, WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBPF ADDRESS A18-0 5555 TAH TWP BE#1 TAS BE#2, BE#3, OE# TWPH TDS 2AAA 5555 ADDR TDH
WE#1 TWES DQ150 AA SW0 55 SW1 A0 SW2
TWEH
DATA WORD (ADDR/DATA)
327 ILL F04a2.3
FIGURE 6: FLASH BANK 1, BE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBPF ADDRESS A18-0 5555 TAH TWP WE# TAS BE#1, BE#3, OE# TBEH BE#2 TBES DQ15-0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
327 ILL F04b1.3
FIGURE 7: FLASH BANK 2, WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBPF ADDRESS A18-0 5555 TAH TWP BE#2 TAS BE#1, BE#3, OE# TWEH WE# TWES DQ15-0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
327 ILL F04b2.3
FIGURE 8: FLASH BANK 2, BE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TWC ADDRESS A14-0 5555 TAH TWP WE# TAS BE#1, BE#2, OE# TBEH BE#3 TBES DQ15-0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
327 ILL F04c1.3
FIGURE 9: E 2 BANK, WE# CONTROLLED WORD-WRITE CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TWC ADDRESS A14-0 5555 TAH TWP BE#3 TAS BE#1, BE#2, OE# TWEH WE# TWES DQ15-0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
327 ILL F04c2.3
FIGURE 10: E 2 BANK, BE# CONTROLLED WORD-WRITE CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBPE ADDRESS A14-0 5555 TAH TWP WE# TAS BE#1, BE#2, OE# TBEH BE#3 TBES DQ15-0 AA SW0 55 SW1 A5 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
327 ILL F04d1.3
FIGURE 11: E 2 BANK, WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBPE ADDRESS A14-0 5555 TAH TWP BE#3 TAS BE#1, BE#2, OE# TWEH WE# TWES DQ15-0 AA SW0 55 SW1 A5 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
326 ILL F04d 2.3
FIGURE 12: E 2 BANK, BE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
SIX-BYTE CODE FOR BANK-ERASE ADDRESS A18-0 5555 TAH TAS 2AAA 5555 5555 2AAA 5555
TBEF
BE#1
BE#2, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
327 ILL F05a1.2
FIGURE 13: FLASH BANK 1, BANK-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A18-0 5555 TAH TAS 2AAA 5555 5555 2AAA BAX
TLEF
BE#1
BE#2, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
50 SW5
327 ILL F05a2.3
FIGURE 14: FLASH BANK 1, BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A18-0 5555 TAH TAS 2AAA 5555 5555 2AAA SAX
TSEF
BE#1
BE#2, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
327 ILL F05a3.3
FIGURE 15: FLASH BANK 1, SECTOR-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
SIX-BYTE CODE FOR BANK-ERASE ADDRESS A18-0 5555 TAH TAS 2AAA 5555 5555 2AAA 5555
TBEF
BE#2
BE#1, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
327 ILL F05b1.2
FIGURE 16: FLASH BANK 2, BANK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A18-0 5555 TAH TAS 2AAA 5555 5555 2AAA BAX
TLEF
BE#2
BE#1, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
50 SW5
327 ILL F05b2.4
FIGURE 17: FLASH BANK 2, BLOCK-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A18-0 5555 TAH TAS BE#2 2AAA 5555 5555 2AAA SAX
TS EF
BE#1, BE#3, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
327 ILL F05b3.3
FIGURE 18: FLASH BANK 2, SECTOR-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR BANK-ERASE ADDRESS A14-0 5555 TAH TAS BE#3 2AAA 5555 5555 2AAA 5555
TBEE
BE#1, BE#2, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
327 ILL F05c1.2
FIGURE 19: E 2 BANK, BANK-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A14-0 5555 TAH TAS BE#3 2AAA 5555 5555 2AAA SAX
TSEE
BE#1, BE#2, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
327 ILL F05c2.3
FIGURE 20: E 2 BANK, SECTOR-ERASE TIMING DIAGRAM
ADDRESS A18-0
BE#2, BE#3 TBE BE#1 TOEH OE# TOE WE# TOES
DQ7
Data
Data#
Data#
Data
326 ILL F06a.3
FIGURE 21: FLASH BANK 1, DATA# POLLING TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
ADDRESS A18-0
BE#1, BE#3 TBE BE#2 TOEH OE# TOE WE# TOES
DQ7
Data
Data#
Data#
Data
327 ILL F06b.3
FIGURE 22: FLASH BANK 2, DATA# POLLING TIMING DIAGRAM
ADDRESS A14-0
BE#1, BE#2 TBE BE#3 TOEH OE# TOE WE# TOES
DQ7
Data
Data#
Data#
Data
327 ILL F06c.3
FIGURE 23: E 2 BANK, DATA# POLLING TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
ADDRESS A18-0
BE#2, BE#3 TBE BE#1 TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS 327 ILL F07a.3
FIGURE 24: FLASH BANK 1, TOGGLE BIT TIMING DIAGRAM
ADDRESS A18-0
BE#1, BE#3 TBE BE#2 TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS 327 ILL F07b.3
FIGURE 25: FLASH BANK 2, TOGGLE BIT TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
ADDRESS A14 -0
BE#1, BE#2 TBE BE#3 TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS 326 ILL F07c.3
FIGURE 26: E 2 BANK, TOGGLE BIT TIMING DIAGRAM
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BE#1
BE#2, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 90 SW2 TAA 00BF 2791
327 ILL F08a.5
TIDA
FIGURE 27: FLASH BANK 1, SOFTWARE ID ENTRY AND READ
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BE#2
BE#1, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 90 SW2 TAA 00BF 2792
327 ILL F08b.5
TIDA
FIGURE 28: FLASH BANK 2, SOFTWARE ID ENTRY AND READ
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BE#3
BE#2, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 90 SW2 TAA 00BF 2793
327 ILL F08c.5
TIDA
FIGURE 29: E 2 BANK, SOFTWARE ID ENTRY AND READ
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for Software ID Exit ADDRESS A14-0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#2, BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F09a.3
FIGURE 30: FLASH BANK 1, SOFTWARE ID EXIT
Three-Byte Sequence for Software ID Exit ADDRESS A14-0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#1 , BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F09b.4
FIGURE 31: FLASH BANK 2, SOFTWARE ID EXIT
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for Software ID Exit ADDRESS A14 -0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#1 , BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F09c.4
FIGURE 32: E 2 BANK, SOFTWARE ID EXIT
Three-Byte Sequence for CFI Entry ADDRESS A14-0 5555 2AAA 5555 0010 0011
BE#1
BE#2, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 98 SW2
327 ILL F10a.2
TIDA
TAA 0051 0052
FIGURE 33: FLASH BANK 1, CFI ENTRY AND READ
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for CFI Entry ADDRESS A14-0 5555 2AAA 5555 0010 0011
BE#2
BE#1, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 98 SW2
327 ILL F10b.3
TIDA
TAA 0051 0052
FIGURE 34: FLASH BANK 2, CFI ENTRY AND READ
Three-Byte Sequence for CFI Entry ADDRESS A14-0 5555 2AAA 5555 0010 0011
BE#3
BE#2, BE#3
OE# TWP WE# TWPH DQ15-0 AA SW0 55 SW1 98 SW2
327 ILL F10c.3
TIDA
TAA 0051 0052
FIGURE 35: E 2 BANK, CFI ENTRY AND READ
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for CFI Exit ADDRESS A14-0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#2, BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F11a.2
FIGURE 36: FLASH BANK 1, CFI EXIT
Three-Byte Sequence for CFI Exit ADDRESS A14-0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#1 , BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F11b.3
FIGURE 37: FLASH BANK 2, CFI EXIT
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Three-Byte Sequence for CFI Exit ADDRESS A14 -0 5555 2AAA 5555
DQ15-0
AA
55
F0 TIDA
BE#1
BE#1 , BE#3, OE# TWP WE# T WPH SW0 SW1 SW2
327 ILL F11c.3
FIGURE 38: E 2 BANK, CFI EXIT
SIX-BYTE CODE FOR OTP ENABLE ADDRESS A14 -0 5555 TAH TAS 2AAA 5555 5555 2AAA 5555
TBPE
BE#3
BE#1, BE#2, OE# TWP WE# TWPH TDS TDH
DQ15-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
70 SW5
327 ILL F12.2
FIGURE 39: E 2 BANK, OTP ENABLE
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
TRC ADDRESS A18-0 5XXXX TAA BE#3 TBE
OE# VIH BE#1, BE#2, WE# TOLZ
TOE
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
327 ILL F13.3
FIGURE 40: WRITE OPERATION STATUS READ
ADDRESS A18-0
BE#i TBS BE#i
WE#
OE#
DQ15-0
327 ILL F25.1
Note: i = 1, 2, 3
FIGURE 41: TIMING DIAGRAM TO ALTERNATE BETWEEN EACH MEMORY BANK
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
327 ILL F14.3
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <10 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 42: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
327 ILL F15.3
FIGURE 43: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Memory Bank Bank-Erase Start
Software Data Protect Bank-Erase Command Wait for End-of-Erase (TBEE, TBEF, Data # Polling, or Toggle Bit)
Bank-Erase Complete
327 ILL F16.3
FIGURE 44: BANK-ERASE FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Flash Bank Block-Erase Start
Software Data Protect Block-Erase Flash Bank Command
Set Block Address
Wait for End-of-Erase (TLEF, Data # Polling, or Toggle Bit)
Flash Bank Block-Erase Complete
327 ILL F17.5
FIGURE 45: FLASH BANK BLOCK-ERASE FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
E2 Bank Sector-Erase Start
Software Data Protect Sector-Erase Flash Bank Command
Set Sector Address
Wait for End-of-Erase (TSEE, Data # Polling, or Toggle Bit)
E2 Bank Sector-Erase Complete
327 ILL F18.5
FIGURE 46: E 2 BANK SECTOR-ERASE FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Flash Bank Sector-Erase Start
Software Data Protect Sector-Erase Flash Bank Command
Set Sector Address
Wait for End-of-Erase (TSEF, Data # Polling, or Toggle Bit)
Flash Bank Sector-Erase Complete
327 ILL F19.5
FIGURE 47: FLASH BANK SECTOR-ERASE FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
E2 Bank Word-Write Start
Software Data Protect Write E2 Bank Command
Set Word Address
Load Word Data
Wait for End-of-Write (TWC, Polling, or Toggle Bit)
E2 Bank Word-Write Complete
327 ILL F20.4
FIGURE 48: E 2 BANK WORD-WRITE FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Flash Bank Word-Program Start
Software Data Protect Program Flash Bank Command
Set Word Address
Load Word Data
Wait for End of Program (TBPF, Data # Polling, or Toggle Bit)
Flash Bank Word-Program Complete
327 ILL F21.3
FIGURE 49: FLASH BANK WORD-PROGRAM FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
E2 Bank Word-Program Start
Software Data Protect Program E2 Bank Command
Set Word Address
Load Word Data
Wait for End of Program (TBPE, Data # Polling, or Toggle Bit)
E2 Bank Word-Program Complete
327 ILL F22.3
FIGURE 50: E 2 BANK WORD-PROGRAM FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Internal Timer
Erase, Program, or Write Operation Initiated
Toggle Bit
Erase, Program, or Write Operation Initiated
Data# Polling
Erase, Program, or Write Operation Initiated
Read DQ7 of the last address set (or any address within selected bank, block, sector for erase)
Wait TWC, TBPE, TBPF, TSEF, TLEF, TBEF, TSEE or TBEE
Read a word from a bank, block, sector, or word selected
Erase, Program, or Write Completed
Read the same word again
No Yes
Is DQ7 same as bit loaded?
No
Is DQ6 the same?
Erase, Program, or Write Completed
Erase, Program, or Write Completed
327 ILL F23.1
FIGURE 51: END-OF-WRITE, ERASE, OR PROGRAM WAIT OPTIONS FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Concurrent Operation Load SDP Command Sequence
Flash Program/Erase or E2 Write Initiated
Wait for End-of-Write Indication End Wait
Read Another Bank
Flash Operation Completed
End Concurrent Operation
327 ILL F24.1
FIGURE 52: CONCURRENT OPERATION FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet Device SST38VF166 Speed XXX Suffix1 XX Suffix2 XX Package Modifier K = 48 balls Package Type E = TSOP (12mm x 20mm) Temperature Range C = Commercial = 0C to +70C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Voltage V = 2.7-3.6V SST38VF166 Valid combinations SST38VF166-70-4C-EK
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
PACKAGING DIAGRAMS
1.05 0.95 .50 BSC
Pin # 1 Identifier
.270 .170
12.20 11.80
18.50 18.30
0.15 0.05
0.70 0.50
20.20 19.80
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 48.TSOP-EK-ILL.5 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
48-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK
(c)2001 Silicon Storage Technology, Inc.
327-3 2/01
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16 Megabit FlashBank Memory SST38VF166
Data Sheet
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. 327-3 2/01 S71065
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