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Integrated Circuit Systems, Inc.
ICS951601
Preliminary Product Preview
General Purpose Frequency Timing Generator
Recommended Application: General Purpose Clock Generator Output Features: * 17 - PCI clocks selectable, either 33.33MHz or 66.6MHz @ 3.3V * 1 - 48MHz @ 3.3V * 1 - REF @ 3.3V, 14.318MHz. Features: * * * Programable Spread spectrum precentage for EMI control Uses external 14.318MHz crystal Select pins for frequency select
Pin Configuration
REF0 VDD X1 X2 GND SDATA SCLK GNDA VDDA SEL1A PCI1A_0 PCI1A_1 VDD33 GND PCI1A_2 PCI1A_3 GND VDD33 PCI1A_4 PCI1A_5 VDD33 GND PCI1A_6 PCI1A_7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48MHz GND VDD48 SPREAD VDDA GNDA SEL2B PCI2B_2 PCI2B_1 GND VDD66 PCI2B_0 SEL2A PCI2A_2 PCI2A_1 VDD2A GND PCI2A_0 SEL1B PCI1B_2 PCI1B_1 GND VDD1B PCI1B_0
Key Specifications: * PCI - PCI output skew within same bank @ 33MHz: <170ps * * * * * * PCI - PCI output skew within same bank@ 66MHz: <340ps Cycle to Cycle Jitter PCI @ 33MHz: <200ps Cycle to Cycle Jitter PCI @ 66MHz: <200ps Cycle to Cycle Jitter 48MHz: <350ps Cycle to Cycle Jitter REF: <500ps Slew Rate: 1.5 - 4 V/ns. (PCI spec.)
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2 48MHz
X1 X2
XTAL OSC PLL1 Spread Spectrum
PCI DIVDER
REF0
8 PCI1A (7:0)
PCI DIVDER
3 PCI2A (2:0)
SDATA SCLK SELA (2:1) SELB (2:1) SPREAD
Control Logic Config. Reg.
PCI DIVDER
3 PCI1B (2:0)
PCI DIVDER
3 PCI2B (2:0)
Power Groups:
VDDA = Analog Power GNDA = Analog Ground
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PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS951601
ICS951601
Preliminary Product Preview
Pin Descriptions
Pin number 1 2, 13, 18, 21, 26, 33, 38, 46 3 4 9, 44 10, 30, 36, 42 5, 14, 17, 22, 27, 32, 39, 47 6 7 8, 43 24, 23, 20, 19, 16, 15, 12, 11, 29, 28, 25 35, 34, 31 41, 40, 37 45 48 Pin name REF0 VDD X1 X2 VDDA SELxx GND SDATA SCLK GNDA PCI1A (7:0) PCI1B (2:0) PCI2A (2:0) PCI2B (2:0) SPREAD 48MHz Type OUT PWR IN OUT PWR IN PWR I/O IN PWR OUT OUT OUT OUT IN OUT Description Reference output 3.3V Power supply Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Analog 3.3V Power supply Real time PCI output frequency selection pins Ground pins Data pin for I2C circuitry 5V tolerant Clock input of I2C input Analog ground pins PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. PCI clock outputs, selectable to be either 33.33 or 66.66MHz at 3.3V. Enables Spread Spectrum, default is on. Fixed 48MHz clock output for USB.
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ICS951601
Preliminary Prouct Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: * Controller (host) sends a start bit. * Controller (host) sends the write address D2 (H) * ICS clock will acknowledge * Controller (host) sends a dummy command code * ICS clock will acknowledge * Controller (host) sends a dummy byte count * ICS clock will acknowledge * Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit How to Read: * Controller (host) will send start bit. * Controller (host) sends the read address D3 (H) * ICS clock will acknowledge * ICS clock will send the byte count * Controller (host) acknowledges * ICS clock sends first byte (Byte 0) through byte 5 * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS951601
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit2 Bit7 Bit6 Bit5 Bit4 66MHZ 33MHz FEATURES FS4 FS3 FS2 FS1 FS0 66 33 -0.25 % down spread 0 0 0 0 0 66 33 -0.5 % down spread 0 0 0 0 1 66 33 -1.0 % down spread 0 0 0 1 0 66 33 -1.5 % down spread 0 0 0 1 1 66 33 + 0.25 % center spread 0 0 1 0 0 66 33 +0.5 % center spread 0 0 1 0 1 66 33 + 1.0 % center spread 0 0 1 1 0 66.6 33.3 +1.5 % center spread 0 0 1 1 1 67.32 33.66 2% over-clocking 0 1 0 0 0 68.64 34.32 4% over-clocking 0 1 0 0 1 69.96 34.98 6% over-clocking 0 1 0 1 0 Bit 72.6 36.3 10% over-clocking 0 1 0 1 1 2,7:4 0 65.27 32.63 2% under- clocking 1 1 0 0 63.96 31.97 2% under- clocking 0 1 1 0 1 62.6 31.3 2% under- clocking 0 1 1 1 0 60 30 2% under- clocking 0 1 1 1 1 66.6 33.3 -1.4 % down spread 1 0 0 0 0 66.6 33.3 -1.6 % down spread 1 0 0 0 1 66.6 33.3 -1.8 % down spread 1 0 0 1 0 66.6 33.3 -2.0 % down spread 1 0 0 1 1 66.6 33.3 + 1.4 % center spread 1 0 1 0 0 66.6 33.3 + 1.6 % center spread 1 0 1 0 1 66.6 33.3 + 1.8 % center spread 1 0 1 1 0 66.6 33.3 + 2.0 % center spread 1 0 1 1 1 0-Frequency and Spread is seleced by hardware select. Latched input Bit3 1-Frequency is seleced by Bit2, 7:4 Bit1 0-Normal 1-Spread spectrum Enabled Bit0 0-Running 1-Tristate all outputs Bit PWD
00000
0 0 0
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ICS951601
Preliminary Prouct Preview
Byte 1: PCI1A Stop Clocks Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin # 24 23 20 19 16 15 12 11 PWD 1 1 1 1 1 1 1 1 Description PCI1A_7 PCI1A_6 PCI1A_5 PCI1A_4 PCI1A_3 PCI1A_2 PCI1A_1 PCI1A_0
Byte 2: PCI2A Stop Clocks Register (1 = enable, 0 = disable)
Bit
Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin # 35 34 31 29 28 25 -
PWD
Description
1 1 1 1 1 1 X X
PCI2A_2 PCI2A_1 PCI2A_0 PCI1B_2 PCI1B_1 PCI1B_0 Reserved Reserved
Byte 3: PCI2B Stop Clocks Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin # 41 40 37 PWD 1 1 1 X X X X X Description PCI2B_2 PCI2B_1 PCI2B_0 Reserved Reserved Reserved Reserved Reserved
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin # 48 1 PWD 1 1 X X X X X X Description 48MHz REF0 Reserved Reserved Reserved Reserved Reserved Reserved
Byte 5: Latched Input Read Back Register (1= enable, 0 = disable)
Bit Pin # PWD Description
Byte 6: Reserved for Byte Count Register (1= enable, 0 = disable)
Bit Pin # PWD Description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-
X X X X X X X X
SEL2B SEL1B SEL2A SEL1A Reser ved Reser ved Reser ved Reser ved
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-
0 0 0 0 0 1 1 0
Note: PWD = Power-Up Default
Reser ved for read byte count Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
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ICS951601
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; VDD, VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 V DD + 0.3 V Input Low Voltage VIL VSS - 0.3 0.8 V Input High Current IIH VIN = V DD 5 mA Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 mA Operating Supply 160 mA IDD3.3OP100 CL = 0 pF; Select @ 100 MHz Current 160 mA IDD3.3OP133 CL = 0 pF; Select @ 133 MHz Input frequency Fi VDD = 3.3 V; 11 14.318 16 MHz Logic Inputs 5 pF CIN Input Capacitance1 X1 & X2 pins 27 45 pF CINX Transition Time1 Ttrans To 1st crossing of target Freq. 3 ms Settling Time1 Ts From 1st crossing to 1% target Freq. 3 ms 1 Clk Stabilization TSTAB From V DD = 3.3 V to 1% target Freq. 3 ms
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current
1
SYMBOL IDD2.5OP100 I DD2.5OP133 IDD2.5PD
CONDITIONS CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = 0 pF; PWRDWN# = 0
MIN
TYP 16 19 0.1
MAX 75 90 100
UNITS mA mA A
Guaranteed by design, not 100% tested in production.
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ICS951601
Preliminary Prouct Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tsk2 Tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V @ 33.33 VT = 1.5 V @ 66.66 VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ps ps ps
45
55 170 340 500
Skew1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 Tjcyc-cyc5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns % ps
Duty Cycle1 Jitter, Cycle-to-cycle1
1
45
55 350
Guaranteed by design, not 100% tested in production.
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ICS951601
Preliminary Product Preview
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Jitter, Cycle-to-cycle1
1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 Tjcyc-cyc5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns % ps
45
55 500
Guaranteed by design, not 100% tested in production.
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ICS951601
Preliminary Prouct Preview
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 SEE VARIATIONS D E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
VARIATIONS D mm. D (inch) MIN MAX MIN MAX 15.75 16.00 .620 .630
Reference Doc.: JEDEC Publication 95, M O-118
300 mil SSOP Package
Ordering Information
ICS951601yF
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type Prefix ICS = Standard Device
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