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CXD1171M
8-bit 40MSPS High Speed D/A Converter
Description The CXD1171M is a 8-bit 40 MHz high speed D/A converter. The adoption of a current output system reduces power consumption to 80 mW (200 load at 2 Vp-p output). This IC is suitable for digital TV and graphic display applications. Features * Resolution 8-bit * Max. conversion speed 40MSPS * Non linearity error within 0.25 LSB * Low glitch noise * TTL CMOS compatible input * +5 V single power supply * Low power consumption 80 mW (200 load at 2 Vp-p output) Function 8-bit 40 MHz D/A converter Structure Silicon gate CMOS IC 24 pin SOP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage AVDD, DVDD 7 V * Input voltage (All pins) VIN VDD +0.5 to VSS -0.5 V * Output current IOUT 15 mA * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25
DVDD, DVSS 4.75 to 5.25 * Reference input voltage VREF 2.0 V * Clock pulse width Tpw1,Tpw0 11.2 ns (min) to 1.1 s (max) * Operating temperature Topr -40 to +85 C
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E89X38F01
CXD1171M
Block Diagram and Pin Configuration
(LSB) D0 1 D1 D2 D3 D4 D5 D6 (MSB) D7 BLK 2 3 4 5 6 7 8 9 CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR CLOCK GENERATOR DECODER 6MSB'S CURRENT CELLS DECODER LATCHES 2LSB'S CURRENT CELLS
24 DVDD 23 DVDD 22 AVDD 21 20 IO IO
19 AVDD 18 AVDD 17 VG 16 VREF 15 IREF 14 AVSS 13 DVSS
DVSS 10 VB 11 CLK 12
--2--
CXD1171M
Pin Description and I/O Pins Equivalent Circuit No. Symbol I/O Equivalent circuit
DVDD 1
Description
1 to 8
D0 to D7
I
to 8 DVSS
Digital input. D0 (LSB) to D7 (MSB) D0 and D1 have a pull-down resistor.
DVDD
9
BLK
I
9
Blanking input. This is synchronized with the clock signal. No signal at "H" (Output 0 V). Output condition at "L".
DVSS
DVDD DVDD
11
VB
O
11
Connect a capacitor of about 0.1 F.
DVSS
DVDD
12
CLK
I
12
Clock input.
DVSS
10, 13 14
DVSS AVSS
-- --
Digital ground. Analog ground.
--3--
CXD1171M
No.
Symbol
I/O
Equivalent circuit
AVDD AVDD
Description Connect a resistor "RIR" 16 times against the output resistance value "ROUT" connected to Pin 20 (IO).
15
IREF
O
15 AVDD
16
VREF
I
AVSS 16 AVDD
Set full-scale output value.
AVSS
17
17
VG
O
AVSS
Connect a capacitor of about 0.1 F.
18, 19, 22 AVDD
--
AVDD
Analog power supply.
20
IO
20
Current output. Voltage output can be obtained by connecting a resistance.
AVSS AVDD
O
21
IO
21
Inverted current output. Normally connected to analog GND.
AVSS
23, 24
DVDD
--
Digital power supply.
--4--
CXD1171M
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale current Output offset voltage Glitch energy Supply current Analog input resistance Input capacitance Digital input voltage Symbol n FCLK EL ED VFS IFS VOS GE IDD RIN CI VIH VIL IIH IIL tS tH tPD
(FCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 , VREF=2.0 V, Ta=25 C) Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=-40 to 85 C Endpoint Min. Typ. 8 Max. Unit bit MSPS LSB LSB V mA mV pV * s mA M pF V
0.5 -0.5 -0.25 1.9
40 1.3 0.25 2.1 15 1 16 9
2.0 10 30 14.5
When D0 to D7=00000000 input ROUT=75 When 14.3 MHz color bar data input VREF AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C AVDD=DVDD=4.75 to 5.25 V D0, D1 Ta=-20 to +75 C D2 to 7, BLK, CLK ROUT=75 ROUT=75
13 1 2.4 -5 -5 5 10
0.8 240 5
Digital input current
A
Setup time Hold time Propagation delay time
10
ns ns ns
Electrical Characteristics Measurement Circuit Analog Input Resistance Digital Input Current
}
Measurement Circuit
+5.25V
AVDD, DVDD
A
CXD1171M
V
AVSS, DVSS
--5--
CXD1171M
Maximum Conversion Speed Measurement Circuit
1 D0 (LSB) * * * 2 8 D7 VG 17 9 BLK 0.1 CLK 40MHZ SQUARE WAVE 11 VB 12 CLK IREF 15 3.3k VREF 16 0.1 2V AVss 1k AVDD IO 20 200 OSCILLOSCOPE
8bit COUNTER with LATCH
DC Characteristics Measurement Circuit
1 CONTROLLER * * * 2
D0 (LSB)
IO 20 200
DVM
8 D7 VG 17 9 BLK 0.1 VREF 16 11 VB 12 CLK IREF 15 2V
AVDD 1k AVss 3.3k
0.1 CLK 40MHZ SQUARE WAVE
Propagation Delay Time Measurement Circuit
1 D0 (LSB) * * * 2 8 D7 VG 17 FREQUENCY DEMULTIPLIER 9 BLK 0.1 11 VB AVss 12 CLK IREF 15 3.3k VREF 16 0.1 1k AVDD IO 20 200 OSCILLOSCOPE
CLK 10MHZ SQUARE WAVE
Setup Time Hold Time Glitch Energy
}
measurement Circuit
8bit COUNTER with LATCH DELAY CONTROLLER 1 D0 (LSB) * * * 2 8 D7 VG 17 9 BLK 0.1 11 VB 12 CLK IREF 15 1.2k VREF 16 0.1 1V AVss 1k AVDD IO 20 75 OSCILLOSCOPE
CLK 1MHZ SQUARE WAVE
DELAY CONTROLLER
--6--
CXD1171M
Operation
tPW1 tPW0
Timing Chart
CLK 2V
tS tH
tS tH
tS tH
DATA
tPD
100%
D/A OUT tPD tPD
50%
0%
I/O Chart (when full-scale output voltage at 2.00 V) Input code MSB LSB 11111111 : 10000000 : 00000000 Output voltage 2.0 V 1.0 V 0V
Application Circuit
(LSB) 1 2 3 8bit DIGITAL INPUT 4 5 6 7 8 9 10 0.1 11 12 14 13 24 23
DVDD
AVDD 22 21 AGND 20 200 19 18 0.1 17 2V 16 15 3.3k 1k D/A OUT
DGND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--7--
CXD1171M
Notes on Operation * How to select the output resistance The CXD1171M is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pin IO. For specifications we have: Output full scale voltage VFS = 1.9 to 2.1 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS x ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF x 16ROUT/RIR. ROUT is the resistance connected to IO while RIR is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. * Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. * Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 F, as close as possible to the pin. * Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. * IO pin The IO pin is the inverted current output pin described in the Pin Description. The sum of the currents output from the IO pin and the IO pin becomes the constant value for any input data. However, the performances such as the linearity error of the IO pin output current is not guaranteed.
--8--
CXD1171M
Latch Up Prevention The CXD1171M is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 18, 19 and 22) and DVDD (Pins 23 and 24), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
18 19 AVDD +5V +5V C
22
23 24 DVDD C DIGITAL IC
CXD1171M
AVSS 14 AVSS
DVSS 10 13 DVSS
b. When analog and digital supplies are from a common source (i)
DVDD
18
19 22 AVDD
23
24
DVDD C DIGITAL IC
+5V C CXD1171M
AVSS 14 AVSS
DVSS 10 13 DVSS
(ii)
DVDD
18
19 22 AVDD
23
24
DVDD C DIGITAL IC
+5V C CXD1171M
AVSS 14 AVSS
DVSS 10 13 DVSS
--9--
CXD1171M
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 18 19 AVDD +5V +5V C CXD1171M 22 23 24 DVDD C DIGITAL IC
AVSS AVSS 14
10 DVSS
DVSS 13
b. When analog and digital supplies are from common source (i)
DVDD AVDD 18 19 AVDD +5V C CXD1171M C DIGITAL IC 22 23 24 DVDD
AVSS AVSS 14 DVSS
DVSS 10 13
(ii)
DVDD AVDD 18 19 AVDD +5V CXD1171M C DIGITAL IC 22 23 24 DVDD
AVSS AVSS 14
DVSS 10 DVSS 13
--10--
CXD1171M
200
Output full scale voltage VFS [V]
2.0
Glitch energy GE [pV * s]
AVDD=DVDD=5.0V VREF=2.0V RIR 16ROUT Ta=25C 100
1.0 AVDD=DVDD=5.0V ROUT=200 RIR=3.3k Ta=25C 0 1.0 2.0
0
100
200
Reference voltage VREF [V] Reference voltage vs. Output full scale voltage
Output resistance ROUT [] Output resistance vs. Glitch energy
Output full-scale voltage VFS [V]
2.0
1.9 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200 RIR=3.3k 0 -25 0 25 50 75 Ambient temperature Ta [C] Ambient temperature vs. Output full scale voltage
--11--
CXD1171M
Package Outline
Unit : mm
24PIN SOP (PLASTIC)
+ 0.4 15.0 - 0.1 24 13
+ 0.4 1.85 - 0.15 0.15
+ 0.3 5.3 - 0.1
7.9 0.4
+ 0.2 0.1 - 0.05
0.24
M
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.3g
--12--
0.5 0.2
1 0.45 0.1
12
6.9
+ 0.1 0.2 - 0.05
1.27

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