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| LM75 2-Wire Serial Temperature Sensor and Monitor The LM75 is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user-programmed setpoint. Hysteresis is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication with the LM75 is accomplished via a two-wire bus that is compatible with industry standard protocols. This permits reading the current temperature, programming the setpoint and hysteresis, and configuring the device. The LM75 powers up in Comparator Mode with a default setpoint of 80C with 5C hysteresis. Defaults allow independent operation as a stand-alone thermostat. A shutdown command may be sent via the 2-wire bus to activate the low-power standby mode. Address selection inputs allow up to eight LM75's to share the same 2-wire bus for multi-zone monitoring. All registers can be read by the host and the INT/CMPTR output's polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease of use make the LM75 an ideal choice for implementing sophisticated system management schemes. Features * Temperature Sensing: 0.5C Accuracy (Typ.) * Operates from: 55C to +125C * Operating Range: 2.7V - 5.5V * Programmable Trip Point and Hysteresis with Power-up Defaults * Standard 2-Wire Serial Interface * Thermal Event Alarm Output Functions as Interrupt or Comparator / Thermostat Output * Up to 8 LM75's May Share the Same Bus * Shutdown Mode for Low Standby Power Consumption * 5V Tolerant I/O at VDD = 3V * Low Power 250A (Typ.) Operating, 1A (Typ.) Shutdown Mode Typical Applications * Thermal Protection for High Performance CPUs * Solid-State Thermometer * Fire/Heat Alarms * Thermal Management in Electronic Systems: Computers Telecom Racks Power Supplies / UPS * Copiers / Office Electronics * Consumer Electronics / Amplifiers * Process Control http://onsemi.com Micro8 DM SUFFIX CASE TBD PRELIMINARY INFORMATION PIN CONFIGURATION (Top View) SDA 1 SCL 2 INT/CMPTR 3 GND 4 LM75 8 V DD 7 A0 6 A1 5 A2 ORDERING INFORMATION Device LM75DM-33R2 LM75DM-50R2 Package Micro-8 Micro-8 Shipping 2500 Tape/Reel 2500 Tape/Reel (c) Semiconductor Components Industries, LLC, 1999 1 February, 2000 - Rev. 0 Publication Order Number: LM75/D AAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A PIN DESCRIPTION Pin No. 8 7 6 5 4 3 2 1 INT/CMPTR Symbol GND VDD SDA SCL A0 A1 A2 Power Supply Input Address Select Pin (LSB) Address Select Pin Address Select Pin (MSB) System Ground Interrupt or Comparator Output Serial Data Clock Input Bidirectional Serial Data t DH SDA Data Out SDA Data In SCL t H (START) SCL SDA V A A A DD 2 1 0 Temp Sensor FUNCTIONAL BLOCK DIAGRAM Two Wire Serial Port Interface TIMING DIAGRAM http://onsemi.com A/D Converter t 9 Bit SC Configuration Temperature DS LM75 Register Set t DSU 2 T SET T HYST Control Logic LM75 Description INT/ CMPTR t SU (STOP) LM75 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage (VDD) ESD Susceptibility Input Voltage, On Pins: A0, A1, A2 SDA, SCL, INT/CMPTR Operating Temperature Range (TJ) Storage Temperature Range (TSTG) Lead Temperature Range (Soldering, 10 sec) Thermal Resistance (Junction to Ambient) * Maximum Ratings are those values beyond which damage to the device may occur. Value 6.0 1000 (GND - 0.3) to (VCC + 0.3) (GND - 0.3) to 5.5 -55 to +125 -65 to +150 +300 250 C C C C/W Unit V V V ELECTRICAL CHARACTERISTICS (Specifications Measured Over Operating Temperature Range, V+ = 5V, COSC = 0, Test Circuit (Figure 1), unless otherwise noted. Symbol V+H V+L I+ ROUT Characteristic Supply Voltage Range, High (-40C TA +85C, RL = 10 kW, LV Open) Supply Voltage Range, Low (-40C TA +85C, RL = 10 kW, LV to GND) Supply Current (RL = Min 3.0 1.5 -- -- -- -- -- -- 95 97 -- -- Typ -- -- 80 70 -- -- 150 10 98 99.9 1000 100 Max 10 V 3.5 180 100 120 130 300 -- -- -- -- -- A Unit V R) Output Source Resistance IOUT = 20mA, TA = 25C IOUT = 20mA, 0C TA +70C IOUT = 20mA, -40C TA +85C V+ =2V, IOUT = 3 mA, LV to GND, 0C TA +70C Oscillator Frequency (Pin 7 Open) Power Efficiency (RL = 5kW) Voltage Conversion Efficiency Oscillator Impedance V+ = 2V V+ = 5V W FOSC PEFF VOUT EFF ZOSC kHz % % kW http://onsemi.com 3 LM75 DETAILED OPERATING DESCRIPTION A typical LM75 hardware connection is shown in Figure 1. +V DD C Bypass 8 A0 Address (Set as Desired) A 1 A2 Two Wire Interface SDA SCL 7 6 5 Slave Address The four most significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the LM75 to respond with an Acknowledge (indicating the LM75 is on the bus and ready to accept data). The Slave Address is represented by: LM75 Slave Address 1 MSB 0 0 1 A2 A1 A0 LSB 0.1mF Recommended Unless Device is Mounted Close to CPU 3 TCN75 1 2 4 INT/CMPTR Comparator/Interrupt Modes Figure 1. Typical Application Serial Data (SDA) Bidirectional. Serial data is transferred in both directions using this pin. Serial Clock (SCL) Input. Clocks data into and out of the LM75. INT/CMPTR Open Collector, Programmable Polarity. In Comparator Mode, unconditionally driven active any time temperature exceeds the value programmed into the TSET register. INT/CMPTR will become inactive when temperature subsequently falls below the THYST setting. (See Register Set and Programmer's Model.) In Interrupt Mode, INT/CMPTR is made active by TEMP exceeding TSET; it is unconditionally reset to its inactive state by reading any register via the 2-wire bus. If and when temperature falls below THYST, INT/CMPTR is again driven active. Reading any register will clear the THYST interrupt. In Interrupt Mode, the INT/CMPTR output is unconditionally reset upon entering Shutdown Mode. If programmed as an active-low output, it can be wire-ORed with any number of other open collector devices. Most systems will require a pull-up resistor for this configuration. Note that current sourced from the pull-up resistor causes power dissipation and may cause internal heating of the LM75. To avoid affecting the accuracy of ambient temperature readings, the pull-up resistor should be made as large as possible. INT/CMPTR's output polarity may be programmed by writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low. Address (A2, A1, A0) INT/CMPTR behaves differently depending on whether the LM75 is in Comparator Mode or Interrupt Mode. Comparator Mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds TSET. When in Comparator Mode, INT/CMPTR will remain active until TEMP falls below THYST, whereupon it will reset to its inactive state. The state of INT/CMPTR is maintained in shutdown mode when the LM75 is in comparator mode. In Interrupt Mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below THYST, until any register is read via the 2-wire bus. Interrupt Mode is better suited to interrupt driven microprocessor-based systems. The INT/CMPTR output may be wire-OR'ed with other interrupt sources in such systems. Note that a pull-up resistor is necessary on this pin since it is an open-drain output. Entering Shutdown Mode will unconditionally reset INT/CMPTR when in Interrupt Mode. SHUTDOWN MODE When the appropriate bit is set in the configuration register (CONFIG) the LM75 enters its low-power shutdown mode (IDD = 1A, typical) and the temperature-to-digital conversion process is halted. The LM75's bus interface remains active and TEMP, TSET, and THYST may be read from and written to. Transitions on SDA or SCL due to external bus activity may increase the standby power consumption. If the LM75 is in Interrupt Mode, the state of INT/CMPTR will be RESET upon entering shutdown mode. Fault Queue Inputs. Sets the three least significant bits of the LM75 8-bit address. A match between the LM75's address and the address specified in the serial bit stream must be made to initiate communication with the LM75. Many protocol-compatible devices with other addresses may share the same 2-wire bus. To lessen the probability of spurious activation of INT/CMPTR the LM75 may be programmed to filter out transient events. This is done by programming the desired value into the Fault Queue. Logic inside the LM75 will prevent the device from triggering INT/CMPTR unless the programmed number of sequential temperature-to-digital conversions yield the same qualitative result. In other words, the value reported in TEMP must remain above TSET or below THYST for the consecutive number of cycles http://onsemi.com 4 LM75 programmed in the Fault Queue. Up to a six-cycle "filter" may be selected. See Register Set and Programmer's Model. Serial Port Operation (SDA changes while SCL is HIGH are reserved for Start and Stop Conditions). Start Condition (START) The Serial Clock input (SCL) and bidirectional data port (SDA) form a 2-wire bidirectional serial port for programming and interrogating the LM75. The following conventions are used in this bus scheme: LM75 Serial Bus Conventions Term Explanation The LM75 continuously monitors the SDA and SCL lines for a start condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. (See Timing Diagram) Address Byte Transmitter The device sending data to the bus. Receiver Master The device receiving data from the bus. The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). The device addressed by the master. A unique condition signaling the beginning of a transfer indicated by SDA falling (High-Low) while SCL is high. A unique condition signaling the end of a transfer indicated by SDA rising (Low - High) while SCL is high. A Receiver acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock-pulse. The Master provides the clock pulse for the ACK cycle. When the bus is idle, both SDA & SCL will remain high. The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See Start and Stop conditions) Slave Start Immediately following the Start Condition, the host must next transmit the address byte to the LM75. The four most significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001(B). The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the LM75 to respond with an Acknowledge (indicating the LM75 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read-Write Bit. This bit is a 1 for a read operation or 0 for a write operation. Acknowledge (ACK) Stop ACK Acknowledge (ACK) provides a positive handshake between the host and the LM75. The host releases SDA after transmitting eight bits then generates a ninth clock cycle to allow the LM75 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address. Data Byte NOT Busy Data Valid After a successful ACK of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the LM75. Stop Condition (STOP) All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which provides the clock signal for all transfers. The LM75 always operates as a Slave. This serial protocol is illustrated in Figure 2. All data transfers have two phases; and all bytes are transferred MSB first. Accesses are initiated by a start condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW Communications must be terminated by a stop condition (a LOW to HIGH transition of SDA while SCL is HIGH). The Stop Condition must be communicated by the transmitter to the LM75. (See Timing Diagram) Power Supply To minimize temperature measurement error, the LM75DM-33 is factory calibrated at a supply voltage of 3.3V 5% and the LM75DM-50 is factory calibrated at a supply voltage of 5V 5%. Either device is fully operational over the power supply voltage range of 2.7V to 5.5V, but with a lower measurement accuracy. The typical value of this power supply-related error is 2C. http://onsemi.com 5 LM75 1 9 1 9 1 9 1 Start by Master 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Stop No Ack Cond by by Master Master Address Byte Ack Most Significant Data Byte by LM75 9 1 Ack by Master 9 Least Significant Data Byte (a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, THYST 1 ..... 1 Start by Master 0 0 1 A2 A1 A0 R/W Ack by LM75 0 0 0 0 0 0 D1 D0 Ack by LM75 9 1 9 ..... Address Byte 1 Pointer Byte 9 1 1 Repeat Start by Master 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Stop No Ack Cond by by Master Master Address Byte Ack by Most Significant Data Byte LM75 Ack by Master Least Significant Data Byte (b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, TOS, THYST 1 9 1 9 1 Start by Master 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Data Byte Stop No Ack Cond by by Master Master Address Byte Ack by LM75 (c) Typical 1-Byte Read From Configuration Register With Preset Pointer 1 9 1 9 1 9 1 9 1 Start by Master 0 0 1 A2 A1 A0 R/W Ack by LM75 0 0 0 0 0 0 0 D0 1 0 0 1 A2 A1 A0 R/W Ack by LM75 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte Stop No Ack Cond by by Master Master Address Byte Pointer Byte Ack Repeat by Start LM75 by Master 9 1 Address Byte (d) Typical Pointer Set Followed by Immediate Read from Configuration Register 1 9 1 9 1 Start by Master 0 0 1 A2 A1 A0 R/W Ack by LM75 0 0 0 0 0 0 D1 D0 Ack by LM75 0 0 0 D4 D3 D2 D1 D0 Stop Ack Cond by by LM75 Master Address Byte Pointer Byte Configuration Byte (e) Configuration Register Write 1 9 1 9 1 91 9 1 Start by Master 0 0 1 A2 A1 A0 R/W Ack by LM75 0 0 0 0 0 0 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Ack by LM75 Most Significant Data Byte D7 D6 D5 D4 D3 D2 D1 D0 Least Significant Data Byte Stop Ack Cond by by LM75 Master Address Byte Pointer Byte Ack by LM75 (f) TOS and THYST Write Figure 2. Serial Port Operation http://onsemi.com 6 LM75 REGISTER SET AND PROGRAMMER'S MODEL Register (POINT), 8-bits, Write-only Pointer Register (POINT) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Must Be Set To Zero Pointer Register Selection via the Pointer Register: D1 0 0 1 1 D0 0 1 0 1 Register Selection TEMP CONFIG THYST TSET Configuration Register (CONFIG), 8-bits, Read/Write Configuration Register (CONFIG) D[7] D[6] D[5] D[4] D[3] D[2] INT/ CMPTR. POLARITY D[1] COMP/ INT. D[0] Shut- Down Must Be Set To Zero Fault Queue D0: Shutdown: 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High D3 - D4: Fault Queue: Number of sequential temperature-to-digital conversions with the same result before the INT/CMPTR output is updated: D4 0 0 1 1 D3 0 1 0 1 Number of Conversions 1 (Power-up-default) 2 4 6 http://onsemi.com 7 LM75 Temperature (TEMP) Register, 16-bits, Read-only The binary value in this register represents ambient temperature following a conversion cycle. Temperature Register (TEMP) D[15] MSB D[14] D7 D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] X D[1] X D[0] X Temperature Setpoint (TSET) and Hysteresis (THYST) Register, 16-bits, Read-Write: Temperature Setpoint Register (TSET) D[15] MSB D[14] D7 D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] X D[1] X D[0] X Hysteresis Register (THYST) D[15] MSB D[14] D7 D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] X D[1] X D[0] X In the TEMP, TSET, and THYST registers, each unit value represents one-half degree (Celsius). The value is in 2's - complement binary format such that a reading of 000000000b corresponds to 0C. Examples of this temperature to binary value relationship are shown in the following table. Temperature to Digital Value Conversion Temperature +125C +25C +0.5C 0C -- 0.5C -- 25C -- 40C -- 55C Binary Value 0 11111010 0 00110010 0 00000001 0 00000000 1 11111111 1 11001110 1 10110000 1 10010010 HEX Value 0FA 032 001 00 1FF 1CE 1B0 192 The LM75's register set is summarized below Name TEMP TSET THYST POINT CONFIG Description Ambient Temperature Temperature Setpoint Temperature Hysteresis Register Pointer Configuration Register Width 16 16 16 8 8 Read X X X X X X X X X Write Notes 2's Complement Format 2's Complement Format 2's Complement Format http://onsemi.com 8 LM75 TAPE AND REEL INFORMATION Component Taping Orientation for Micro-8 Devices USER DIRECTION OF FEED PIN 1 Standard Reel Component Orientation for R2 Suffix Device (Mark Right Side Up) Tape & Reel Specifications Table Package Micro-8 Tape Width (W) 12 mm Pitch (P) 4 mm Part Per Full Reel 2500 Diameter 13 inches MARKING LM75DM-33 LM75DM-50 LM75 33 LM75 50 http://onsemi.com 9 LM75 PACKAGE DIMENSIONS Micro8 PLASTIC PACKAGE CASE TBD ISSUE TBD PIN 1 .122 (3.10) .197 (5.00) .114 (2.90) .187 (4.80) .026 (0.65) TYP. .122 (3.10) .114 (2.90) .043 (1.10) MAX. .006 (0.15) .016 (0.40) .002 (0.05) .010 (0.25) 6 MAX. .008 (0.20) .005 (0.13) .028 (0.70) .016 (0.40) Dimensions: inches (mm) http://onsemi.com 10 LM75 Notes http://onsemi.com 11 LM75 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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