| PART |
Description |
Maker |
| CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350 |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| CY7C1415BV18-250BZI CY7C1415BV18-167BZI |
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 1M X 36 QDR SRAM, 0.45 ns, PBGA165
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| PRESENTATION |
Presentation - AMDNext Generation Microprocessor Architecture
AMDs Next Generation Microprocessor Architecture
|
Advanced Micro Devices
|
| M5LV-256_104-10VC M5LV-256_104-10VI M5LV-256_104-1 |
7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
20ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
12ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
15ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
|
LATTICE[Lattice Semiconductor]
|
| UPD4264405G5-A50-7JD UPD4265405G5-A50-7JD UPD42S65 |
2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture
x4 EDO Page Mode DRAM
512K (32K x 16) Static RAM
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
128K x 8 Static RAM 128K的8静态RAM
|
Omron Electronics, LLC
|
| CY7C1333 7C1333 CY7C1333-66AC CY7C1333-50AC |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
From old datasheet system
|
Cypress Semiconductor Corp.
|
| CY7C1518KV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1315CV18-200BZC CY7C1315CV18-250BZC |
18-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V 512K X 36 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1305AV18 CY7C1305AV18-100BZC CY7C1305AV18-133B |
18-Mb Burst of 4 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 4 Pipelined SRAM with QDR⑩ Architecture
|
Cypress Semiconductor
|
| CY7C1354CV25-225AXI CY7C1354CV25-167AXI CY7C1356CV |
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture 9兆位56 × 36/512K × 18）流水线的SRAM的总线延迟TM架构
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture 9兆位56 × 36/512K × 18）流水线的SRAM的总线延迟，TM架构
|
Cypress Semiconductor Corp.
|
