| PART |
Description |
Maker |
| HCTS109HMSR HCTS109KMSR HCTS109K HCTS109D HCTS109D |
Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 辐射加固双JK触发器拖
Radiation Hardened Dual JK Flip Flop
From old datasheet system
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| 74AUP2G79GF 74AUP2G79GS |
Low-power dual D-type flip-flop; positive-edge trigger AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| 74LCX16821 74LCX16821MEA 74LCX16821MTD 74LCX16821M |
Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
20-Bit D-Type Flip-Flop LVC/LCX/Z SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
From old datasheet system
Low Voltage 20-Bit D-Type Flip-Flops with 5V Tolerant Inputs and Outputs
|
Fairchild Semiconductor, Corp.
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| 74AUP2G80GT 74AUP2G80GM 74AUP2G80DC 74AUP2G80 74AU |
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
|
PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
|
| 74LCX74SJ 74LCX74MX_NL 74LCX74 74LCX74BQX 74LCX74M |
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC14
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| EN29F040A-70TI EN29F040A-70TC EN29F040A-70TCP EN29 |
4 Megabit (512K x 8-bit) Flash Memory 4兆位（为512k × 8位）闪存
Dual D-Type Positive Edge-Triggered Flip-Flop; Package: DIP; No of Pins: 14; Container: Rail
Dual D-Type Positive Edge-Triggered Flip-Flop; Package: TSSOP; No of Pins: 14; Container: Tape & Reel
Dual D-Type Positive Edge-Triggered Flip-Flop; Package: TSSOP; No of Pins: 14; Container: Rail
4 Megabit (512K x 8-bit) Flash Memory
|
Electronic Theatre Controls, Inc.
Eon Silicon Solution Inc.
Eon Silicon Solution In...
|
| CD4013BC CD4013BCM CD4013BCN CD4013BCSJ CD4013 |
Dual D-Type Flip-Flop
|
FAIRCHILD[Fairchild Semiconductor]
|
| CMOS4013 |
Dual D-type flip-flop
|
ETC
|
