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CY7C1548V18-300BZC - 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165

CY7C1548V18-300BZC_3915563.PDF Datasheet
 
Part No. CY7C1548V18-300BZC CY7C1548V18-300BZI CY7C1548V18-300BZXI CY7C1548V18-300BZXC CY7C1546V18-300BZI CY7C1546V18-300BZXI CY7C1548V18-375BZC CY7C1548V18-375BZI
Description 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165
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Cypress Semiconductor, Corp.

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 Full text search : 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165

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18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
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72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
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36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
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