PART |
Description |
Maker |
IDT71P73204 IDT71P73204167BQ IDT71P73804 IDT71P738 |
18Mb Pipelined DDR垄芒II SRAM Burst of 4 18Mb Pipelined DDR?⑸I SRAM Burst of 4 18Mb Pipelined DDR?II SRAM Burst of 4
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Integrated Device Technology Integrated Device Techn...
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M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation. Renesas Electronics, Corp.
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CY7C1382CV25-167AI CY7C1382CV25-200BZI CY7C1382CV2 |
512K x 36 pipelined SRAM, 167MHz 512K x 36/1M x 18 Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PBGA165 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3.4 ns, PBGA165 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.8 ns, PBGA165 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.8 ns, PQFP100 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA119 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA119 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PQFP100 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PQFP100 512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA165 TRANS DARL PNP 100V 8A TO-220FP 1M X 18 CACHE SRAM, 3.4 ns, PQFP100 512K x 36 pipelined SRAM, 225MHz
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Cypress Semiconductor, Corp.
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KM48L16031BT-GFZ/Y/0 KM416L8031BT-GFZ/Y/0 KM44L160 |
DDR SDRAM Specification Version 0.61 DDR SDRAM的规格版.61 16M X 8 DDR DRAM, 0.8 ns, PDSO66 0.400 X 0.875 INCH, 0.65 MM PITCH, MS-024FC, TSOP2-66
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Samsung Semiconductor Co., Ltd. SAMSUNG SEMICONDUCTOR CO. LTD.
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CY7C1474V33-167BGC CY7C1470V33-250AXC CY7C1470V33- |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3 ns, PBGA165 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3.4 ns, PBGA165 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 1M X 72 ZBT SRAM, 3.4 ns, PBGA209 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 2M X 36 ZBT SRAM, 3.4 ns, PBGA165
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Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
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PLL103-03 PLL103-03XC PLL103-03XI PLL103-03XM |
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS
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PhaseLink Corporation
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HM5425801B |
256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM) 256M DDR SDRAM的接口SSTL_256M SSTL_2接口的DDR同步DRAM)的
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Hitachi,Ltd.
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IDT709149S 709149_DS_24983 IDT709149S8PF IDT709149 |
4K x 9 Sync, Dual-Port RAM, Pipelined HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM From old datasheet system
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IDT[Integrated Device Technology]
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CY7C1352F CY7C1352F-100AC CY7C1352F-100AI CY7C1352 |
4-Mbit (256Kx18) Pipelined SRAM with NoBLArchitecture 256K X 18 ZBT SRAM, 2.8 ns, PQFP100 4-Mbit (256Kx18) Pipelined SRAM with NoBL(TM) Architecture 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture 4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Architecture
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Cypress Semiconductor, Corp. Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
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HYS72D64020GR HYS72D128020GR HYS72D64000GR |
2.5 V 184-pin Registered DDR-I SDRAM Modules(2.5 V 184脚G位寄存型 DDR-I SDRAM 模块) 2.5 V 184-pin Registered DDR-I SDRAM Modules(2.5 V 184脚12M位寄存型 DDR-I SDRAM 模块) 2.584针注册的DDR - 1 SDRAM的模块(2.584脚,512M的位寄存型的DDR - SDRAM内存模块余)
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SIEMENS AG
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M312L6523BTS-CAA M312L2923BTS-A2 M312L2923BTS-CAA |
64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 64M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 26615150 DDR SDRAM的注册模 DDR SDRAM Registered Module
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Samsung Semiconductor Co., Ltd. SAMSUNG SEMICONDUCTOR CO. LTD.
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