| PART |
Description |
Maker |
| NC7WV07P6X NC7WV07 NC7WV07L6X |
TinyLogic ULP-A Dual Buffer (Open Drain Output) AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, DSO6
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| NC7WP17 NC7WP17L6X NC7WP17P6X |
TinyLogic ULP Dual Buffer with Schmitt Trigger Input (Preliminary)
|
Fairchild Semiconductor
|
| NC7SP126 NC7SP126L6X NC7SP126P5X |
TinyLogic ULP Buffer with 3-STATE Output
TinyLogic ULP Buffer with 3-STATE Output
|
FAIRCHILD[Fairchild Semiconductor]
|
| NC7WP125 NC7WP125L8X NC7WP125K8X |
TinyLogic ULP Buffer with 3-STATE Output
|
ON Semiconductor
|
| NC7WV125L8X NC7WV125 NC7WV125K8X |
TinyLogic ULP-A Buffer with 3-STATE Output
|
FAIRCHILD[Fairchild Semiconductor]
|
| NC7SP126_04 NC7SP126 NC7SP126L6X NC7SP126P5X NC7SP |
TinyLogic ULP Buffer with 3-STATE Output
|
FAIRCHILD[Fairchild Semiconductor]
|
| NC7SV17L6X10 |
TinyLogic? ULP-A Single Buffer with Schmitt Trigger Input
|
Fairchild Semiconductor
|
| NC7WZ07P6X NC7WZ07 NC7WZ07L6X |
TinyLogic UHS Dual Buffer (Open Drain Outputs) LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
TinyLogic UHS Dual Buffer (Open Drain Outputs)
TinyLogic UHS Dual Buffer (Open Drain Outputs)
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| NC7WP0805 NC7WP08L8X NC7WP08 NC7WP08K8X |
TinyLogic ULP Dual 2-Input AND Gate
|
FAIRCHILD[Fairchild Semiconductor]
|
| NC7SV05P5X NC7SV05 NC7SV05L6X |
TinyLogic ULP-A Inverter (Open Drain Output)
TinyLogic ULP-A Inverter (Open Drain Output) AUP/ULP/V SERIES, 1-INPUT INVERT GATE, PDSO6
TinyLogic ULP-A Inverter (Open Drain Output) AUP/ULP/V SERIES, 1-INPUT INVERT GATE, PDSO5
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| NC7SVU04P5X NC7SVU04 NC7SVU04L6X |
TinyLogic ULP-A Unbuffered Inverter
TinyLogic ULP-A Unbuffered Inverter
|
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| NC7SP08 NC7SP08L6X NC7SP08P5X |
TinyLogic ULP 2-Input AND Gate
TinyLogic ULP 2-Input AND Gate
|
FAIRCHILD[Fairchild Semiconductor]
|
