| PART |
Description |
Maker |
| MAX125CEAX 1797 MAX125 MAX126 |
2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
From old datasheet system
IC,DATA ACQ SYSTEM,8-CHANNEL,14-BIT,SOP,36PIN,PLASTIC
|
MAXIM - Dallas Semiconductor
Maxim Integrated Products Inc
|
| K4D28163HD |
2M x 16Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| K4D26323AA-GL |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| HI-8684PST-10 HI-8683 HI-8683PJI HI-8683PJT HI-868 |
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
(HI-8683 / HI-8684) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 8-BIT PARALLEL DATA
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
System component for interfacing incoming ARINC 429 signals to 8-bit parallel data
|
http://
HOLTIC[Holt Integrated Circuits]
HOLT INTEGRATED CIRCUITS INC
Holt Integrated Circuit...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M13S128324A-2M |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| K4D263238M K4D263238M-QC45 K4D263238M-QC50 K4D2632 |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
|
Samsung Electronic
SAMSUNG[Samsung semiconductor]
|
