| PART |
Description |
Maker |
| CP2105-F01-GM CP2105-GM |
Data format: 8 data bits, 1 stop bit Parity: Even, Pdd, No parity Baud rates: 2400 bps to 921600 bps
|
Silicon Laboratories Inc.
|
| HSP9501 |
Programmable Data Buffer(???绋??????插?)
Data Buffer, Programmable, 32MHz, Data Word to 10-Bits
|
Intersil Corporation
|
| XRT75R03D06 |
EXAR DATA SHEET FORMAT TEMPLATES
|
Exar Corporation
|
| MT9174 MT9173 |
2 wire full-duplex 2B D (80/160Kb/s) data format Digital Subscriber Network Interface Circuit (range up to 4Km) with loop length measurement capability for wireless base stations
2 wire full-duplex 2B D (80/160Kb/s) data format Digital Subscriber Network Interface Circuit (range up to 3KM) with loop lengh measurement capability for wireless base station applications
|
Zarlink Semiconductor
|
| HI-8685PST-10 HI-8685PJI HI-8685PJI-10 HI-8685PJT- |
System component for interfacing incoming ARINC 429 signals to 16-bit parallel data
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC28
384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
ARINC 429 & 561 SerialDatato16-BitParallelData
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 16-BIT PARALLEL DATA
|
Holt Integrated Circuit...
HOLT INTEGRATED CIRCUITS INC
Holt Integrated Circuits, Inc.
http://
|
| M13S128324A-2M |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| HI-8785PSTF HI-8783 HI-8783_06 HI-8783PDI HI-8783P |
ARINC INTERFACE DEVICE 8 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
