| PART |
Description |
Maker |
| AND8090 AND8090D MC100H601 MC100H601FN MC10H106FN |
3.3V / 5V ECL Quad 2-Input Differential AND/NAND
5V ECL Low Impedance Driver
LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER
8 Input Priority Encoder
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V Dual Differential LVPECL to LVTTL Translator
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
Fibre Channel Coaxial Cable Driver and Loop Resillency Circuit
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
3.3V / 5V Programmable PLL Synthesized Clock Generator (25 to 400 MHz)
2.5 V/3.3 V SiGe 1:2 Differential Clock Driver with RSECL Outputs
2.5 V/3.3 V SiGe 1:10 Differential Clock Driver with RSECL Outputs
Triple 4-3-3-Input NOR Gate
9-Bit ECL-TTL Translator
AC Characteristics of ECL Devices
|
Motorola
ONSEMI[ON Semiconductor]
|
| MC100LVEL29DWR2 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20
|
ON Semiconductor
|
| HCS109HMSR HCS109KMSR FN2466 HCS109MS HCS109D HCS1 |
Radiation Hardened Dual JK Flip Flop HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual JK Flip Flop(抗辐射双J-K触发 辐射加固JK触发器拖鞋（抗辐射双JK触发器）
From old datasheet system
Flip Flop, JK, Dual, Rad-Hard, High-Speed, CMOS, Logic
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| SN74LS377D SN74LS377N SN74LS379D SN74LS379DW SN74L |
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
OCTAL D FLIP-FLOP WITH ENABLE HEX D FLIP-FLOP WITH ENABLE 4-BIT D FLIP-FLOP WITH ENABLE
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| MC100LVEL31-D |
3.3V ECL D Flip Flop with Set and Reset
|
ON Semiconductor
|
| MC100LVEL51DR2G MC100LVEL5106 MC100LVEL51MNR4G MC1 |
3.3V ECL Differential Clock D Flip-Flop
|
ONSEMI[ON Semiconductor]
|
| MC100LVEL30-D |
3.3V ECL Triple D Flip-Flop with Set and Reset
|
ON Semiconductor
|
| MC10EP52-D |
3.3V / 5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| MC100EP51DTR2 MC100EP51DT MC100EP51DR2 MC100EP51D |
3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock
|
ONSEMI[ON Semiconductor]
|
| MC100EP51DG MC100EP51DR2G MC100EP51DTG MC100EP51DT |
3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock
|
ONSEMI[ON Semiconductor]
|
| MC100EL30DW MC100EL30DWG MC100EL30DWR2 MC100EL30DW |
5V ECL Triple D Flip−Flop with Set and Reset
|
ONSEMI[ON Semiconductor]
|
| MC100LVEL29-D |
3.3V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
|
ON Semiconductor
|
