| PART |
Description |
Maker |
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74AUP2G80GN 74AUP2G80GD |
Low-power dual D-type flip-flop; positive-edge trigger AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO8
Low-power dual D-type flip-flop; positive-edge trigger 低功耗双D型触发器;上升沿触
|
NXP Semiconductors N.V.
|
| IN74HC109A |
Dual J-K Positive-Edge-Triggered Flip-Flop
|
IK Semiconductor
|
| IN74AC109 |
Dual J-K Positive-Edge-Triggered Flip-Flop
|
IK Semiconductor
|
| LS74 |
Dual D-Type Positive Edge Triggered Flip-Flop
|
Agere Systems
|
| KS74AHCT74 |
Dual D-Type Positive-Edge-Triggered Flip-Flops
|
Samsung Electronics
|
| SN54_74LS109A ON2806 |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
From old datasheet system
|
ON Semi
|
| 74F50728 N74F50728N I74F50728D I74F50728N N74F5072 |
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74F50109 N74F50109N N74F50109D |
Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| DM74S74 DM74S74M DM74S74N |
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
|
Fairchild Semiconductor
|
