| PART |
Description |
Maker |
| MECH2B |
MECH2B Series 10KH ECL Logic Buffered Dual Independent Delays
|
Rhombus Industries
|
| SEL2510E-FREQ |
CRYSTAL OSCILLATOR, CLOCK, 7 MHz - 133 MHz, ECL 10KH OUTPUT
|
PERICOM SEMICONDUCTOR CORP
|
| MC100LVE310FN MC100LVE31006 MC100LVE310FNG MC100LV |
3.3V ECL 2:8 Differential Fanout Buffer(3.3V ECL 2 差分输出缓冲 3.3V的差分ECL 2:8扇出缓冲器（3.3 ECL 2:8差分输出缓冲器）
|
ONSEMI[ON Semiconductor]
|
| MC100EP80906 MC100EP809FAG MC100EPT2106 MC74VHCT02 |
Inverting Octal Bus Buffer; Package: SOEIAJ-20; No of Pins: 20; Container: Rail; Qty per Container: 40 AHCT/VHCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20
PNP DIGITAL TRANSISTOR (BULT-IN RESISTORS)
3.3V ECL Programmable Delay Chip with FTUNE
5V ECL 8-Bit Scannable Register
3.3V ECL Phase?Frequency Detector
Noninverting Buffer / CMOS Logic Level Shifter with LSTTL?Compatible Inputs
Octal D?Type Flip?Flop with 3?State Output
Octal D?Type Latch with 3?State Output
8?Bit Addressable Latch/1?of?8 Decoder CMOS Logic Level Shifter with LSTTL?Compatible Inputs
Octal Bus Transceiver
Quad 2?Channel Multiplexer
Hex Schmitt Inverter
Dual 2?to?4 Decoder/ Demultiplexer
3?to?8 Line Decoder
Quad 2?Input NAND Schmitt Trigger
Quad 2?Input AND Gate
Hex Inverter
Quad 2?Input NOR Gate
3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator
3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
|
ONSEMI[ON Semiconductor]
UTC
|
| DDU12H-75C3 DDU12H-750MC3 DDU12H-XXC3 DDU12H-XXM D |
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) ACTIVE DELAY LINE, TRUE OUTPUT, DSO24
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) ACTIVE DELAY LINE, TRUE OUTPUT, DIP17
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) 5，技术咨询，经过ECL接口固定延迟线（系列DDU12H
|
Data Delay Devices, Inc.
DATA DELAY DEVICES INC
|
| AND8020 AND8020D |
Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure
|
Analog Devices
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| BU4S81 |
Standard Logic LSIs > CMOS logic BU4S Series
Single 2-input AND gate
|
ROHM[Rohm]
|
| BU4584B/BF/BFV |
Standard Logic LSIs > CMOS logic BU4000B Series
|
ROHM
|
| BU4042B |
Standard Logic LSIs > CMOS logic BU4000B Series
|
ROHM
|
| BU4S11 A5800607 |
Standard Logic LSIs > CMOS logic BU4S Series
From old datasheet system
Single 2-input NAND gate
|
ROHM[Rohm]
Rohm CO.,LTD.
|
